RMS Amplitude Error Research Articles

X‐Band 130‐nm CMOS transceiver front‐end with a broadband attenuator design for phased‐array systems

AbstractThis letter demonstrates an X‐band transceiver front‐end in 130‐nm CMOS technology for phased‐array systems. To solve the problem that passive attenuator performance deteriorates significantly in wideband systems, a 6‐bit attenuator with source follower and common‐gate amplifier is proposed. Besides, an 8‐bit vector‐summing phase shifter is implemented in common path to realize the phase coverage of 360° with the least significant bit of 5.625°. In the frequency range of 8–12 GHz, the measured root‐mean‐square (rms) amplitude and phase errors of the attenuator in the transceiver are less than 0.36 dB and 2.2°, respectively. The rms phase and amplitude errors of the phase shifter in the transceiver are less than 4.8° and 0.56 dB, respectively. The whole chip area including pads is 3 × 2.3 mm2.

A 4.5–5.5-GHz Compact 6-bit Phase Shifter With Low RMS Phase and Amplitude Errors Based on Bandpass Structure for High-Power Applications

A 4.5–5.5-GHz Compact 6-bit Phase Shifter With Low RMS Phase and Amplitude Errors Based on Bandpass Structure for High-Power Applications

A 10-20 GHz 6-Bit High-Accuracy Digital Step Attenuator with Low Insertion Loss in 0.15 µm GaAs p-HEMT Technology.

In a beamforming circuit for a modern broadband phased-array system, high accuracy and compactness have received sufficient attention as they are directly related to side lobe level and fabrication cost, respectively. In order to meet the low phase error required, this paper proposed an ultra-broadband 6-bit digital step switched-type attenuator (STA) with capacitive/inductive compensation networks. Compared to the conventional methods, the proposed technique employs an improved simplified T-structure with capacitive compensation networks, which simultaneously achieves low insertion loss and high-accuracy amplitude/phase control. In addition, on-chip level shifting circuit is integrated to avoid complex control schemes. The strategy of prioritizing return loss is adopted to alleviate the performance degradation caused by impedance mismatch after cascade. As a proof-of-principle demonstration, a wideband 6-bit STA with core area of only 0.5 mm × 1.8 mm was designed via 0.15-micrometer GaAs pHEMT technology. It exhibits ultra-broadband operation with a 31.5 dB amplitude tuning range and a 0.5 dB tuning step. The insertion loss of the reference state is 4-5.3 dB. The return loss is better than 15 dB for all the 64 states. The RMS amplitude and phase errors are less than 0.2 dB and 2° over the 10 to 20 GHz.

Variable-Gain Phase Shifter with Phase Compensation Using Varactors

This paper demonstrates a phase compensation technique using varactors for variable-gain phase shifters (VGPSs). The VGPS consists of an I/Q generator and I/Q variable gain amplifiers (I/Q VGAs). I/Q VGAs based on common-emitter stages are enabled to control the gain by adjusting the collector current of the transistor. However, the phase control performance degenerates because the input capacitance varies with the collector current. The proposed phase compensation technique reduces the variation in the insertion phase of the I/Q VGA by adjusting the voltage of the varactor provided at its input and maintaining the input capacitance constant in any gain state. As a result, the VGPS can provide a low phase and amplitude error under phase control. A Ka-band VGPS with the proposed phase compensation technique, fabricated in a 130-nm SiGe BiCMOS process, demonstrates a 0.73° and 0.06 dB improvement in the RMS phase and amplitude error compared with the case without the compensation technique. The VGPS achieves measured RMS amplitude and phase errors of less than 0.19 dB and 0.75°, respectively, in an amplitude control range of more than 20 dB with a frequency range of 28 to 32 GHz.

A DC-87.8-GHz Switched-Type Attenuator With Switched Capacitor Branch in 40-nm CMOS

This paper presents a 5-bit switched-type attenuator (STA) working from DC to 87.8 GHz. In addition to T-type and Π-type attenuation cells with capacitive compensation technique in shunt branch, a new Π-type-based compensation method with switched capacitor branch is proposed, which effectively reduces phase errors at high frequencies without compromising the amplitude errors. The STA in this work is fabricated in 40-nm CMOS technology and the active core area is 0.019 mm, which demonstrates 15.5-dB attenuation range with 0.5-dB tuning step. Across the operational band, the insertion loss of reference state is 1.4-5.3 dB and the return loss is better than 9 dB for all states. From DC to 87.8 GHz, the RMS amplitude and phase errors are below 0.5 dB and 5.4∘ respectively.

A ku-band common-leg transceiver with built-in configurable register in 130-nm CMOS technology for phased-array systems

To solve the bottleneck of amplitude and phase accuracy deterioration caused by process and unpredictable errors, this paper proposes a Ku-band common-leg transceiver with built-in configurable register to achieve 64-state amplitude and phase accuracy correction, respectively, by redefining control codes of each state after taping out. Two-stage cascaded variable gain amplifiers (VGAs) and the vector-summing phase shifter (VSPS) with tail current source controlled by DAC are adopted to achieve large amplitude and phase coverage of 31.5 dB with the LSB of 0.5 dB and 360° with the LSB of 5.625°, respectively. According to the measurement results, in the frequency range of 14–18 GHz, the chip has amplitude accuracy with the root mean square (rms) error of ＜ 0.4 dB, while the rms phase error is ＜ 5.3°. The phase shifting accuracy is measured to be ＜ 2.2°, while the rms amplitude error is ＜ 0.67 dB. The receiving and transmitting channels have reference gain of 3.6–6 dB and 8–10.4 dB, respectively. The whole transceiver occupies 3 × 2.3 mm2 chip area including pads.

A 2.4 GHz low-power and compact 3-bit active phase shifter utilizing miller capacitance

A low-power and compact 3-bit active phase shifter is designed and implemented in a 22 nm FDSOI CMOS process. A modified inverter-based topology, which takes advantage of miller capacitance, is used to create a compact and low-power solution, resulting in ∼10× and ∼90× reduction in the power and chip area, respectively, for a given phase shift, compared to the standard inverter-based topology. At the same time, the proposed phase shifter exhibits less sensitivity to device mismatch. The proposed design measures ∼0.004 mm2, consumes 1.8 mW, and delivers up to 65°of phase shift with RMS phase and amplitude error of 3.85°and ±0.34 dB, respectively. The measured die-to-die variation is also confined to ±6.2°, which is <10% of the full range.

A 2.2–4.2-GHz Wideband Analog Phase Shifter MMIC With Low RMS Phase/Amplitude Error

This letter presents a 2.2–4.2-GHz 360° continuous-tuned phase shifter (PS) using the Gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) technology. A new method for broadband analog PS design based on a tunable low-pass network (LPN), a tunable high-pass network (HPN), and a magnetically coupled all-pass network (MCAPN) configuration is proposed to achieve uniform phase shifting and flat amplitude response at the same time for each phase-shifting state. The fabricated PS demonstrates a low average insertion loss (IL) of 4.9 dBC a low root-mean-square (rms) phase error of less than 5.5°, and a low rms amplitude error of less than 0.47 dB between 2.2 and 4.2 GHz. The proposed analog PS has the most flattened phase performance compared with previously reported pass PSs over a wide bandwidth.

An 11-15GHz multifunctional MMIC with 1.7° RMS phase error, 26.5dBm P&lt;sub&gt;sat&lt;/sub&gt; and &gt;30% PAE for T/R module

This paper presents an 11-15GHz MMIC multifunction chip (MFC) with phase and amplitude control. The chip is based on the common-leg structure and comprises a phase shifter (PS), attenuator (ATT), T/R switch, gain compensation amplifiers (AMPs), driver stage AMPs and parallel control circuits. In the 11-15GHz bandwidth, measurements show that the gain and saturation power (Psat) are higher than 21.5dB and 26.5dBm, while the efficiency is more than 30% in TX mode. In RX mode, the small signal gain is more than 10.2dB, the NF is less than 9.8dB, and output 1dB power (OP1dB) is more than 8.5dBm. The measured minimum RMS phase and amplitude errors are 1.7° and 0.45dB, respectively.

A 17.7–19.2-GHz Receiver Front End With an Adaptive Analog Temperature- Compensation Scheme

This article presents an eight-element 17.7–19.2-GHz receiver front end with 1–2 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes a temperature-compensation variable-gain amplifier (TC-VGA) to minimize the temperature-induced gain variation. The concept of the proposed TC-VGA and the realization of corresponding adaptive analog control are introduced in detail. The front-end architecture and circuit-level design to enable a flat wideband gain response, precise phase and amplitude control, low power consumption, and adaptive analog temperature compensation are presented. Wafer probing is conducted to measure the performance of the receiver front end. The measured gain-temperature coefficient is ±0.005 dB/°C from −15°C to 85 °C at 17.7–19.2 GHz, while the counterpart without temperature compensation is −0.1 dB/°C. The chip demonstrates a 28-dB power gain, a 26% 3-dB fractional bandwidth, a 3.2–4.1-dB noise figure (NF), and a −27.4-dBm input 1-dB gain compression point (IP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {1\,dB}}$ </tex-math></inline-formula> ) for each element. In addition, each channel provides 7-bit phase-shifting resolution and 6-bit attenuation for a 15.75-dB gain range with a <1.5° root-mean-square (rms) phase error, and a < 0.22-dB rms amplitude error. The chip occupies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.65\times2.77$ </tex-math></inline-formula> mm2 area with pads, equivalent to 1.61 mm2 per element (for two beams), and consumes 37.2 mW per element per beam. To the best of our knowledge, the receiver front end demonstrates the minimum gain variation with temperature among silicon RF-beamforming front ends.

A 110–145-GHz SiGe HBT D-Band Vector Modulator Phase Shifter Utilizing Differential Quadrature Delay Lines

This paper presents a 4-bit D-band SiGe vector modulator phase shifter (VMPS). A novel transmission line-based delay line topology is used to generate differential quadrature signals that are weighted by 4 VGAs and cascaded with a buffer amplifier, achieving wide bandwidth, moderate gain, and low power consumption. The VMPS achieves 1.5 dB peak average gain with a 3-dB bandwidth from 110 -145 GHz. The peak RMS amplitude and phase errors are 1.2 dB and 8.5∘, respectively, and the circuit consumes 20.3 mW of average DC power from a 1.5 V supply. To the authors best knowledge, the presented D-Band vector modulator phase shifter achieves the widest fractional bandwidth of any mm-Wave vector modulator phase shifter implemented in silicon.

Novel Passive Vector-Sum Amplitude-Variable Phase Shifter With Integrated Reconfigurable Filtering Function

In this article, a novel passive vector-sum amplitude-variable phase shifter with integrated reconfigurable filtering function is proposed for the first time. It is constructed using conventional trisection filtering topology, with all the couplings between adjacent resonators being implemented with controllable mixed electric&#x2013;magnetic couplings. This not only achieves a reconfigurable filtering response but also forms an intrinsic <inline-formula> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> signal generator inside the filter, which can be directly utilized to achieve continuous phase control based on the vector-sum mechanism. In such a manner, an integrated filtering phase shifter (FPS) without the need for an extra <inline-formula> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> generation network and individual filtering device is obtained. By properly choosing the coupling types and coupling strengths between adjacent resonators, a continuous phase control from 0&#x00B0; to 360&#x00B0;, covering the full four quadrants, is successfully realized. Closed-form equations associating the circuit parameters and insertion phase at center frequency are deduced, providing a quantitative theoretical guideline for determining the parameters of the FPS. Subsequently, a novel tuning mechanism for independent <inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula>-factor and resonant frequency control of the resonator is proposed and applied in the circuit to further exploit the amplitude control ability of the phase shifter. Measured results show that the proposed amplitude-variable FPS is capable of achieving a continuous phase control range of 360&#x00B0; and an amplitude control range of 10 dB within a center frequency tuning range of 0.75&#x2013;0.95 GHz. The measured root-mean-square (rms) amplitude error and the rms phase error are less than 2.58 dB and 8.45&#x00B0;, respectively.

A Compact 6-bit Phase Shifter in 65 nm RF CMOS Technology for ISM Band

We presented a 6-bit switched-network type phase shifter, which was implemented in Samsung 65nm RF CMOS technology. The phase shifter was designed with lumped-element filter topologies using inductors and capacitors for compact size. For 64 states, in the frequency of 2.12 GHz - 2.51 GHz, measured insertion loss was -9.7±1.5 dB. The input and output return loss were above 8.2 dB and 10 dB, respectively. The rms phase error and rms amplitude error were less than 3° and 0.87 dB, respectively. The chip size with including pads was 1.4 × 0.81 mm².

A Calibration Scheme for 24–28-GHz Variable-Gain Phase Shifter in 65-nm CMOS

This brief presents a 24–28-GHz variable-gain phase shifter (VG-PS) and a geometric-projection-based three-point calibration scheme. The VG-PS achieves a 360° phase-shifting range with a 6-bit resolution and an 8-dB gain-tuning range with a 0.25-dB step size. The proposed calibration scheme achieves the optimal control codes directly from only three measurements to optimize the amplitude and phase precision and saves the need for I/Q calibration. The chip is fabricated in a 65-nm CMOS process, occupies a 0.27-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area, and consumes 31.9 mW. The measured gain is −7.4 dB at 24–28 GHz, and the input 1-dB gain compression point (IP1dB) is 0.27 dBm at 26 GHz. By using the three-point calibration scheme, the measured root-mean-square (rms) amplitude and phase errors across 64 phase states at the maximum gain are improved from 0.8 dB/9° to 0.25 dB/1.4°, respectively. The measured rms amplitude and phase errors across 32 gain states are less than 0.06 dB/0.78°, respectively.

Design Methodology for a Wideband, Low Insertion Loss, Digital Step Attenuator in SiGe BiCMOS Technology

This paper presents a wideband, low insertion loss, high attenuation range digital step attenuator (DSA) implemented using SiGe HBTs. In a switched-type topology, the off-state capacitances (COFF) in both reference and attenuation states cause different poles and zeros, which trigger amplitude and phase errors and limit the operating bandwidth. To achieve wide bandwidth, methods to relocate poles and zeros to the highest possible frequencies in both states are investigated. In the reference state, minimizing the size of the shunt switching transistors extends the bandwidth. In the attenuation state, switching in a capacitor at the base of an anti-parallel (AP) SiGe HBT pair series switch reduces the effective COFF, enhancing the bandwidth. The proposed techniques facilitate the realization of a 16-dB attenuator cell to support wide bandwidth and offer lower insertion loss than conventional cascaded 8-dB cell designs. Fabricated in 130-nm SiGe BiCMOS technology, the proposed DSA with an attenuation range of 31.5 dB in 0.5 dB steps operates from DC to 67 GHz and achieves an insertion loss lower than 7.8 dB. The RMS amplitude error is less than 0.4 dB above 1 GHz, while the RMS phase variation is less than 13.1∘.

A 2.4–4-GHz Wideband 7-Bit Phase Shifter With Low RMS Phase/Amplitude Error in 0.5-μm GaAs Technology

This article presents a 2.4–4-GHz wideband 7-bit switch-type phase shifter (STPS) with a switch driver. Three switch-type phase shifting topologies are employed for the design of the phase shifter (PS), including the switched <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L/C$ </tex-math></inline-formula> structure, T-type structure, and high-/low-pass network. For minimizing the phase and amplitude deviations, an improved T-type structure with a switched filter structure has been proposed to boost the performance of the PS. Besides, a phase compensation cell also has been adapted to further decrease the phase error of the STPS. Based on the topology choice of each cell and the amplitude compensation among cells, a systematic design method is developed to extend the bandwidth of the PS. The proposed 7-bit STPS was implemented in the 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. The measured root-mean-square (rms) phase error of the proposed STPS is less than 3.1° from 2.4 to 4 GHz and less than 1.5° at 2.8–3.7 GHz. The average insertion loss (IL) is 4.5–4.9 dB with an rms amplitude error of less than 0.34 dB. IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> is about 30 dBm. To the best of our knowledge, this PS achieves the highest resolution and the lowest rms amplitude error among the published GaAs/GaN PSs over a similar frequency band. The IL, bandwidth, and rms phase error of the proposed PS also show good performance.

15～45 GHz 고해상도 소형 분산형 디지털 감쇠기

This paper describes the design and measurement of a compact distributed digital attenuator using multi-state cells. The attenuator consists of four multi-state cells with different attenuation states. To improve linearity, a stacked-FET topology, in which four transistors are stacked, is applied to the parallel transistors of multi-state cells. In addition, grounded T-lines are inserted to the source of parallel transistors to compensate the phase error. The size of parallel transistors is optimized to implement a 0.5-dB attenuation step and to remove the coupling effect of the previously proposed compact distributed digital attenuator. The attenuator showed a measured 14-dB maximum attenuation range and 0.5-dB attenuation step in a frequency range of 15～45 GHz. The RMS amplitude error and RMS phase error were 0.1～1.4 dB and 1.7～4°, respectively.

A DC–28-GHz 7-Bit High-Accuracy Digital-Step Attenuator in 55-nm CMOS

This letter presents an ultrawideband 7-bit digital-step attenuator (DSA). Capacitive compensation technique is utilized to improve the amplitude and phase accuracy and enable wideband operation. The attenuator is implemented in a 55-nm CMOS process and occupies 0.044-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. It demonstrates a 15.9-dB attenuation range with a 0.125-dB step size. The measured insertion loss (IL) is 2.7–6.6 dB at dc–28 GHz and the rms amplitude and phase errors of four measured chips are < 0.15 dB and <0.8°, respectively. The return loss is better than 12 dB for all the 128 attenuation states. To the best of our knowledge, this chip demonstrates the highest attenuation accuracy and minimum phase variation among silicon-based DSAs with a similar dynamic range.

Topology selection of switch‐type phase shifter units for wideband Ka‐band 5‐bit phase shifter with low RMS errors

AbstractThis article discusses different topologies of switch‐type phase shifter units and the effects of such units on phase accuracy and loss variation for wideband operation. It is observed that the optimal selection of topology depends on the value of phase shift. This article discusses a Ka‐band 5‐bit switch‐type phase shifter MMIC with T‐type high‐pass topology, T‐type low‐pass topology, and high‐pass/low‐pass switched‐path‐type topology. This circuit was implemented through a 65‐nm CMOS process. This phase shifter has low RMS phase error of 2.4°–6.2° and low RMS amplitude error of 0.48–0.66 dB over the 32–41 GHz.

A Wideband Compact 5-Bit Phase Shifter With Low Loss and RMS Errors for 5G Applications

This letter presents a differential 5-bit switch-type phase shifter (PS) that is based on a 65-nm CMOS process. This PS uses a new differential PS unit, which includes a high-pass state and a low-pass state. The strengths of this PS unit include low-phase error and low-amplitude error between two states, which can effectively improve the performance of the entire 5-bit PS. The fabricated 5-bit PS has a low average insertion loss of <8.0 dB, low root mean square (rms) phase error of <5.9°, and low rms amplitude error of <0.22 dB in 35–41.9 GHz. It also has a compact size of 0.125 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .