Rm Rms Research Articles

A High-Voltage SiC-Based Boost PFC for LED Applications

This paper reports a single-stage grid-supplied boost converter with power factor correction for light-emitting diode (LED)-applications using Silicon-Carbide (SiC) and operating at the boundary between continuous and discontinuous conduction modes to reduce switching losses. The converter is supplied by a 230 $V_{{\rm RMS}}$ grid voltage, and attains 1200-V dc at the output port, where a-spot of 320 LEDs connected in series is supplied at constant current. The sliding-mode control theory is employed to analyze the switching regulator dynamics, assuring the system stability. The controller is easily implemented by means of a hysteretic comparator avoiding the risk of modulator saturation. The converter can operate in a normal mode, in which all the input current semicycles are employed, and in a burst mode where only a fraction of all the current semicycles is used. The power switch is realized with silicon carbide (SiC) devices to improve the performance of low-power -grid -supplied LED-based lighting systems. The experimental results are in perfect agreement with the theoretical predictions and demonstrate the feasibility of the proposed approach.

A Digital Predictive Peak Current Control for Power Factor Correction With Low-Input Current Distortion

A digital predictive peak current control (PPCC) employing the adaptive slope compensation is proposed in this paper. The PPCC precisely predicts the peak current reference with the adaptive slope compensation according to operation regions and load conditions. Thereby, the PPCC can control the peak inductor current, and it significantly reduces the total harmonic distortion compared to that of the conventional digital average current control with duty ratio feed-forward which is widely used. In addition, parts of the PPCC are implemented by utilizing the internal high-resolution ramp generator and comparator of a digital signal processor without external components. The principle and analysis of the PPCC are presented, and the performance and feasibility are verified by experimental results with universal input ( $90\; {\rm V}_{\rm rms} \sim 260\; {\rm V}_{\rm rms}$ ) and $750\; {\rm W}-400\; {\rm V}$ output laboratory prototype.

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional jitter at the front-end, not only magnitude and bandwidth but also group-delay responses are considered. The AD-CDR employs an LC quadrature digitally controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 ps $_{\rm rms}$ and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 $\mu\hbox{A} _{{\rm pk}\mathchar702D {\rm pk}}$ for a bit error rate of $ {10^{ - 12}} $ at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm $^{2}$ and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and <formula formulatype="inline"><tex Notation="TeX">$\gamma $</tex></formula>-Ray Spectrum Analyzer

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and $\gamma $ -ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC $0.35 - \mu \hbox{m}$ mixed-signal CMOS technology, the die size of the prototype chip is $2.2~\hbox{mm} \times 4.8~\hbox{mm}$ . At room temperature, the equivalent noise level of a typical channel reaches $133~\hbox{e}^ - ({\rm rms})$ with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than $ \pm 2\% $ and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a $\gamma $ -ray spectrum, the energy resolution is 1.8% at the 662-keV line of $^{137}{\rm Cs}$ source.

Isolated AC/DC Offline High Power Factor Single-Switch LED Drivers Without Electrolytic Capacitors

Energy-efficient residential lighting such as household light-emitting diode (LED) lamps with ac input require an ac/dc converter (or driver) with large output capacitance to minimize the low frequency LED current ripple. The energy storage capacitor used in the conventional ac/dc LED driver is usually an electrolytic capacitor due to its low cost and high energy density. However, the average lifetime of an electrolytic capacitor is at least 2–3 times less than that of an LED device. Hence, the potential lifetime of the LED lamp is significantly affected by the presence of the electrolytic capacitor in the driver circuit. In this paper, two novel isolated single-switch ac/dc high power factor LED drivers without using any electrolytic capacitors are proposed. In the proposed circuits, the energy storage capacitor is moved to the rectifier side, with a three-winding transformer used to provide isolation; input power factor correction as well as to store and provide the required energy to the output. As a result, the energy storage capacitance is significantly reduced, which allows film capacitor to be used to replace the conventionally used electrolytic capacitors. The circuit’s operating principles and its characteristics are described in this paper. Simulation and experimental results are given on a 120 $\text{V}_{\rm rms}$ , 12 W prototype to confirm that a power factor of at least 0.96 is achieved.

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS

Spread-spectrum clocking is an established approach to mitigate electromagnetic interference (EMI) of digital circuits, by intentionally sweeping the clock frequency. In this way, the energy of each clock harmonic is spread over a larger bandwidth, thereby reducing the peak of the interfering spectrum. This paper describes an highly flexible all-digital spread-spectrum clock generator (SSCG) realized with a standard-cells design flow. The developed circuit supports discontinuous frequency modulation profiles (with improved EMI reduction capability) and features reduced output jitter, due to delay interpolators and digital compensation of delay path asymmetries. The proposed SSCG is ideally suited for complex system on chips applications, having programmable spreading parameters, frequency synthesis capability and reduced recovery time to support local standby modes. The SSCG is implemented in bulk 28 nm CMOS technology, presents a maximum working frequency of 3.3 GHz and less than 3.2 ps $_{\rm rms}$ output jitter. The measured peak level reduction of the clock power spectrum, at 1.0 GHz output frequency, is 27.0 dB with a 10% modulation depth. The power dissipation is 29.3 mW @ 3.3 GHz and the area occupation is 0.031 mm.

Core formation in dwarf haloes with self-interacting dark matter: no fine-tuning necessary

We investigate the effect of self-interacting dark matter (SIDM) on the density profiles of $V_{\rm max} \simeq 40~km~s^{-1}$ isolated dwarf dark matter halos -- the scale of relevance for the too big to fail problem (TBTF) -- using very high-resolution cosmological zoom simulations. Each halo has millions of particles within its virial radius. We find that SIDM models with cross sections per unit mass spanning the range \sigma/m = $0.5 - 50$ $cm^2~g^{-1}$ alleviate TBTF and produce constant density cores of size 300-1000 pc, comparable to the half-light radii of $M_\star$ ~ $10^{5-7}$ $M_\odot$ dwarfs. The largest, lowest density cores develop for cross sections in the middle of this range, \sigma/m ~ $5-10~cm^2~g^{-1}$. Our largest SIDM cross section run (\sigma/m = $50~cm^2~g^{-1}$) develops a slightly denser core owing to mild core-collapse behavior, but it remains less dense than the CDM case and retains a constant density core profile. Our work suggests that SIDM cross sections as large or larger than $50~cm^2~g^{-1}$ remain viable on velocity scales of dwarf galaxies ($v_{\rm rms}$ ~ $40~km~s^{-1}$). The range of SIDM cross sections that alleviate TBTF and the cusp/core problem spans at least two orders of magnitude and therefore need not be particularly fine-tuned.

PTFE Vapor Contribution to Pressure Changes in High-Voltage Circuit Breakers

A transient magneto-hydrodynamic model based on @Ansys-Fluent software applied on a high-voltage circuit breaker (HVCB) geometry is presented. The model is turbulent ( $\kappa $ – $\varepsilon $ realizable model), and radiation is taken into account by a hybrid model (Discrete Ordinates Method and P1). The insulating medium is SF6, and current $I_{\rm rms}=25$ kA. An ablation model based on the literature was applied to represent the ablation of the Polytetrafluoroethylene (PTFE) walls. The theoretical and experimental results (pressure, ablation rate, and voltage drop variation) are presented and compared. Several cases were considered: no ablation (ceramic walls), ablation only from downstream parts, and ablation from upstream parts of HVCB walls. The corresponding pressure variations are presented. In order to explain the pressure increase, some additional quantities such as mass flow rate and energy integrated into one section of the heating channel are given. The results show that even if the mass of PTFE ablated is small, the pressure increase is due to the energy input from the vapor.

ON THE BLACK HOLE MASS—X-RAY EXCESS VARIANCE SCALING RELATION FOR ACTIVE GALACTIC NUCLEI IN THE LOW-MASS REGIME

Recent studies of active galactic nuclei (AGN) found a statistical inverse linear scaling between the X-ray normalized excess variance $\sigma_{\rm rms}^2$ (variability amplitude) and the black hole mass spanning over $M_{\rm BH}=10^6- 10^9\ M_{\odot}$. Being suggested to have a small scatter, this scaling relation may provide a novel method to estimate the black hole mass of AGN. However, a question arises as to whether this relation can be extended to the low-mass regime below $\sim10^6\ M_{\odot}$. If confirmed, it would provide an efficient tool to search for AGN with low-mass black holes using X-ray variability. This paper presents a study of the X-ray excess variances for a sample of AGN with black hole masses in the range of $10^5- 10^6\ M_{\odot}$ observed with {\it XMM-Newton} and {\it ROSAT}, including data both from the archives and from newly preformed observations. It is found that the relation is no longer a simple extrapolation of the linear scaling; instead, the relation starts to flatten at $\sim10^6\ M_{\odot}$ toward lower masses. Our result is consistent with the recent finding of \citet{L15}. Such a flattening of the $M_{\rm BH}-\sigma_{\rm rms}^2$ relation is actually expected from the shape of the power spectrum density of AGN, whose break frequency is inversely scaled with the mass of black holes.

Paralleled Three-Phase Current-Source Rectifiers for High-Efficiency Power Supply Applications

This paper presents the paralleling operation of three-phase current-source rectifiers (CSRs) as the front-end power conversion stage of data center power supply systems based on 400- $\hbox{V}_{\rm dc} $ power delivery architecture, which has been proven to have higher efficiency than traditional ac architectures. A control algorithm of paralleled three-phase CSRs is introduced to achieve balanced outputs and individual rectifier module hot swap, which are required by power supply systems. By using silicon carbide (SiC) power semiconductors, SiC MOSFETs, and Schottky diodes, the power losses of the front-end stage are reduced, and the power supply system efficiency can be further increased. The prototype of a 19-kW front-end rectifier to convert 480 $\hbox{V}_{{\rm ac},{\rm rms}}$ to 400 $\hbox{V}_{\rm dc} $ , based on three paralleled three-phase CSRs, is developed. Each CSR is an all-SiC converter and designed for high efficiency, and the front-end stage full-load efficiency is greater than 98% from experimental tests. The balanced outputs and individual converter hot swap are realized in the hardware prototype too.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and $\Delta \Sigma $ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of $-$ 104 dBc/Hz and 1.5 ps $_{\rm rms}$ integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of $-$ 225.8 dB.

A Simple Average Current Control With On-Time Doubler for Multiphase CCM PFC Converter

This paper proposes a new modulated carrier control method for an interleaved continuous conduction mode (CCM) power factor correction (PFC) boost converter. The proposed method allows precise sinusoidal line current shaping for a PFC boost converter operating in CCM. This is accomplished by simply comparing modulated carrier signal with switch current, such that inner current loop compensation design and rectified line voltage sensing are not required. The proposed control method greatly simplifies current sensing and control circuitry of multiphase converters since average current control is available by just sensing the switch current for each module. This also enables simple current balancing between parallel converters by employing modulated carrier signals with same amplitude. The principle of the control method is presented. The performance of the proposed control method is experimentally verified on a 600-W PFC converter. The measured power factor remains above 94.9% down to 20% of a full load for $110\hbox{-}V_{\rm rms}$ and $220\hbox{-}V_{\rm rms}$ line voltages. The line current harmonics also meet the IEC61000-3-2 Class D standard.

Filament Power Supply for Electron Beam Welding Machine

This paper describes the design of a 255-W (17 $\hbox{V}_{\rm rms}$ , 15 $\hbox{A}_{\rm rms} $ ) filament power supply for a 15-kW electron beam welding (EBW) machine. Simulations and results are also included. The filament of the EBW machine consists of a wire, which is heated by the current flowing through it. Although the filament power supply voltage is low (around 17 V) , it is not grounded. In fact, it is displaced $-$ 60 kV dc with respect to ground. Hence, the filament power supply has to be properly isolated. On the other hand, a well-regulated filament power supply is essential for maintaining the stability of the cathode temperature and, consequentially, the lifetime of the filament. In this way, a control method based on the primary voltage is presented, avoiding any feedback loop from the secondary side. The design process and the simulation and experimental results are included in order to verify the control strategy proposed.

Bulk Switching Instrumentation Amplifier for a High-Impedance Source in Neural Signal Recording

Flicker noise is the most crucial issue in an instrumentation amplifier (IA) for neural recordings because low-frequency neural signals overlap with the frequency of the amplifier's flicker noise. A Chopping technique, often used to reduce the flicker noise, is not desirable for high-impedance input sources due to the charge injection and clock feedthrough from the MOSFETs of the input chopper to the signal source, resulting in a significant increase in the total input-referred noise. Whereas MOSFETs have less flicker noise at the moment of turning on, and the intrinsic flicker noise can be then reduced by turning on and off the MOSFETs in the IA. This brief proposes a bulk switching IA, which can avoid the input current noise. A prototype IA is implemented in a 65 nm CMOS occupying 0.053 $\hbox{mm}^{2}$ , and it achieves the input-referred noise of 0.74 $\mu\hbox{V}_{\rm rms}$ (local field potential) for 100 k $\Omega$ source impedance, a 3.3 times reduction compared with that of the chopper IAs, while consuming only 3.96 $\mu\hbox{W}$ from a 1.2 V supply.

Estimating the effective viscosity of bubble suspensions in oscillatory shear flows by means of ultrasonic spinning rheometry

We have proposed a novel methodology using ultrasonic velocity profiling to estimate the effective viscosity of bubble suspensions that are accompanied by non-equilibrium bubble deformations in periodic shear flows. The methodology was termed “ultrasonic spinning rheometry” and validated on measurement of the effective viscosity of particle suspensions that has a semi-empirical formula giving good estimation of the actual viscosity. The results indicated that the proposed technique is valid for particle volume fractions below 3.0 %. Applying this to bubble suspensions suggested that the effective value of temporal variations in the capillary number, $$\hbox{Ca}_{\rm rms}$$ , is an important indicator to distinguish regimes in estimating the effective viscosity: Unsteady flows having larger $$\hbox{Ca}_{\rm rms}$$ number than the critical capillary number for the deformation of bubbles are categorized into Regime 2 that includes both highly unsteady conditions and large steady deformation of bubbles.

A 3–25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA

A 3–25 Gb/s four-channel receiver with noise-canceling transimpedance amplifiers and power-scalable limiting amplifiers is presented. It is fabricated in a 40-nm CMOS process. Each channel provides an overall gain of 64 $\hbox{dB}\cdot \Omega$ . The measured input integrated noise is 2.7 $\mu\hbox{A}_{\rm rms}$ , and the measured bit error rate is $ for a 25-Gb/s pseudorandom bit sequence of $2^{7}-1$ . The power consumption is 103 mW per channel from a 1.3-V supply. The total area is 1.16 $\hbox{mm}^{2}$ .

Implementation of a DC-Side Class-DE Low-<formula formulatype="inline"><tex Notation="TeX">$\bm{d\upsilon/ dt}$</tex> </formula> Rectifier as a PFC for Electronic Ballast Application

An analysis and design of a single-stage electronic ballast with a dc-side Class-DE low- $d\upsilon/dt$ resonant rectifier is studied in this paper to improve a poor power-factor and low line harmonic. The power-factor correction is achieved by utilize an output characteristics of a Class-DE rectifier, which is inserted between the front-end bridge rectifier and the bulk-filter capacitor. The design procedure is based on the principle of the Class-DE rectifier, which also ensures more accurate results and the proposed scheme provided a more systematic and feasible analysis methodology. The active switches can be operated under the soft-switching condition. By employing an electromagnetic interference filter after bridge rectifier, the standard-recovery diode for bridge rectifier can be employed, the cost can be reduced, the conduction angle of the bridge-rectifier diode current was increased, and low line harmonic distortion and a power factor near unity were achieved. The dc-side Class-DE rectifier is driven by a high-frequency current source, which is obtained from the square-wave output voltage of the Class-D series–parallel resonant inverter through an LC-series circuit. A prototype of the ballast, operating at an 84-kHz fixed frequency and a 220-V $_{\rm rms}$ , 50-Hz line voltage, was utilized to drive a T8–36 W fluorescent lamp. The validity of this approach was confirmed by simulation and experimental results.

Displacement Measurement With a Self-Sensing MEMS Electrostatic Drive

This letter outlines a simultaneous actuation and displacement sensing technique applied to a microelectromechanical system (MEMS) electrostatic drive. Using the same electrostatic drive for both actuation and sensing allows more die space to be dedicated to the electrostatic drive, increasing the effective transduction efficiency of both functions and simplifying the mechanical design. Displacement sensing is performed with capacitive measurement implemented by incorporating the drive into an LC oscillator. This provides the mapping from displacement-to-capacitance to frequency-to-voltage. The technique was applied to a MEMS nanopositioner and the sensor exhibited no dynamics over the bandwidth of the device. The sensitivity of the sensor was 0.7551 ${\rm V}~\mu{\rm m}^{-1}$ and had a displacement noise floor of 0.00836 ${\rm nm}_{\rm rms}/\sqrt{\rm Hz}$ . $\hfill{[2014\hbox{-}0002]}$

An All-SiC Three-Phase Buck Rectifier for High-Efficiency Data Center Power Supplies

The low power losses of silicon carbide (SiC) devices provide new opportunities to implement an ultra high-efficiency front-end rectifier for data center power supplies based on a 400- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> ${\rm V}_{\rm dc}$</tex></formula> power distribution architecture, which requires high conversion efficiency in each power conversion stage. This paper presents a 7.5-kW high-efficiency three-phase buck rectifier with 480- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{V}_{{\rm ac}, {\rm rms}}$</tex></formula> input line-to-line voltage and 400- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V}_{\rm dc}$</tex></formula> output voltage using SiC MOSFETs and Schottky diodes. To estimate power devices' losses, which are the dominant portion of total loss, the method of device evaluation and loss calculation is proposed based on a current source topology. This method simulates the current commutation process and estimates devices' losses during switching transients considering devices with and without switching actions in buck rectifier operation. Moreover, the power losses of buck rectifiers based on different combinations of 1200-V power devices are compared. The investigation and comparison demonstrate the benefits of each combination, and the lowest total loss in the all-SiC rectifier is clearly shown. A 7.5-kW prototype of the all-SiC three-phase buck rectifier using liquid cooling is fabricated and tested, with filter design and switching frequency chosen based on loss minimization. A full-load efficiency value greater than 98.5% is achieved.

Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier

This paper presents the design and optimization of a nested-Miller compensated, three-stage operational transconductance amplifier (OTA) for use in switched-capacitor (SC) circuits. Existing design methods for three-stage OTAs often lead to sub-optimal solutions because they decouple inter-related metrics like noise and settling performance. In our approach, the problem of finding an optimal design with the best total integrated noise and settling time has been cohesively solved by formulating a nonlinear constrained optimization program. Equality, inequality, and semi-infinite constraints are formed using closed form symbolic expressions obtained by a closed loop analysis of the SC gain stage and the optimization program is solved by using the interior-point algorithm. For the optimization routine, there is no need to interface with a circuit simulator because all significant device parasitics are included in the model. The optimization and modeling steps are general in nature and can be applied to any amplifier or filter topology. Simulation results show that a 90-nm prototype amplifier achieves a $\pm 0.1{\hbox{\%}}$ dynamic error settling time of 2.5 ns with a total integrated noise of 240 $\mu {\rm V}_{\rm rms}$ , while consuming 5.2 mW from a 1-V power supply.