RF CMOS Low Noise Amplifier Research Articles

Design of inductively degenerated common source RF CMOS Low Noise Amplifier

The Low Noise Amplifier (LNA) is the first stage in RF CMOS receivers. The Common Gate (CG) LNA and Inductively Degenerated Common Source (CS) LNA are one of the widely used topologies for realizing RF CMOS receivers. The present work emphasizes a simple and exhaustive search procedure for the synthesis and analysis of CMOS CG and Inductively Degenerated CS LNA circuits. The width (W), gate source voltage ( $$ V_{gs} $$ ) and drain source voltage ( $$ V_{ds} $$ ) of the transistors constitute the design space in the circuit design. The design first involves the use of a circuit simulator (HSPICE) to obtain the small signal parameters of the circuit for various W, $$ V_{gs}$$ , and $$ V_{ds} $$ of the transistors and then to generate a Look-Up Table (LUT) for all design points using the obtained values. This LUT is used to meet the target performance specifications along with appropriate analytical expressions derived from the circuit in a numerical simulator (MATLAB). This will enable one to explore the whole design space quickly and fastly for arriving at the optimal values for the device dimensions, bias voltages and bias currents of the two LNA circuits. The design methodology is demonstrated by designing CG and Inductively Degenerated CS LNA circuits using 90 nm CMOS technology library in which Inductively Degenerated CS LNA gets high gain and low noise figure than CG LNA.

A miniaturized 2.4-GHz CMOS low-noise amplifier using a gate-source coupling technique

In this study, we proposed a miniaturization technique for a differential RF CMOS low-noise amplifier (LNA). The inductors of the input matching network and for the source degeneration are magnetically coupled to minimize the area for the inductors. By adapting this technique in a CMOS LNA, the parasitic resistance induced by both the input and the source degeneration inductors is reduced, improving the noise figure and gain of the amplifier. To verify the feasibility of the proposed technique, we designed the 2.4-GHz differential LNA using 0.13-µm RF CMOS technology. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1836–1838, 2014

5‐Ghz low noise amplifier with ESD protection method using transformer

AbstractIn this study, we propose a 5‐GHz differential RF CMOS low noise amplifier (LNA) with electrostatic discharge (ESD) protection method in the RF input and output using spiral transformers. Spiral transformers are used as the ESD protection elements as well as the components of the input and output matching networks. During an ESD event, the transformers become the path through which the ESD current shunts because the frequency of the ESD is much lower than the operating frequency of the general RF circuit. The designed LNA is implemented using a 0.18‐µm RF CMOS process. The measured ESD survival level is higher than 1.4 kV. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:684–689, 2014

Optimised LNA for wireless link in brain machine interface applications

Presentsed is an optimised design for the RF CMOS low-noise amplifier (LNA) as the analogue front-end circuit for the brain-machine interface's transceiver with an emphasis on the tradeoff between gain, noise and power consumption. A 360 nm cascode LNA operating in 404 MHz of the Medical Implant Communication Service frequency band is designed to demonstrate good performance achievable in the microwatt range. Overdrive voltage of the transistors is approximately 100 mV to exploit the high g m / I D achieving low power consumption, while avoiding performance degradation associated with the subthreshold region.

Design of the Input Matching Network of RF CMOS LNAs for Low-Power Operation

Optimum design of input matching network of CMOS low-noise amplifiers (LNAs) for low-power applications is discussed in this paper. This is done through an investigation of the effect of four different matching methodologies on the gain of radio frequency CMOS LNAs by means of compact analytical expressions. It is demonstrated that methods that convert the MOSFET's input impedance to 50 Omega for power matching are more suitable for low-power applications than methods that create a real 50-Omega resistance at the input of the LNA, such as source inductive degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET's input resistance. The impact of each matching methodology on the noise figure (NF) of the LNA is also discussed in detail and design guidelines for optimum gain-NF performance are developed using analytical models of MOSFET's noise parameters. It is demonstrated that all four methods could achieve very good NF values, provided that the size of active and passive components are chosen carefully based on the given guidelines. Measured results of two monolithic 5.7-GHz LNAs, designed and fabricated in a 0.18-mum CMOS technology, are also presented. The input matching networks of these LNAs are optimized for low-power operation based on the theory presented in this paper. It is experimentally shown that this optimization results in approximately 60% reduction in the dc power consumption and up to 300% improvement in the overall performance of the LNA when compared with some of the most recently published LNAs

Distortion in RF CMOS short-channel low-noise amplifiers

An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-/spl mu/m gate length) RF low-noise amplifiers (LNAs), based on Volterra's series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-/spl mu/m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance C/sub gs/ of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.

Implementation of plug-and-play ESD protection in 5.5 GHz 90 nm RF CMOS LNAs—Concepts, constraints and solutions

Design and implementation of ESD protection for a 5.5 GHz low noise amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as “plug-and-play”, is used as ESD protection for the RF pins. The consequences of design and process, as well as, the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail. Enhancement in the ESD robustness using additional core-clamp diodes is proposed.

Design method for broadband CMOS RF LNA

A design method for a broadband RF CMOS low noise amplifier (LNA) is presented. The shape of the transfer function fits the classical filtering response such as Butterworth or Tchebycheff. This method uses an input matching cell with only parallel LC resonators coupled with admittance inverters realised by series coupling capacitors. An LNA for the 7.2 to 8.6 GHz frequency band designed with this method in a 0.13 µm RF CMOS process shows a 3.9 dB noise figure with a voltage gain of 28 dB at 8 GHz with a power consumption of 3.9 mW and a surface consumption of 0.4 mm2.

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-/spl mu/m CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain.