RF CMOS Devices Research Articles

Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with $L_{\mathrm{ eff}}= 36$ nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for $f_{T}$ , $f_{\mathrm {\mathrm {MAX}}}$ , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively.

THRU-Based Cascade De-embedding Technique for On-Wafer Characterization of RF CMOS Devices

In this paper, an accurate two-port cascade-based de-embedding technique is presented for characterization of RF devices. It uses two and four structures for device structure with symmetrical and asymmetrical layouts, respectively. Specifically, it outperforms the existing de-embedding techniques by showing distinct capability of accounting for both series contact resistance and distributed effects of interconnects. Furthermore, it is designed to overcome the deficiency of existing transmission line-based techniques in dealing with the interconnects of nonuniform line width. To avoid over de-embedding errors in lumped techniques, the deembedding is performed in unique steps with solely THRU structures for better prediction of test fixture parasitic. The proposed technique is verified on THRU line for a wide frequency range from 2 to 50 GHz. It demonstrates better performance over existing transmission line-based technique as evidenced by excellent agreement with electromagnetic simulation result of THRU line. This is further confirmed by validation result on deembedded gain and gate capacitance of 0.13-μm nMOS devices.

A New Millimeter-Wave Fixture Deembedding Method Based on Generalized Cascade Network Model

In this letter, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device. As compared with existing deembedding approaches, it is developed based on unique combinations of two THRU structures that enable efficient deembedding of fixture parasitics without any inaccurate lumped approximation or requirement of known standards. The proposed deembedding technique is validated on 0.13- μm CMOS devices and has been proven to be more accurate than existing lumped and cascade-based deembedding techniques. As a result, it gives deeper physical prediction on transistor gate capacitances and transconductance. Therefore, it is highly suitable to be applied for device characterization at millimeter-wave frequencies.

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.

Gate substrate effect on RF CMOS device noise

The gate substrate effect on RF CMOS device noise is investigated. The gate substrate resistance (Rgb) noise contribution to the total RF device minimum noise figures (NFmin) is obtained. The results show that the gate substrate resistance noise is considerable in a certain frequency range for 90 nm CMOS devices.

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.

VCO phase-noise improvement by gate-finger configuration of 0.13-/spl mu/m CMOS transistors

Using a standard logic process, 0.13-/spl mu/m RF CMOS devices with multifinger gate structure have been fabricated. The flicker noise and minimum noise figure characteristics have been investigated with different gate layout splits, where the device parasitic resistance is the determining factor in this issue. The stripe-shaped gate configuration demonstrates better noise performance, due to the reduction of device gate resistance. In addition, the MOS varactors designed with different gate layouts were used in a 5.2-GHz voltage-controlled oscillator (VCO) design, where the VCO with the stripe-shaped (2 /spl mu/m /spl times/ 36 fingers) gate varactor improved about 6 dB in phase-noise performance at 100-kHz offset frequency than that of square-shaped (8 /spl mu/m /spl times/ 9 fingers) gate varactor.

MEMS for RF Applications

Micro-Electro-Mechanical-Systems (MEMS) technology promises revolution in the various application domains in the 21st century. RF communication systems are expected to be benefited through MEMS technology. The desire for the mobile gadgets to do the computing, communication and customer specific functions dictates that these gadgets should encompass a variety of device capabilities. Along with the sensory and actuating functions that MEMS can accomplish, MEMS can do value addition to the RF CMOS device integration to enable mixed signal System On Chip (SOC) solution. This paper specifically addresses the use of MEMS technology to realize the components of RF subsystem. The possible components include, but not limited to, varactors, inductors, switches, resonators and oscillators.

Stable extraction of linearity (V/sub IP3/) for nanoscale RF CMOS devices

We have proposed an improved and stable algorithm for linearity (V/sub IP3/) extraction by setting an optimized measurement node interval. This algorithm, considering the accuracy of measurement appliances, provides less noisy V/sub IP3/ without loss of details. Adopting it, V/sub IP3/ can be derived satisfying 1% error criterion. Accurate V/sub IP3/ extraction can be a strong help in CMOS performance analysis for the RF applications. Measurements were carried out on a nMOSFET.

Proton tolerance of multiple-threshold voltage and multiple-breakdown voltage CMOS device design points in a 0.18 /spl mu/m system-on-a-chip CMOS technology

The paper presents the results of an investigation of the proton tolerance of the multiple-threshold voltage and multiple-breakdown voltage device design points contained in a 0.18 /spl mu/m system-on-a-chip CMOS technology. The radiation response of the CMOS devices having three different device design configurations are characterized and compared for equivalent gamma doses up to 300 krad(Si), using the threshold voltage, off-state leakage, and effective mobility to assess the dc performance. All three CMOS device configurations show a very slight degradation of threshold voltage and effective mobility with increasing dose. We also present for the first time the frequency response and S-parameters of these RF CMOS devices under proton radiation. The S-parameters and cut-off frequency show little degradation up to 300 krad(Si) total dose. These results suggest that the CMOS devices in this 0.18 /spl mu/m SoC CMOS technology are well-suited for RF circuit applications in an ionizing radiation environment without intentional total-dose hardening.

A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation

A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 μm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.