Reverse Recovery Charge Research Articles

Detection of reverse recovery characteristics of power diodes

A setup was constituted for measuring reverse recovery (RR) waveforms of current I rr and voltage V rr, RR time t rr, RR charges Q rr, as well as the ratio C of absolute value of RR peak voltage V rm to amplitude of reverse biased pulse voltage V r and so on, for power device under test (DUT). Forward pulse current I f and the V r were generated from a central processing unit (CPU). Amplitude of I f was magnified by a transistor, while the scale was regulated via a Darlington array controlling relays for altering different resistors connected to emitter of the transistor to apply on DUT. Pulse of V r was first shaped by a Schmitt trigger and then was magnified by a metal–oxide–semiconductor field-effect transistor (MOSFET), while the edge commutating rate dI f/dt was adjusted through the Darlington controlling relays for changing different inductors linked to drain of the MOSFET to bias on DUT. The waveforms can be observed with an oscilloscope and sampled for further digitally processing. Inputting test parameters via keyboard, calculating and displaying of test results can be controlled by a host CPU. The parameters and metering results can be monitored by a liquid crystal displayer (LCD).

Low Reverse Recovery Charge 30 V Power MOSFET With Double Epi Structure for DC–DC Converters

Low reverse recovery charge solutions are proposed for 30 V power MOSFETs featuring a double epi structure. The parallel connection of a MOSFET and a Schottky barrier diode (SBD) is used to reduce the recovery charge. The breakdown voltage of the SBD area must be enhanced in order to integrate the MOSFET and the SBD on a single chip. Thus, we studied two types of devices using a double epi structure for enhancing the breakdown voltage of the SBD area. One is an integrated single-chip device and the other is an integrated unit cell device. The integrated unit cell device exhibited lower reverse recovery currents than the integrated single-chip device did during the simulations that were conducted. However, the loss calculation of the integrated unit cell device resulted in an increase in loss because of the diode characteristics needed for the greater barrier height of the p−-layer. Therefore, the integrated single-chip device was experimentally investigated. As a result, the surge voltage of the device was reduced by 58%, which enabled for the use of a lower voltage device and a reduction in the device loss.

Minimization of reverse recovery charge and forward voltage of silicon p–i–n diodes

The forward voltage and reverse recovery charge of silicon p–i–n diodes are controlled on the basis of carrier lifetime or carrier injection efficiency to reduce power loss. In this study, the ideal carrier lifetime for minimizing power loss is calculated by theoretical analysis. The ideal carrier lifetime depends on the current density, forward voltage, and trap energy level in the intrinsic layer. A decrease in the current density leads to an increase in the ideal lifetime. In addition, a shallow trap level has similar current dependence on ideal lifetime. Using the appropriate lifetime is important for designing a p–i–n diode, and a shallow trap level can achieve greater ideal current density dependency.

0.34 <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm {T}}$ </tex-math> </inline-formula> AlGaN/GaN-on-Si Large Schottky Barrier Diode With Recessed Dual Anode Metal

A large GaN-Schottky barrier diode (SBD) with a recessed dual anode metal is proposed to achieve improved the forward characteristics without a degradation of the reverse performances. Using optimized dry etch condition for a large device, the electrical characteristics of the device are demonstrated when applying the recessed dual anode metal and changing the recess depths. The device size and channel width are 4 mm2 and 63 mm, respectively. The 16-nm recessed dual anode metal SBD has a turn- on voltage of 0.34 V, a breakdown voltage of 802 V, and a reverse leakage current of $1.82~\mu \text{A}$ /mm at −15 V. The packaged SBD exhibits a forward current of 6.2 A at 2 V and a reverse recovery charge of 11.54 nC.

Thermal analysis and improvement of cascode GaN device package for totem-pole bridgeless PFC rectifier

The totem-pole bridgeless power factor correction (PFC) rectifier has a simpler topology and higher efficiency than other boost-type bridgeless PFC rectifiers. Its promising performance is enabled by using high-voltage gallium nitride (GaN) high-electron-mobility transistors, which have considerably better figures of merit (e.g., lower reverse recovery charges and less switching losses) than the state-of-the-art silicon metal-oxide-semiconductor field-effect transistors. Cascode GaN devices in traditional packages, i.e., the TO-220 and power quad flat no-lead, are used in the totem-pole PFC boost rectifier. But the parasitic inductances induced by the traditional packages not only significantly deteriorate the switching characteristics of the discrete GaN device but also adversely affect the performance of the built PFC rectifier. A new stack-die packaging structure with an embedded capacitor has been introduced and proven to be efficient in reducing parasitic ringing at the turn-off transition and achieving true zero-voltage-switching turn-on. However, the thermal dissipation capability of the device packaged in this configuration becomes a limitation on further pushing the operating frequency and the output current level for high-efficiency power conversion. This paper focuses on the thermal analysis of the cascode GaN devices in different packages and the GaN-based multichip module used in a two-phase totem-pole bridgeless PFC boost rectifier. A series of thermal models are built based on the actual structures and materials of the packaged devices to evaluate their thermal performance. Finite element analysis (FEA) simulation results of the cascode GaN device in a flip-chip format demonstrate the possibility of increasing the device switching speed while maintaining the peak temperature of the device below 125 °C. Thermal analysis of the GaN-based power module in a very similar structure is also conducted using the FEA method. Experimental data measured using the fabricated devices and modules validate the simulation results. The developed new package in a flip-chip configuration enhances the thermal dissipation capability of the cascode GaN device in the stack-die format. The GaN-based power module built using the same packaging structure also demonstrates desirable thermal performance.

GaN FET을 이용한 토템폴 구조의 브리지리스 부스트 PFC 컨버터

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

Accurate Analytical Modeling for Switching Energy of PiN Diodes Reverse Recovery

PiN diodes are known to significantly contribute to switching energy as a result of reverse-recovery charge during turn- off . At high switching rates, the overlap between the high peak reserve-recovery current and the high peak voltage overshoot contributes to significant switching energy. The peak reverse-recovery current depends on the temperature and switching rate, whereas the peak diode voltage overshoot depends additionally on the stray inductance. Furthermore, the slope of the diode turn- off current is constant at high insulated-gate bipolar transistor (IGBT) switching rates and varies for low IGBT switching rates. In this paper, an analytical model for calculating PiN diode switching energy at different switching rates and temperatures is presented and validated by ultrafast and standard recovery diodes with different current ratings. Measurements of current commutation in IGBT/PiN diode pairs have been made at different switching rates and temperatures and used to validate the model. It is shown here that there is an optimal switching rate to minimize switching energy. The model is able to correctly predict the switching rate and temperature dependence of the PiN diode switching energies for different devices.

Theoretical analysis of forward voltage and reverse recovery charge of silicon p–i–n diodes

Silicon p–i–n diodes have attracted considerable attention for their use as many applications. In the light of reducing total power loss, the forward voltage Vf and the reverse recovery charge Qr of silicon p–i–n power diodes are controlled by using two approaches based on control of either carrier lifetime or carrier injection efficiency. In this study, we investigate the effect of the two approaches on the relationship between Vf and Qr for a Si p–i–n diode rated at 200 A/1200 V via theoretical analyses. The magnitude of Vf for a given Qr value depends on rate of current density decreasing dj/dt. In the case of large values of dj/dt, carrier injection control can lead to decrease in Vf and Qr to a greater extent. In contrast, at small values of dj/dt, carrier lifetime control can provide a greater decrease in Vf and Qr.

Development of low-voltage power MOSFET based on application requirement analysis

Low-voltage power MOSFETs based on charge-compensation using a field-plate offer a significant reduction of the area-specific on-resistance. Beside a further improvement of this key parameter, the new device generation takes an in-depth focus on the other device parameters which are essential to the targeted application fields. To allow a high efficiency also in light-load conditions, the power MOSFET not only needs to meet general requirements like low on-resistance, low gate charge and good avalanche capability, but must also have a low output capacitance and low reverse-recovery charge. The paper discusses how the most important of these often conflicting requirements were identified. It is shown that beside the device technology the package contributes significantly to the overall device performance. A new package solution is introduced which is especially suited for high current applications linked to high reliability requirements such as industrial motor drives or servers.

Characteristics and Application of Normally-Off SiC-JFETs in Converters Without Antiparallel Diodes

In this paper, reverse characteristics of vertical-channel SiC-JFETs similar to an equivalent diode are discussed and compared with an actual SiC-SBD. The relationship between the reverse conduction voltage and the applied gate-to-source voltage is extracted along with channel structure of JFETs. Experiments involving operation of normally-off SiC-JFETs in actual converters are then conducted with and without antiparallel SiC-SBDs at different temperatures. The issue of JFET channel mistriggering is observed and evaluated by introducing extra negative gate bias during the switch-off state. Excellent dynamic performance can be obtained with minimal reverse-recovery charge when the SiC-JFET is driven properly. The dynamic losses are then calculated in different conditions. The results indicate that SiC-JFETs can perform the function of antiparallel diodes with minimal performance sacrifice in converters. Furthermore, an actual SiC-JFET-based dc-dc converter with/without antiparallel SiC-SBDs is built to verify the influence of eliminating the external diodes. It is concluded that with slight modification in the gate driver circuit to maintain safety, antiparallel diodes could be eliminated in vertical-channel SiC-JFET-based applications.

AlGaN/GaN-Based Lateral-Type Schottky Barrier Diode With Very Low Reverse Recovery Charge at High Temperature

We have demonstrated the lateral multifinger-type Schottky barrier diode (SBD) with bonding pad over active structure fabricated on the AlGaN/GaN heterostructure prepared on sapphire substrate. The fabricated GaN-SBD with size of 9 mm2 exhibited excellent device characteristics such as forward current of 4.5 A at 1.5 V, leakage current of 6 μA at 600 V, and high breakdown voltage of 747 V. The temperature variations of GaN-SBD for the reverse recovery characteristics are negligible and the value of reverse-recovery charge (Q)rr of GaN-SBD is one twentieth of Si-diode at 175°C.

Cathode-Side Current Filaments in High-Voltage Power Diodes Beyond the SOA Limit

An analysis of the plasma front velocities during turnoff of a power diode is used to explain the differences between the formation and the behavior of cathode-side and anode-side filaments. Device simulations show, how cathode-side filaments may trigger a thermal runaway at the end of a reverse-recovery period of diodes turned off with extremely high current rates operating the diode in a regime far away from the safe operating area. From the transient voltage curve, the analysis of the reverse-recovery charge as a function of the dc-link voltage and an analysis of the turnoff transients in the current-voltage phase space, it is, however, deduced that the appearance of a cathode-side filament by itself does not necessarily lead to diode destruction. The transformation of the initially avalanche-generated filaments into filaments that are essentially driven by thermal mechanism seems to be a further important condition for device destruction.

High‐voltage superjunction VDMOS with low reverse recovery loss

A new design of the high-voltage superjunction VDMOS (SJ-VDMOS) structure is proposed to minimise the reverse recovery losses of the body diode and the noise during the switching process. The key feature of the structure is that a discontinuous P + region in the source is implemented which can decrease the carrier injection efficiency. Numerical results indicate that the reverse recovery charge and the overshoot voltage of the proposed structure is decreased by 76.5% and 52.5%, respectively, compared to the conventional SJ-VDMOS structure, while maintaining the same breakdown voltage.

Analysis of LDMOS for Effect of Fingers, Device-Width and Inductance (Load) on Reverse Recovery

This work demonstrates the effect of fingers, device-width and inductance on reverse recovery of LDMOS by unclamped inductive switching (UIS) circuit simulation for two dimensional (2D) and three dimensional (3D) devices. All the observations have been done for maximum pulse width at which device pass under UIS test. For UIS simulations the failure criteria is taken as the device temperature reaching a critical value of 650K. It has been shown that reverse recovery charge (Qrr) increased linearly with number of fingers, device width and inductance.

Performance of Hybrid 4.5 kV SiC JBS Freewheeling Diode and Si IGBT

The performance of Junction Barrier Schottky (JBS) diodes developed for medium voltage hard-switched Naval power conversion is reported. Nominally 60 A, 4.5kV rated JBS freewheeling diodes were paired with similarly rated Si IGBTs and evaluated for temperature dependent static and dynamic characteristics as well as HTRB and surge capability. The SiC JBS/Si IGBT pair was also directly compared to Si PiN diode/Si IGBT with similar ratings. Compared to Si, the SiC freewheeling diode produced over twenty times lower reverse recovery charge leading to approximately a factor-of-four-reduction in turn-on loss. Alternatively, for equivalent total switching loss, the SiC JBS/Si IGBT hybrid configuration allows for at least a 50% increase in specific switched power density. Reliability testing showed the devices to be robust with zero failures.

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its Ron,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated, and the optimized results with BV of 83 V and Ron,sp of 54 mΩ·mm2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior “Ron,sp/BV" trade-off to the conventional VDMOS (a 38% reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of Ron,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively.

An Experimental Study of High Voltage SiC PiN Diode Modules Designed for 6.5 KV / 1 KA

The paper describes first results of 6.5 kV SiC PiN diode modules which are designed as neutral point valves for medium-voltage power inverters rated for 1000 A. The power module consists of 4 AlN DCB substrates soldered on an AlSiC base plate. Each DCB is equipped with 20 SiC PiN diodes operating in parallel. The total active area of all 80 diode chips is 5.68 cm². At the rated current of 2 x 500A the forward voltage drops from 4.1 V at room temperature to 3.9 V at an averaged junction temperature of 125°C. The switching experiments show a very low reverse recovery charge of about 30 µC only. The conduction loss is comparable to the corresponding 6.5 kV silicon diode whereas the dynamic loss is marginal with respect to the forward conduction loss if the switching frequency is held below 10 kHz.

6.5 kV SiC PiN Diodes with Improved Forward Characteristics

The paper compares static and dynamic characteristics of 6.5 kV SiC PiN diodes fabricated with different p-emitters. The version with the thickest p-emitter (4 µm) showed the lowest forward voltage (3.4 V at 100 A/cm²) and the lowest (negative) temperature coefficient. Forward voltage DC stress tests revealed a stability within the measurement error of the test apparatus (<50 mV). The dynamic performance showed a soft recovery even at 4 kV. The reverse recovery charge Qrr is analyzed for different forward currents and junction temperatures. The dynamic losses of the SiC PiN diode are marginal with view to the application in industrial inverters.

Experimental 4H-SiC junction-barrier Schottky (JBS) diodes

4H-SiC junction-barrier Schottky (JBS) diodes have been fabricated with local p–n junctions under the Schottky contact formed by nonequilibrium diffusion of boron. Static and dynamic characteristics of the JBS diodes are compared with those of similar 4H-SiC Schottky diodes. It is shown that, compared with ordinary Schottky diodes, the JBS diodes have leakage currents that are, on average, a factor of 200 lower at the same reverse bias. The reverse recovery charge is the same for both types of diodes and equal to the charge of majority carriers removed from the n-type base region in switching.

Schottky versus bipolar 3.3 kV SiC diodes

A comparative study of the electrical characteristics of 3.3 kV SiC Schottky barrier (SBD), junction bipolar Schottky (JBS) and PiN diodes is presented. 3.3 kV class 4H-SiC SBD, JBS and PiN diodes have been fabricated with an analogous technology process on similar epi wafers. Diodes have been characterized in forward, reverse and switching mode in the 25 °C–300 °C temperature range. The optimum performance of the diodes depends on the adequate use of the unipolar or bipolar advantages and is established by the final application specifications. In this respect, a reverse recovery charge versus on-resistance diagram for different current densities is also presented. DC stress tests have been performed to investigate the forward voltage drift, related to the formation of stacking faults, during the bipolar mode of operation.