Resistivity Of Silicon Wafer Research Articles

Effects of Silicon Wafer’s Resistivity on Passivation and Devices Performances of Solar Cell

In the manufacture of solar cells, the resistivity of silicon wafers has a crucial impact on their performance. This study investigated the effects of different resistivities on p-TOPCon solar cells. The results indicate that lower resistivity wafers have a higher implied open-circuit voltage (iVoc) value, but higher carrier mobility due to the low resistivity leads to an increase in saturation current density (J0). Conversely, solar cells made on higher resistivity silicon wafers have a lower carrier mobility, leading to slower electron-hole recombination and lower bulk recombination, resulting in the advantage of lower saturation current density and higher minority carrier lifetime. At the same time, simulation shows that as the resistivity increases, the Voc and efficiency increase. However, cost considerations need to be taken into account as higher resistivity silicon wafers are more expensive. Therefore, resistivity between 2 - 3 Ω·cm2 is considered the preferred substrate for solar cells as it offers a better balance between cost and achieving high cell efficiency.

Porous Silicon Fabrication and Surface Cracking Behavior Research Based on Anodic Electrochemical Etching▴

AbstractPorous silicon (PSi) was fabricated based on anodic electrochemical etching, and the relationship between preparation conditions, nanostructure and PSi surface crack behavior were systematically studied. The effects of silicon wafer resistivity (doping concentration), etching time, and etching current density on nanostructure of PSi were investigated. Results indicated that lower resistivity was beneficial to etching process and led to higher porosity with uniform nano‐channels, and surface crack was more intense during drying process. Thickness and porosity of the porous layer are both initially increased and then decreased with increasing etching time. Direction of capillary stress depended on pore geometry, which further affected crack shape (shrinkage or crimp) of surface layer of PSi. Cracking extent was controlled by porosity, that the surface cracking layer began to peel off when the porosity exceeded 70%. Finally, a geometry and porosity‐controlled model was proposed to describe the cracking behaviors of PSi surface layer.

Effect of Silicon Wafer Resistivity on Morphology and Wettability of Silicon Nanowires Arrays

Herein, we prepare vertical and single crystalline silicon nanowires (SiNWs) via a one-step metal-assisted chemical etching method in aqueous NH4HF2/AgNO3 solution. The effects of silicon substrate resistivity and concentrations of NH4HF2 and AgNO3 on the etching process were examined. Two properties were studied, the morphology and the wettability of etched layers. The morphology of the silicon nanowire (SiNW) layers was investigated by scanning electron microscopy (SEM) while the wettability was studied by contact angle measurement system. It was established that the morphology is strongly influenced by etching parameters and their wettability changes from superhydrophilic to hydrophobic.

Contactless determination of doping concentration and resistivity of silicon wafers with cavity ring-down technique

A contactless method for measuring the doping concentration and resistivity of silicon wafers based on cavity ring-down technique was developed and verified experimentally. The doping concentration and resistivity of the silicon wafer in our experiment were calculated to be 1.53 ± 0.47 × 1016 cm−3 and 1.08 ± 0.41 Ω·cm, respectively, by measuring the optical loss caused by the sample, which are consistent with that obtained with conventional four-point probe measurements. The results indicated that the proposed method can be an alternative non-destructive tool for doping concentration and resistivity measurements.

Contactless determination of base resistivity on silicon wafers with highly doped surfaces

In this paper a contactless and non-destructive method for the determination of base resistivity of silicon wafers with highly doped surfaces is introduced. The method is based on photoconductance and photoluminescence measurements. Unlike existing methods for the determination of base resistivity, the proposed method does not require an experimental setup, which simultaneously measures photoconductance and photoluminescence signals synchronized in time. The method is applied to a set of test samples with highly doped surfaces representing a broad variety of samples present in industrial and laboratory environments. The results of the proposed method are compared to reference values which are inductively measured after the removal of highly doped surfaces. An mean absolute error with respect to the reference values below 4% is obtained for the investigated set of samples. This corresponds to a deviation of less than 0.1 Ωcm for typical solar wafers with resistivities below 5 Ωcm. Sources of uncertainties in the proposed method are discussed in detail. From that discussion rules of thumb for a reasonable choice of calibration and test samples are derived. A maximum error of less than 10% is expected if rules of thumb are followed.

直排四探针法测量硅片电阻率及不确定度评定

直排四探针法测量硅片电阻率及不确定度评定

The effects of the silicon wafer resistivity on the performance of microelectrical discharge machining

In this study, the performance of Si wafer machining by employing the die-sinking microelectrical discharge machining technique is reported. Specifically, the machining performance was examined on both high- (1–10 Ω cm) and low-resistivity (0.001–0.005 Ω cm) Si wafers by means of using a range of discharge energies. In this regard, the machining time, material removal rate, surface quality, surface roughness, and material mapping, which are categorized among the important properties in micromachining, have been investigated. In order to analyze the surface properties and to perform the elemental analysis, the scanning electron microscope and energy-dispersive X-ray spectroscopy were used. In contrast, the 3D surface profiler was used to evaluate the roughness of machined surface. The results of this experimental study revealed that the electrical resistivity and discharge energy parameter of microelectrical discharge machining had a great influence on the Si wafer machining performances. The observations in this study indicated a decrease in machining time, high material removal rate, and high surface roughness with an increased discharge energy values. Overall, it was learnt that the minimum amount of energy required to machine Si wafer was 5 μJ for both low and high-resistivity Si. In addition, the highest material removal of 5.842 × 10−5 mm3/s was observed for low-resistivity Si. On the contrary, the best surface roughness, R a, of 0.6203 μm was achieved for high-resistivity Si and it also pointed to a higher carbon percentage after the machining process.

The effect of porosity on energetic porous silicon solid propellant micro-propulsion

Energetic porous silicon is investigated as an actuator for micro-propulsion based on thrust and impulse measurements for a variety of porous silicon porosity conditions. Porosity of 2 mm diameter, porous silicon microthruster devices was varied by changing the concentration of hydrofluoric acid and ethanol in an etch solution, by changing porous silicon etch depth, and by changing the resistivity of silicon wafers used for the etch process. The porosity varied from 30% to 75% for these experiments. The highest mean thrust and impulse values measured with a calibrated Kistler 9215 force sensor were 674 mN and 271 μN s, respectively, with a 73% porosity, 2 mm diameter porous silicon device etched in a 3 : 1 etch solution on a 3.6 Ω cm wafer to a target etch depth of 30 μm. As a result of changing porosity, a 23× increase in thrust performance and a 36× increase in impulse performance was demonstrated. Impulse values were also validated using a pendulum experiment in which the porous silicon microthruster was unconstrained, but several non-linearities in the pendulum experimental setup resulted in less consistent data than when measured by the force sensor for microthrusters at this size scale. These thrust and impulse results complement previous work in determining the effect of porosity on other porous silicon reaction metrics such as flame speed.

Fabrication of silicon nanowires by ion beam irradiation

ABSTRACTSilicon nanowires are becoming more important because of increasing requirements of the small scale and dense integration of devices. We report a top-down fabrication method for silicon nanowires using high-energy ion beam irradiation of bulk p-type silicon followed by electrochemical etching. Silicon nanowires with a diameter of ∼50nm have been fabricated and densely patterned nanowire arrays fabricated in different resistivity silicon wafers. With a suitable support structure, free standing silicon nanowires are also achieved. We investigate results depending on silicon wafer resistivity and location within the irradiated area.

Microfabrication and Characterization of W-Band Planar Helix Slow-Wave Structure With Straight-Edge Connections

A slow-wave structure (SWS) consisting of a planar helix with straight-edge connections and incorporating a coplanar waveguide feed has been designed for operation at W-band and has been fabricated using microfabrication technique. On-wafer cold measurements have been carried out on a number of fabricated SWSs, and the results are reported here for the first time. The parameters measured are return loss, attenuation, and phase velocity, and the results cover a frequency range of 70-100 GHz. Cold-test parameters of the SWS have been also obtained using simulations, and the effects of fabrication, such as surface roughness, have been accounted for by estimating effective conductivity of different parts of the microfabricated structures. The measured and simulated results match well. The effects of silicon wafer resistivity have been also discussed. Planar helical SWSs fabricated in this manner have application in traveling-wave tubes operating at millimeter wave and higher frequencies.

Single-configuration FPP method에 의한 실리콘 웨이퍼의 비저항 정밀측정

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

A combined synthetic&X chart for monitoring the process mean

The Shewhart X chart (or X chart) is widely used to monitor the mean of a quality characteristic x. This chart decides the process status based on the magnitude of the sample mean x and is effective for detecting large mean shifts. The synthetic chart is also a Shewhart type chart for monitoring the process mean, but it utilises the information about the time interval between two nonconforming samples. Here a sample is nonconforming if its x value falls beyond the predetermined warning limits. Unlike the X chart, the synthetic chart is more powerful to detect small shifts. The applications of the X and synthetic charts cover a wide variety of manufacturing processes and production lines, e.g., the monitoring of the mean values of the inside diameter of a piston-ring, the viscosity of aircraft paint, the resistivity of silicon wafers. This article proposes a combined scheme, the Syn-X chart, that comprises a synthetic chart and an X chart. The results of the performance studies show that the Syn-X chart always outperforms the individual X chart and synthetic chart under different conditions. It is more effective than the X chart and synthetic chart by 47% and 20%, respectively, over the wide range of mean shift values in different experiment runs.

Effect of wafer resistivity and HF concentration on the formation of vertically aligned porous silicon

In this study, the mechanism of vertically aligned porous silicon formation was examined. Silicon wafers with various resistivities and electrolytes containing different HF concentrations were used to explain porous silicon formation by the reaction at the silicon/electrolyte interface. Total pore volume increased proportionally to the current applied and anodization time. As the concentration of HF increased, pore depth and total pore volume formed in silicon anodization increased, then decreased beyond the optimum point. At a given applied current, total pore volume formed by anodization increased with an increase in resistivity of silicon wafer, but then decreased. From the mechanism of silicon etching and schematic isoetch contour of silicon suggested in this study, it is concluded that the formation of porous silicon is determined by an accumulation of F − near the silicon/electrolyte interface in silicon anodization.

Examination of Relationship Between Resistivity and Photocurrent Induced Magnetic Field in Silicon Wafers Using Laser SQUID

Using the laser SQUID method, we examined the relationship between silicon wafer resistivity and magnetic field. By irradiating the wafer with a 3.2 W high-power laser beam, we were able to generate a measurable magnetic field perpendicular to the wafer, even for the wafers without p-n junctions. For samples having resistivities of 130 /spl Omega//spl middot/cm or less, we observed magnetic field distributions in the form of concentric circles. Histogram analysis showed that as resistivity decreases, mean value of magnetic field and standard deviation increase. For p-type wafers having resistivities of up to 300 /spl Omega//spl middot/cm, both mean value of magnetic field and standard deviation vary as a power law with respect to resistivity. However, for samples having resistivities of 300 /spl Omega//spl middot/cm or higher, the relationship was saturated, and determining resistivity was difficult. Since the laser SQUID method can be used to measure resistivity without electrical contact, it works well even for wafers with surface oxide films, and does not cause contamination.

ＤＩＯＳ法を利用した合成高分子の質量分析−ＤＩＯＳチップ作製の最適化−

Desorption/ionization on porous silicon (DIOS) is a novel matrix-free variant of laser desorption/ionization (LDI) techniques for mass spectrometry. The DIOS chips are produced by electrochemical etching of silicon wafers under light exposure. In the present report, the optimal conditions, regarding resistivity of silicon wafer, etching current density and etching time, for making DIOS chip with better ionization performance are described. In addition, the DIOS mass spectra of various synthetic polymers including polyethyleneglycol, nonylphenolpolyethoxylate, nonylphenolpolyethoxylatesulfate, polymethylmethacrylate are compared with the matrix-assisted LDI mass spectra.

A Fully Depleted pn-Junction CCD for Infrared-, UV- and X- ray detection

This paper describes the performance of the Fully Depleted pn-junction CCD (pn-CCD) system, developed for ESA's XMM-satellite mission for soft x-ray imaging and spectroscopy in the single photon counting mode in the 100 eV to 10 keV photon range. The 58 mm x 60 mm large pn-CCD array, designed and fabricated at the Semiconductor Lab (Halbleiterlabor) of the Max-Planck-Institut, uses pn-junctions for registers and as backside structure. This concept naturally enables full depletion of the detector volume independent of the silicon wafer's resistivity and thickness, and as such make it an efficient detector for the x-ray region and the infrared. For high detection efficiency in the soft x-ray region and UV, an ultrathin pn-CCD backside deadlayer has been realized. Each pn-CCD-channel is equipped with its own on-chip JFET amplifier which, in combination with the CAMEX-amplifier and multiplexing chip, facilitates parallel readout and fast data rate: the cooled pn-CCD system can be read out at a data rate up to 3 MHz with an electronic noise floor of ENC < 5 e-.

Sheet resistivity of silicon wafers implanted with a high current machine

Silicon wafers, as used in the integrated circuits and semiconductor device industry, have been implanted with all the common dopants using Eaton Corporation's commercially available “NV” series of high current implanters. Most detailed studies of the implanted wafers have focused on using arsenic and boron as dopants since the transport of these dopants in silicon has been found to be more compatible with the trend towards shrinking device dimensions. Four point probe measurements have been taken on implanted wafers with subsequent annealing to indicate the quality and effect of the implant. The variation of sheet resistance with dose and energy have been studied using a machine in standard condition over the range of 10 14 − 10 16 ions/cm 2 and over an energy range of 5–180 keV for arsenic and boron implants into bare wafers and wafers with screen oxides. Dose control at low doses in the Eaton High Current Implanter has been studied over a range of 10 10−10 13 ions/cm 2 using MOS devices and other measurements. Repeatability of the machines has been obtained by tracking the manufacture of over one hundred machines for nearly three years. With the use of an Eaton Standard Test Implant Procedure for each machine before shipment, it has been shown that the dose repeatability can be as good as 2% (including furnace and four point probe variations) for machine to machine. The repeatability within a single machine was found to be better than 0.5%. Arsenic ion beams have shown excellent independence of end station pressure, as may occur during photoresist outgassing or controlled gas leaks. Boron beams have a higher electron capture cross-section than other commonly used beams and require a dose control compensation for high end station pressure implants to give agreement with the low pressure regime. In all cases, dose uniformity across each wafer has also been measured. The variation of uniformity with implant parameters as well as the annealing conditions and target surface properties have been studied.

A planar four-probe test structure for measuring bulk resistivity

A small planar four-probe test structure for measuring the bulk or collector resistivity of silicon wafers was designed and fabricated with a bipolar transistor process. Analogous to a mechanical square array four-point probe, the planar four-probe structure consists of a large-area base diffusion which is broken at four points through which contact is made to the undiffused collector material. A probe spacing of 2.25 mil (57.2 µm) allows the resistivity of the silicon wafer to be measured with good spatial resolution. A correction factor was derived to obtain the true resistivity from measurements on a wafer with finite thickness and a conducting backside, and it is presented along with the correction factors for other cases. The test device was fabricated in silicon wafers whose resistivities ranged from 0.013 Ω. cm to 12 Ω. cm in n-type material and from 0.7 Ω. cm to 30 Ω. cm in p-type material. Planar four-probe resistivity values are compared with mechanical four-probe values taken on the same wafers before fabrication, and the results are generally in agreement within ±3 percent.