Residue Amplifier Research Articles

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply.

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique

A 12-bit 210-MS/s 2-channel time-interleaved analog-to-digital converter (ADC) employing a pipelined-SAR architecture for low-power and high-speed application is presented. The proposed ADC is partitioned into 3 stages with a passive residue transfer technique between the 1st and 2nd stages for power saving and active residue amplification between the 2nd and 3rd stages for noise consideration. Furthermore, a 2.8-bit SAR conversion embedded in the 1st stage also improves the speed and downsizes the required decoupling capacitance of reference voltage. With the foreground calibration, the inter-stage DAC error and gain/offset errors between interleaving channels are resolved. The proposed ADC, fabricated in a 65-nm CMOS technology, consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.5 dB at low input frequencies and 60.1 dB near Nyquist rate. The prototype occupies an active area of 0.48 $\text{mm}^{2}$ and the corresponding FoM is 30.3 fJ/conversion-step.

An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency

A new pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) structure without residue amplifier and timing-interleaving is presented in this brief. Two redistribution digital-to-analog converters (DACs) and comparators are adopted in two stages, with $\mbox{DAC}_1$ for most significant bit (MSB) comparisons and $\mbox{DAC}_2$ for least significant bit (LSB) comparisons. The previous sampled signal is transferred from $\mbox{DAC}_1$ to $\mbox{DAC}_2$ through charge sharing so that previous LSB conversions can operate simultaneously with the next sample and MSB conversions, which increases the conversion speed. With a 0.5 scale factor between two stages and multicomparator offsets, offset calibration has to be obtained to eliminate offset nonlinearity. The number of conversion cycles required by the proposed design is only 6 and sampling requires no extra time, which is 3 cycles fewer than traditional SAR ADC. The behavioral model of the 8b proposed design proves the performance stability with parasitic capacitance variation, capacitor mismatch, offset, and noise errors. An 8b prototype is designed in a 65-nm CMOS technology. The supply voltage is 1.2 V, with a 500-MS/s sampling rate. The circuit simulation results achieve 7.49b ENOB with 1.53-mW power consumption. The simulated FoM is 17 fJ/conv.

An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS

This paper presents a 12-bit 50MS/s asynchronous rail-to-rail Pipeline-SAR ADC. Design optimization is performed to achieve low power and high performance. The ADC consists of a 6-bit coarse SAR ADC, a residue amplifier and a 7-bit fine SAR ADC. A novel highly linear, power efficient switching scheme for the 2nd stage SAR ADC is proposed. The ADC operates asynchronously in order to simplify the design and save power. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC was fabricated in 0.18μm CMOS process with 1.8V power supply range. The proposed SAR ADC achieves 67.01dB SNDR and 77.13dB SFDR with sampling rate up to 50MS/s, corresponding to a figure-of-merit of 110fJ/conversion-step. The proposed ADC core occupies an active area of about 450×700µm2.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter (RSD-ADC) is presented featuring a high signal to noise ratio (SNR), spurious free dynamic range (SFDR) and signal to noise plus distortion (SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC (residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

A new digital background calibration for redundant radix-4 pipelined ADCs by modeling of adaptive filter for linear and nonlinear errors

In this paper a new digital background correction and calibration technique for redundant multi-bit pipeline stages is presented. In this method output voltage of each stage in converter is defined as sum of the ideal product and error signal, which error voltage include of linear non-ideal section or first order error and nonlinearity undesired signal or third order error. Linear error is formed by capacitor mismatch, op-amp offset, comparator offset and finite op-amp gain effects. Nonlinear error is deformed the output voltage depend on the nonlinear results of open loop residue amplifier. Correction begins with separately calculation and cancelation of the nonlinear and linear errors respectively. For calibration of each stage at first step, the nonlinear effects in digital output of backend ADC is eliminated and then by digital modeling of first order analog error the influence of this unfavorable signal is diminished from digital equivalent of input voltage. Therefore for cancelation of non-ideal impairment in each stage a digital filter consist of linear and nonlinear channel in digital domain is designed. The first order and third order coefficients of designed digital function are unknown and should by a pertinent method be estimated simultaneously. Adaptive filter are best choose for this method. Simulation results show that INL/DNL parameters of 14-bit radix-4 pipelined converter are improved from 17LSB/3LSB to 0.45LSB/0.41LSB after calibration. The SNDR/SFDR parameters are increased from 30dB/36dB to 83dB/90dB.

Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs

In this paper, a digital background calibration technique for pipelined analog-to-digital converters (ADCs) is presented to continuously mitigate the conversion errors arising from the residue amplifier imperfections. The introduced method indirectly measures the digitized residue errors based on a novel principle. In the proposed method, the digitized residue errors are measured through the probability distribution of the digitized residue and a two-level pseudorandom noise sequence. Behavioral simulations are provided for a 12-bit pipelined ADC architecture to show the effectiveness of the proposed technique. The simulation results show that the signal-to-noise and distortion ratio is improved from 42.94 to 72.85 dB using the presented calibration technique. The required number of samples for convergence is approximately 5 $$\times $$× $$10^{6}$$106 clock cycles.

A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC

This paper presents a 13 bit 50 MS/s fully differential ring amplifier based SAR-assisted pipeline ADC, implemented in 65 nm CMOS. We introduce a new fully differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of high gain, fast slew based charging and an almost rail-to-rail output swing. We implement a switched-capacitor (SC) inter-stage residue amplifier that uses this new fully differential ring amplifier to give accurate amplification without calibration. In addition, a new floated detect-and-skip (FDAS) capacitive DAC (CDAC) switching method reduces the switching energy and improves linearity of first-stage CDAC. With these techniques, the prototype ADC achieves measured SNDR, SNR, and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, with a Nyquist frequency input. The prototype achieves 13 bit linearity without calibration and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion $\cdot$ step and 174.9 dB, respectively.

A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-$\mu $ m CMOS Technology

This brief presents a zero-crossing-based pipeline analog-to-digital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13- $\mu $ m CMOS process and occupies a die area of 0.7 $\mathrm{mm}^{2}$ . The differential and integral nonlinearity of the ADC are less than 0.83/−0.47 and 1.05/−0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

보정기법 없이 채널 간 오프셋 부정합을 최소화한 2x Interleaved 10비트 120MS/s 파이프라인 SAR ADC

본 논문에서는 특별한 보정기법 없이 채널 간 오프셋 부정합 문제를 최소화한 2채널 time-interleaved (T-I ) 구조의 10비트 120MS/s 파이프라인 SAR ADC를 제안한다. 제안하는 ADC는 4비트-7비트 기반의 2단 파이프라인 구조 및 2채널 T-I 구조를 동시에 적용하여 전력소모를 최소화하면서 빠른 변환속도를 구현하였다. 채널 간에 비교기 및 잔류전압 증폭기 등 아날로그 회로를 공유함으로써 일반적인 T-I 구조에서 선형성을 제한하는 채널 간 오프셋 부정합 문제를 추가적인 보정기법 없이 최소화할 뿐만 아니라 전력소모 및 면적을 감소시켰다. 고속 동작을 위해 SAR 로직에는 범용 D 플립플롭 대신 TSPC D 플립플롭을 사용하여 SAR 로직에서의 지연시간을 최소화하면서 사용되는 트랜지스터의 수도 절반 수준으로 줄임으로써 전력소모 및 면적을 최소화하였다. 한편 제안하는 ADC는 기준전압 구동회로를 3가지로 분리하여, 4비트 및 7비트 기반의 SAR 동작, 잔류전압 증폭 등 서로 다른 스위칭 동작으로 인해 발생하는 기준전압 간섭 및 채널 간 이득 부정합 문제를 최소화하였다. 시제품 ADC는 고속 SAR 동작을 위한 높은 주파수의 클록을 온-칩 클록 생성회로를 통해 생성하였으며, 외부에서 duty cycle을 조절할 수 있도록 설계하였다. 시제품 ADC는 45nm CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 10비트 해상도에서 각각 최대 0.69LSB, 0.77LSB이며, 120MS/s 동작속도에서 동적 성능은 최대 50.9dB의 SNDR 및 59.7dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 0.36mm2이며, 1.1V 전원전압에서 8.8mW의 전력을 소모한다.

A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs) to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It estimates the calibration coefficients at start-up by a modified self-measurement method with low-precision stimulation signals in the multistage calibration. Then, during the ADC normal operation, a sliding histogram in the vicinity of the decision boundaries of stage comparators is utilized to adjust the calibration coefficients in order to follow the variation of errors. To do so, the ratio of information achieved from the initial and new histograms is used to update the calibration coefficients. Behavioral simulation results of a 12-bit pipelined ADC show that the proposed calibration technique improves the ADC linearity by more than 4 bits and it is robust against the variation of errors.

A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs

A digital background calibration technique for pipelined analog-to-digital converters (ADCs) is proposed to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It divides the pipelined ADC into two equal channels and changes the decision points of sub-ADCs with a pseudorandom sequence to perform the digital background calibration. The difference between the digital outputs of the channels is used to drive the least mean square (LMS) machine to correct the mentioned errors and also the mismatch between the channels. In order to speed up the error correction, an accurate estimation for the errors is identified. The estimation is done by utilizing a piecewise linear model and a slope mismatch measurement technique in the digital domain. Behavioral simulations of a 12-bit 100-MS/s split pipelined ADC show that the convergence time of the proposed LMS calibration technique is significantly reduced in comparison with the conventional LMS algorithm for the same signal-to-noise-and-distortion ratio.

An Integrator-Based Pipelined ADC With Digital Calibration

A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25- $\mu\mbox{m}$ CMOS prototype dissipates 140 mW and occupies an active area of 5 mm 2. At 40 megasamples/s (40 MS/s) , the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB.

A statistics-based digital background calibration technique for pipelined ADCs

This paper introduces a digital background calibration technique for pipelined analog-to-digital converters (ADCs). The proposed method continuously measures and digitally corrects conversion errors resulting from residue amplifier gain error and nonlinearity. It is based on modulation of the residue voltage using a pseudorandom-noise sequence (PN). A least-mean-squares (LMS) algorithm is utilized to correct conversion errors arising from the residue amplifier non-idealities. Besides, a new statistics-based digitized residue distance estimation (DRDE) algorithm is proposed that allows the LMS algorithm to operate in the background without interrupting the normal operation of the ADC. The DRDE method extracts the residue amplifier non-idealities by evaluating the digitized residue voltage probability density function (PDF). Behavioral simulation results verify the usefulness of the proposed calibration technique and show that the signal-to-noise-and-distortion-ratio (SNDR) is improved from 43 to 71.9dB, in a 12-bit pipelined ADC.

High speed, open loop residue amplifier with linearity improvement

In this paper a new solution for a highly linear, high speed open loop (OL) residue amplifier for applications in high-speed pipelined analogue-digital converters is proposed. The proposed amplifier has a voltage gain of 4 (V/V) with <0.2% non-linearity error and 1.2 Vp-p output swing. The amplifier is compensated for process variations by using a novel gain control mechanism, thus maintains the linearity in all process conditions and also in the presence of a mismatch. The proposed amplifier is designed in 0.35 μm complementary metal-oxide semiconductor process, and the settling time is approximately 2 ns when driving two 1 pF single ended capacitive loads. It consumes 38 mW power from a 2.8 V supply and occupies 0.073 mm2 of die area. Simulations are performed in HSPICE using level 49 models.

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration

A 12 bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered to achieve higher energy efficiency and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical op amp implementation, the settling accuracy of the residue amplifier was relaxed by a factor of more than 3x in the first two stages and by 2x in the remaining stages. The ADC was implemented in 40 nm digital CMOS and shows a Schreier figure-of-merit of 157.5 dB at 1 V supply, sampling at 195 MS/s, with an SNDR/SFDR of 64.8 dB/82 dB. While working in continuous background mode, the split-ADC calibration improved the ADC SFDR by 37 dB within 70,000 samples.

Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self‐Tracking Comparator Thresholds

A digital background calibration technique which mainly corrects nonlinear errors of residue amplifiers in pipelined analog-to-digital converters (ADCs) is presented. The proposed technique extracts the nonlinear errors by splitting sampling capacitors and inserting two extra comparators, and is highly effective as long as the input signal is busy. The method of self-tracking comparator thresholds is proposed to reduce the time of convergence with low complexity for any bit cases in a pipelined ADC. Both measurement and correction are processed in digital domain. After calibration, the behavioral simulation shows that the Signal-to-noise-and-distortion ratio (SNDR) is raised from 55.4dB to 90.2dB and the Spurious-free dynamic range (SFDR) is improved from 61.6dB to 102dB in a 16-bit prototype pipelined ADC with 0.5% capacitor mismatches and 4.5% gain compression of the residue amplifier.

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

This paper presents a 0.55 V, 7 bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, high-speed open-loop dynamic amplifiers with a common-mode detection technique are used as residue amplifiers to increase the ADC's speed, to enhance the robustness against supply voltage scaling, and to realize clock-scalable power consumption. To mitigate the absolute gain constraint of the residue amplifiers in a pipeline ADC, the interpolated pipeline architecture is employed to shift the gain requirement from absolute to relative accuracy. To show the new requirements of the residue amplifiers, the effects of gain mismatch and nonlinearity of the dynamic amplifiers are analyzed. The 7 bit prototype ADC fabricated in 90 nm CMOS demonstrates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM of the ADC is 240 fJ/conversion-step.