Residue Amplifier Research Articles

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry

This paper presents a signal-chain friendly 12-bit pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) in 40nm CMOS, which is optimized to achieve a 68.5 dB-SNDR, 100-MS/s sample rate with 54.5% of maximum available input range. The implemented ADC employs an improved clock booster and latch-register to achieve high on-conductance of nmos switches and low-leakage data storage. It also explores an adaptive non-overlapping complementary clock generator and a dedicated VCM buffer to accommodate process, voltage, and temperature (PVT) conditions. The relative variation of non-overlapping time is reduced by 50% compared to the conventional method, and the signal-to-distortion ratio (SDR) of residue amplification is improved by 8dB . Moreover, on-chip bit weight calibration is implemented to address the gain error brought by capacitor mismatch and inner-stage gain error. The prototype ADC is simulated under 5 corners, −40 to 125°C, and 1.1V±2.5%. For a Nyquist input, the simulated SNDR under typical corner is 68.5dB , which can remain over 66dB under PVT conditions. The achieved Walden Figure of Merit (FoM) is 12.4-fJ/conv.-step.

A 10 MHz‐BW 85 dB‐SNDR 4th‐order sturdy MASH 2‐0 noise shaping SAR ADC with 2nd‐order gain‐error‐shaping technique

AbstractThe multi‐stage noise shaping (MASH) ΣΔ ADC has a good potential to achieve high‐order noise shaping (NS) and high resolution. However, it suffers from quantization noise leakage caused by the mismatch between the analogue NS filter and the digital cancellation filter, which greatly degrades the ADC performance. The sturdy MASH topology of the ΣΔ ADC can solve the leakage issue, but it cannot be implemented using the NS SAR ADC due to structural limitations. This paper proposes a sturdy MASH 2‐0 NS SAR to solve the noise leakage issue. The 4th‐order NS is achieved by only using a 2‐0 topology, which is hardware efficient. Instead of eliminating the first‐stage quantization error, the proposed sturdy MASH 2‐0 NS SAR shapes it, achieving better robustness to PVT variables. Furthermore, owing to the first‐stage 2nd‐order NS capability, the impairments of the residue amplifier, including the gain error and nonlinearity, are 2nd‐order shaped. The proposed 4th‐order sturdy MASH 2‐0 NS SAR is implemented in a 28 nm CMOS process, which achieves a SNDR of 85.6 dB and a SFDR of 101.3 dB with 10 MHz BW at OSR of 10, resulting in a Schreier FoM of 178.8 dB/179.4 dB (in SNDR/DR) with power consumption of 4.8 mW.

A Fast and Cost-Effective Calibration Strategy of Inter-Stage Residual Amplification Errors for Cyclic-Pipelined ADCs

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm2.

An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC

This paper presents a low-power 18/12-bit 1 MS/s reconfigurable pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC). The proposed pipelined-SAR ADC employs a two-stage SAR structure coupled through a residual amplifier, with the forestage performing 12-bit coarse quantization and the poststage handling 7-bit fine quantization, one bit of redundancy is contained in the rear stage. The input signal is sampled by the first stage, SAR ADC, using the upper plate of a capacitor array and is quantized by charge redistribution. This eliminates the need of additional DACs and subtractors, allowing direct acquisition of the residuals. In addition, the residuals can be amplified by reusing the capacitor array as a switching capacitor. To minimize static power consumption, dynamic logic is adopted in each module of the pipelined-SAR ADC. The calibration of comparator offset and capacitor mismatch is carried out using analog front-end calibration techniques. Implemented in a 180 nm CMOS process, the simulation results show an extra-low power consumption of 1.76 mW with 3.3 V supply voltage and 1 MS/s sampling rate, indicating an exceptional Schreier figure of merit (FOMs) at 181.64 dB. By shutting down the modules of the second-stage SAR ADC, the 18-bit ADC can be dynamically configured as a 12-bit ADC with a sampling rate of up to 5 MS/s.

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification

A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage

A Three-Step Low-Power Multichannel TDC Based on Time Residual Amplifier

A Three-Step Low-Power Multichannel TDC Based on Time Residual Amplifier

A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS

A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Sigma $</tex-math> </inline-formula> and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency. The single-channel NS-SAR with high resolution, however, suffers from bandwidth (BW) limitations. The time-interleaved (TI) NS-SAR mitigates the speed bottleneck but faces challenges in obtaining high resolution and BW simultaneously due to the lack of a sharp noise transfer function (NTF). This article presents a calibration-free two-channel TI-NS-SAR with an aggressive second-order NTF for high resolution. Based on a one-time error feedback (FB) at midway, we propose a second-order error-feedforward (FF) to enhance the noise-shaping (NS) effect further meanwhile avoiding the excessive NTF peaking and dynamic range (DR) loss. A dynamic residue amplifier shared between two channels lowers the offset, which reduces the redundant bit to only one bit, thus improving the efficiency of SAR conversion. Fabricated in a 28 nm CMOS with 1 V supply, the prototype achieves 73.2 dB-signal-to-noise-and-distortion-ratio (SNDR) over 30 MHz-BW when operating at 330 MHz. It consumes 3.07 mW and exhibits a Schreier FoM (FoMs) of 173.1 dB.

Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency

One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.

A non-pipelined ADC with a GM-R amplifier

A GM-R amplifier is proposed as a residual amplifier to implement a 16-bit two-stage non-pipelined ADC in intermittent signal acquisition applications. Unlike common capacitive feedback amplifiers, residual amplifiers utilize resistor ratios to generate constant gain for small input amplitude ranges and wide temperature ranges. The input circuit of the proposed amplifier consists of two source followers and a bridge resistor, thus converting residual voltages to currents, and the transconductance is the reciprocal of the bridge resistor. The amplifier offset voltage is corrected by a one-time foreground offset calibration, and the gain error is calibrated with the capacitor weights in the first stage. Redundancy is adopted between the two stages to accommodate the residual offset voltage after calibrating the offset voltage of a comparator and the gain variation. A design prototype is implemented in 180 nm CMOS technology, occupies a 0.69 mm2 footprint, and consumes 3.0 mW from 1.8/5 V power supplies. After calibration, it achieves the SNR of 88.2 dB, SNDR of 87.6 dB, and THD of −95.6 dB at 200 kHz sampling rate. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.62/+0.74 LSB and −1.39/+1.50 LSB, respectively.

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier

This article presents a process, voltage, and temperature (PVT)-robust capacitively degenerated dynamic amplifier as the residue amplifier of the low-power pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier achieves a voltage gain of 16 with a two-stage configuration and high linearity over a wide temperature range with an on-chip timing generator. This work solves problems related to the low voltage gain and high temperature–sensitivity of the capacitively degenerated dynamic amplifier, while retaining the advantages of high linearity, wide output swing, and high energy efficiency. The prototype ADC is implemented in a 65-nm CMOS process and achieves 65-dB signal-to-noise-and-distortion ratio (SNDR) and 79.8-dB spurious free dynamic range (SFDR) at a sampling rate of 50 MS/s, while consuming only 0.46 mW. The power overhead of the timing generator is only 10% of the overall power consumption. It shows only 0.7-dB and 1.86-dB SNDR variations at 0.8–1.0-V supply variation and 0 °C–100 °C temperature variation, respectively.

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier

This article presents a 13-b high-speed pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by one comparator after each comparison cycle, and the effective-number-of-bits (ENOBs) can improve up to 1 b when the metastability boundary is set at ±1/4 LSB. In addition, an open-loop inverter-based residue amplifier (RA) is proposed with simple circuit implementation. The RA gain is well defined by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> ratio and is immune to process, voltage, and temperature (PVT) variations. Fabricated in 40-nm CMOS technology, the prototype ADC achieves a mean signal-to-noise plus distortion ratio (SNDR) of 59.8–62.8 dB, with 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> than 1.7 dB, at 600–625 MS/s over −40° to 125° temperature range and 1.1–1.2 V power supply range, a 67 dB dynamic range (DR), and a 62.4 dB SNDR for a Nyquist input while sampling at 625 MS/s. The overall power consumption is 7.05 mW.

A Large-Swing High-Linearity Fully-Dynamic Amplifier With Automatic Calibration

In high-speed pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs), the residue amplifiers dominate the overall ADC speed, power, and accuracy. To improve the ADC performance, this brief proposes a large-swing high-linearity fully-dynamic open-loop amplifier. By setting the cascode input transistors in linear region, both the input/output swing and the linearity are improved significantly. By clamping the drain voltages of input transistors, the amplifier gain is PVT insensitive. These drain voltages of input transistors are clamped through a dynamic comparator with small size, which helps save energy. The comparator offset is automatically canceled out through a novel thermal-noise-based technique. Designed in a 40nm CMOS process, the proposed amplifier achieves an output swing of 400mVpp, a settling accuracy of 8-bit ENOB, and a voltage gain of 16X, under a 100MHz clock frequency. It is fully-dynamic and only consumes 1.15mW of power under a 1.1V supply. Compared to the state-of-the-art dynamic amplifiers, the output swing is increased by 4 times; the settling accuracy is improved by 2 bits; the voltage gain is increased by 4 times; the PVT sensitivity of voltage gain is reduced by 4.7 times; and the power consumption is decreased by 45% with fully-dynamic operation.

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over various input voltage conditions, which enables cascading multiple dynamic-amplifier-based pipeline stages. The replica-biased amplifiers from the 2nd to the last stage maintain the differential gain, eliminating the need for bit-weight calibrations. The 1st~3rd stages utilize a loop-unrolled SAR structure for high-speed conversion. A 9-bit 500MS/s pipelined SAR ADC is fabricated in 28nm CMOS process, and it achieves SNDR of 49.1dB and SFDR of 60.4dB at low frequency and SNDR of 45.3dB and SFDR 56.0dB at Nyquist frequency. The measured performance over wide input common-mode and temperature range validates the operation of the replica-biased dynamic amplifiers. The measured Walden figure of merit (FoMw) is 23.3fJ/conversion-step and Schreier FoM (FoMs) is 158.6dB, respectively.

A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier

This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that reduce the RA gain error due to their finite open-loop gain, the proposed DACLS ring amplifier no longer requires an extra level-shifting capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {LS}}$ </tex-math></inline-formula> ) at the RA output, such that the RA bandwidth can be improved. Furthermore, instead of a single-level shift in the prior arts, the DACLS ring amplifier provides an option for multiple level shifts and thereby accomplishes a greater RA gain error reduction. In addition, a customized bypass-window scheme is applied, which can skip some power-wasting digital-to-analog converter (DAC) switchings by window detection and thus reduces the power consumption of the ADC. To reduce the bit-cycling time of the SAR conversion, a delay-reduced (DR) SAR logic is introduced to increase the ADC speed. The ADC chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.013 mm2. At 130-MS/s and the Nyquist-rate input frequency, the measured SNDR is 72.5 dB, while the power consumption is only 0.82 mW. Without any calibration, the proposed ADC achieves a Walden and a Schreier figure-of-merit (FoM) of 1.8 fJ/conversion step and 181.5 dB, respectively. Compared to the prior-art ADCs with an input bandwidth ≥ 40 MHz and a SNDR > 68 dB, this work shows the best FoMs.

A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique

This paper describes a 12-bit 1.25-GS/s RF sampling pipelined analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. To achieve high-speed and high-resolution conversion, a two-stage push-pull residue amplifier powered by a dual-supply is employed. A left half-plane (LHP) zero is generated through the coupling capacitance to expand the bandwidth and an inverter-based auxiliary amplifier is used to improve the gain and simplify the design. In addition, the proposed residue amplifier achieves a stable closed-loop characteristic without adding compensation capacitance, which greatly saves the area and improves the power efficiency. With an 18 MHz and 2 Vpp input signal, the SNDR is 61.5 dB, the SFDR is 70.2 dB. And the SNDR and SFDR are greater than 58 dB and 69 dB over the entire Nyquist bandwidth while the power consumption is 45.6 mW.

2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The FoMS,SNDR is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.

A new background continuous‐time offset cancelation and gain calibration strategy for open‐loop residue amplifiers in high‐speed and high‐resolution ADC's

A continuous-time offset cancelation and gain calibration strategy is proposed for open-loop residue amplifiers of pipeline ADC's. Utilizing a reliable technique for detecting gain and offset error, also saving digital amounts of the signals that are resulted from the calibration loop, data conversion proceeds without any interruption. In addition, due to sharing this structure between the several RA stages in ADC, power consumption and area occupation are decreased. Also, this strategy does not require extra circuits, like replica residue amplifier or wide-bits digital processor for offset and gain-error correction. Using digital circuits results in multiplexing clock frequency; also, utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input-referred offset is reduced to around 30 μV. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Post-layout simulation results are presented at all process corners and various temperatures, using HSPICE software and 0.18 μm standard CMOS technology in 14-bit 200 MS/s Pipeline ADC with 23 dB improvement in SNR and 3.9 bit in ENOB.