Memory Bandwidth Requirements Research Articles

Fast hardware architecture for grey‐level image morphology with flat structuring elements

Mathematical morphology operators, applied in many vision-based applications, are characterised by repetitive operations on large amounts of data. Thus, novel design strategies for efficient hardware implementations are necessary. This study presents and evaluates a real-time hardware architecture for grey-level image erosion and dilation that processes data in streams for an efficient utilisation of memory bandwidth and low on-chip memory requirements. A low-complexity and highly modular architecture is proposed based on a sequence of pipeline stages, and parallel processing in order to minimise computational times. The design is intended to be used as a hardware accelerator in real-time embedded image processing applications requiring moderate-size and non-rectangular flat structuring elements on high-resolution images. The architecture is prototyped on a field programmable gate array device operating at a clock frequency of 260 MHz on a Virtex-6 device which compares favourably to the well-known delay-line-based hardware architectures in terms of complexity, memory requirements and execution time. A 7 × 7 dilation/erosion operator on 1280 × 1024 grey-level image can be performed at a rate of 95 frames per second, but the architecture can be scaled up if required.

Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement

Montgomery modular multiplication is widely used in public-key cryptosystems. This work shows how to relax the data dependency in conventional word-based algorithms to maximize the possibility of reusing the current words of variables. With the greatly relaxed data dependency, we then proposed a novel scheduling scheme to alleviate the number of memory access in the developed scalable architecture. Analytical results show that the memory bandwidth requirement of the proposed scalable architecture is almost 1/(w - 1) times that of conventional scalable architectures, where w denotes word size. The proposed one also retains a latency of exactly one cycle between the operations of the same words in two consecutive iterations of the Montgomery modular multiplication algorithm when employing enough processing elements. Compared to the design in the related work, experimental results demonstrate that the proposed one achieves an almost 54 percent reduction in power consumption with no degradation in throughput. The reduced number of memory access not only leads to lower power consumption, but also facilitates the design of scalable architectures for any precision of operands.

Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

Large-scale parallel lattice Boltzmann–cellular automaton model of two-dimensional dendritic growth

An extremely scalable lattice Boltzmann (LB)–cellular automaton (CA) model for simulations of two-dimensional (2D) dendritic solidification under forced convection is presented. The model incorporates effects of phase change, solute diffusion, melt convection, and heat transport. The LB model represents the diffusion, convection, and heat transfer phenomena. The dendrite growth is driven by a difference between actual and equilibrium liquid composition at the solid–liquid interface. The CA technique is deployed to track the new interface cells. The computer program was parallelized using the Message Passing Interface (MPI) technique. Parallel scaling of the algorithm was studied and major scalability bottlenecks were identified. Efficiency loss attributable to the high memory bandwidth requirement of the algorithm was observed when using multiple cores per processor. Parallel writing of the output variables of interest was implemented in the binary Hierarchical Data Format 5 (HDF5) to improve the output performance, and to simplify visualization. Calculations were carried out in single precision arithmetic without significant loss in accuracy, resulting in 50% reduction of memory and computational time requirements. The presented solidification model shows a very good scalability up to centimeter size domains, including more than ten million of dendrites. Program summaryProgram title: 2DdendCatalogue identifier: AEQZ_v1_0Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEQZ_v1_0.htmlProgram obtainable from: CPC Program Library, Queen’s University, Belfast, UKLicensing provisions: Standard CPC license, http://cpc.cs.qub.ac.uk/licence/licence.htmlNo. of lines in distributed program, including test data, etc.: 29,767No. of bytes in distributed program, including test data, etc.: 3131,367Distribution format: tar.gzProgramming language: Fortran 90.Computer: Linux PC and clusters.Operating system: Linux.Has the code been vectorized or parallelized?: Yes. Program is parallelized using MPI. Number of processors used: 1–50,000RAM: Memory requirements depend on the grid sizeClassification: 6.5, 7.7.External routines: MPI (http://www.mcs.anl.gov/research/projects/mpi/), HDF5 (http://www.hdfgroup.org/HDF5/)Nature of problem:Dendritic growth in undercooled Al–3 wt% Cu alloy melt under forced convection.Solution method:The lattice Boltzmann model solves the diffusion, convection, and heat transfer phenomena. The cellular automaton technique is deployed to track the solid/liquid interface.Restrictions:Heat transfer is calculated uncoupled from the fluid flow. Thermal diffusivity is constant.Unusual features:Novel technique, utilizing periodic duplication of a pre-grown “incubation” domain, is applied for the scaleup test.Running time:Running time varies from minutes to days depending on the domain size and number of computational cores.

A-DFA

Modern network intrusion detection systems need to perform regular expression matching at line rate in order to detect the occurrence of critical patterns in packet payloads. While Deterministic Finite Automata (DFAs) allow this operation to be performed in linear time, they may exhibit prohibitive memory requirements. Kumar et al. [2006a] have proposed Delayed Input DFAs (D2FAs), which provide a trade-off between the memory requirements of the compressed DFA and the number of states visited for each character processed, which in turn affects the memory bandwidth required to evaluate regular expressions. In this article we introduce Amortized time − bandwidth overhead DFAs ( A − DFAs ), a general compression technique that results in at most N ( k + 1)/ k state traversals when processing a string of length N , k being a positive integer. In comparison to the D2FA approach, our technique achieves comparable levels of compression with lower provable bounds on memory bandwidth (or greater compression for a given bandwidth bound). Moreover, the A-DFA algorithm has lower complexity, can be applied during DFA creation, and is suitable for scenarios where a compressed DFA needs to be dynamically built or updated. Finally, we show how to combine A-DFA with alphabet reduction and multistride DFAs, two techniques aimed at reducing the memory space and bandwidth requirement of DFAs, and discuss memory encoding schemes suitable for A-DFAs.

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology.

Influence of memory access patterns to small-scale FFT performance

Modern GPUs (Graphics Processing Units) offer very high computing power at relative low cost. To take advantage of their computing resources and develop efficient implementations is essential to have certain knowledge about the architecture and memory hierarchy. In this paper, we use the FFT (Fast Fourier Transform) as a benchmark tool to analyze different aspects of GPU architectures, like the influence of the memory access pattern or the impact of the register pressure. The FFT is a good tool for performance analysis because it is used in many digital signal processing applications and has a good balance between computational cost and memory bandwidth requirements.

A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications

A 1920 × 1080 160° object viewpoint recognition system-on-chip (SoC) is presented in this paper. The SoC design is dedicated to wearable vision applications, and we address several crucial issues including the low recognition accuracy due to the use of low resolution images and dramatic changes in object viewpoints, and the high power consumption caused by the complex computations in existing computer vision object recognition systems. The human-centered design (HCD) mechanism is proposed in order to maintain a high recognition rate in difficult situations. To overcome the degradation of accuracy when dramatic changes to the object viewpoint occur, the object viewpoint prediction (OVP) engine in the HCD provides 160° object viewpoint in- variance by synthesizing various object poses from predicted object viewpoints. To achieve low power consumption, the visual vocabulary processor (VVP), which is based on bag-of-words (BoW) matching algorithm, is used to advance the matching stage from the feature-level to the object-level and results in a 97% reduction in the required memory bandwidth compared to previous recognition systems. Moreover, the matching efficiency of the VVP enables the system to support real-time full HD (1920 × 1080) processing, thereby improving the recognition rate for detecting a traffic light at a distance of 50 m to 95% compared to the 29% recognition rate for VGA (640 × 480) processing. The real-time 1920 × 1080 visual recognition chip is realized on a 6.38 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die with 65 nm CMOS technology. It achieves an average recognition rate of 94%, a power efficiency of 1.18 TOPS/W, and an area efficiency of 25.9 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while only dissipating 52 mW at 1.0 V.

SORT-SGM: Subpixel Optimized Real-Time Semiglobal Matching for Intelligent Vehicles

The suitability of stereo algorithms for intelligent vehicle applications is conditioned by their ability to compute dense accurate disparity maps in real time. In this paper, an original stereo reconstruction system that is designed for automotive applications is presented. The system is based on the semiglobal matching algorithm (SGM), which is widely known for its high quality and potential for real-time implementation. Several improvements that target the matching, disparity optimization, and disparity refinement steps are proposed. Pixel-level matching uses the census transform because of its invariance to intensity differences due to camera bias or gain that affects the images. The huge memory bandwidth requirements for the SGM disparity optimization step are reduced through a new integration strategy. At the subpixel level, accuracy is increased by devising a new methodology for generating dedicated subpixel interpolation functions. Using this methodology, two novel subpixel interpolation functions for the SGM algorithm are implemented and evaluated. The proposed algorithm has been implemented on a graphics processing unit in the Compute Unified Device Architecture (CUDA). The result is an increased speed and accuracy algorithm profiled for complex real-traffic scenarios. The proposed algorithm has been evaluated at a large scale, and evidence that was collected from both standard benchmarks and real-world images confirm the findings and show a significant improvement over existing solutions.

Analytical memory bandwidth model for many-core processor based systems

Many-core processor based systems gain popularity in high-performance parallel embedded applications. Estimating memory bandwidth requirement, i.e. external memory bandwidth, given various cache size for target parallel applications requires a prohibitively large simulation time. In this work, we propose an analytical model to quickly estimate the memory bandwidth for a given cache size and help exploring trade-offs between cache sizes and memory bandwidth requirement. We model the stochastic behavior of cache misses for a single cache as a random process. Using central limit theorems for identically or non-identically distributed random processes, we accurately estimate the collective cache misses from hundreds of processor cores and thus the total memory bandwidth requirement for the whole system. The results show that our model improves a speed of simulation time up to 200.4 times for 200 cores whereas its estimated results achieve less than 0.01% difference from the simulated ones for 200 cores in terms of accuracy.

Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)

For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVA™) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The three main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.

Creating robust high-throughput traffic sign detectors using centre-surround HOG statistics

In this paper, we detail a system for creating object detectors which meet the extreme demands of real-world traffic sign detection applications such as GPS map making and real-time in-car traffic sign detection. The resulting detectors are designed to detect and locate multiple traffic sign types in high-definition video (high throughput) from several cameras captured along thousands of kilometers of road with minimal false-positives and detection rates in excess of 99%. This allows for the accurate detection and location of traffic signs in geo-tagged video datasets of entire national road networks in reasonable time using only moderate computing infrastructure. A key to the success of the methods described in this paper is the use of extremely efficient classifier features. In this paper, we identify two obstacles to achieving the desired performance for all target traffic sign types, feature memory bandwidth requirements and feature discriminance. We introduce our use of centre-surround histogram of oriented gradient (HOG) statistics which greatly reduce the per-feature memory bandwidth requirements. Subsequently we extend our use of centre-surround HOG statistics to the color domain, raising the discriminant power of the final classifiers for more challenging sign types.

T&amp;I engine

Ray tracing naturally supports high-quality global illumination effects, but it is computationally costly. Traversal and intersection operations dominate the computation of ray tracing. To accelerate these two operations, we propose a hardware architecture integrating three novel approaches. First, we present an ordered depth-first layout and a traversal architecture using this layout to reduce the required memory bandwidth. Second, we propose a three-phase ray-triangle intersection architecture that takes advantage of early exit. Third, we propose a latency hiding architecture defined as the ray accumulation unit. Cycle-accurate simulation results indicate our architecture can achieve interactive distributed ray tracing.

Color reduction using a multi-stage Kohonen Self-Organizing Map with redundant features

Reducing the number of colors in an image while preserving its quality, is of importance in many applications such as image analysis and compression. It also decreases the memory and transmission bandwidth requirements. Moreover, classification of image colors is applicable in image segmentation, and object detection and separation, as well as producing pseudo-color images. In this paper, the Kohonen Self-Organizing Map Neural Network is employed to form an adaptive color reduction method. To enhance the performance of this method, we have used redundant features obtained by one-to-one functions from three main components of the color image (e.g. Red, Green and Blue channels). Exploiting these features will increase the color discrimination and details illustration ability of the network compared to the conventional approaches. This method leads to satisfactory results in image segmentation, especially in small object detection problems. It is also investigated that if the number of features in Kohonen network grows even by using non-deterministic one-to-one functions, the network revenue considerably improves. Moreover, we will study the effect of various adaptation algorithms in Kohonen network training stage. Again, using a multi-stage color reduction procedure which employs both Kohonen neural networks and conventional vector quantization schemes improves the performance. Several experimental results are represented to illustrate the characteristics of different approaches.

Automatic memory partitioning and scheduling for throughput and power optimization

Memory bottleneck has become a limiting factor in satisfying the explosive demands on performance and cost in modern embedded system design. Selected computation kernels for acceleration are usually captured by nest loops, which are optimized by state-of-the-art techniques like loop tiling and loop pipelining. However, memory bandwidth bottlenecks prevent designs from reaching optimal throughput with respect to available parallelism. In this paper we present an automatic memory partitioning technique which can efficiently improve throughput and reduce energy consumption of pipelined loop kernels for given throughput constraints and platform requirements. Also, our proposed algorithm can handle general array access beyond affine array references. Our partition scheme consists of two steps. The first step considers cycle accurate scheduling information to meet the hard constraints on memory bandwidth requirements specifically for synchronized hardware designs. An ILP formulation is proposed to solve the memory partitioning and scheduling problem optimally for small designs, followed by a heuristic algorithm which is more scalable and equally effective for solving large scale problems. Experimental results show an average 6× throughput improvement on a set of real-world designs with moderate area increase (about 45% on average), given that less resource sharing opportunities exist with higher throughput in optimized designs. The second step further partitions the memory banks for reducing the dynamic power consumption of the final design. In contrast to previous approaches, our technique can statically compute memory access frequencies in polynomial time with little or no profiling. Experimental results show about 30% power reduction on the same set of benchmarks.

Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Large external memory bandwidth requirement leads to increased system power dissipation and cost in video coding application. Majority of the external memory traffic in video encoder is due to reference data accesses. We describe a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. The low cost transformless compression technique uses lossy reference for motion estimation to reduce memory traffic, and lossless reference for motion compensation (MC) to avoid drift. Thus, it is compatible with all existing video standards. We calculate the quantization error bound and show that by storing quantization error separately, bandwidth overhead due to MC can be reduced significantly. The technique meets key requirements specific to the video encode application. 24-39% reduction in peak bandwidth and 23-31% reduction in total average power consumption are observed for IBBP sequences.

Implementation of parallel integer motion estimation method by using reference blocks shared for HD video encoding

The redundant data in integer motion estimation (IME) come from the overlapping reference blocks of consecutive current macroblocks processing, and thus increase the requirement of memory bandwidth. In order to overcome these obstacles, we propose the SRBIME (Shared Reference Block Integer Motion Estimation) and implement. In the SRBIME, one reference block is shared for parallel current macroblocks processing in order to enhance data reusability and to reduce internal memory on IME design. Experimental results show that the proposed motion estimation design saves 95.9% of external memory bandwidth than Inter-Candidate data reuse scheme, 3% of gate count and 11.8% of local memory are saved compared with previous design while supporting higher encoding specification.

An effective depth data memory system using an escape count buffer for 3D rendering processors

This paper proposes an effective memory system of depth data to reduce the bandwidth requirement from the external memory for low-power 3D rendering processors. For this purpose, we propose an escape count buffer that contains information about the data size for each compressed depth block. Compared to the previous scheme, experimental results show that this approach reduces the memory bandwidth requirements up to 44%.

Low complexity embedded compression algorithm for reduction of memory size and bandwidth requirements in the JPEG2000 encoder

In this paper, a new and low-complexity embedded compression (EC) algorithm for the JPEG2000 encoder system is proposed to efficiently reduce memory requirements. The proposed EC algorithm is used to achieve a fixed compression ratio of 50% under the near-lossless compression constraint. Through the EC technique, the memory requirement for intermediate low-frequency coefficients during multiple DWT stages can be reduced by a factor of 2 compared with direct implementation of the JPEG2000 encoder. By jointly considering the coding flow of both block-based 2D-DWT and bit-plane coders, the EC scheme combines an efficient quantization and simple entropy coder to reduce memory transaction bandwidth between DWT and bit-plane coder (BPC) to 50%. Furthermore, this EC reduces the size of code-block memory from DWT to BPC. Experiment results based on standard test image benchmarks show that our proposed EC algorithm presents only PSNR degradation of 1.05 dB on average when the target compression ratio is fixed at 50%. Our EC can be applicable to the JPEG2000 encoding system to save memory size and bandwidth requirements with minor picture quality degradation. The proposed EC algorithm is also computationally simple, reducing latency time and creating sufficient accessibility.

Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine

In this paper, a low-cost compatible motion compensator is implemented and integrated into a macroblock-level three-stage-pipelined HDTV decoder, in which an embedded compression (EC) engine is realized as well. The decoder with EC engine is designed to reduce the power consumption and memory bandwidth requirement since memory accesses are reduced. In the motion compensator, a boundary judgment scheme for reference pixel fetching is proposed to provide seamless integration in HDTV video decoder for the block-based EC engines. Furthermore, a buffer sharing mechanism is adopted to reduce extra memory requirement involved by EC. The reference pixel fetching unit costs only 17.3 K logic gates when the working frequency is set to 166.7 MHz. On average, when decoding HD1080 video sequence, 30% memory access reduction and 24% memory power consumption saving are achieved when a near lossless EC algorithm is integrated in the video decoder. In other words, the proposed motion compensator makes the EC engine an integral part of a memory reduced decoder without extra cost. Additionally, since the work in this paper is based on EC schemes, the EC design criterion are discussed, and several useful rules on the selection of EC algorithm are addressed for the video decoder of corresponding VLSI architecture.