Replacement Gate Research Articles

Hafnia-Based Ferroelectric Transistor with Poly-Si Gates for Gate-First Three-Dimensional NAND Structures.

Ferroelectric transistors based on hafnia-based ferroelectrics have emerged as promising candidates for next-generation memory devices. Additionally, hafnia-based ferroelectric transistors are suggested for three-dimensional (3D) memory devices, such as 3D ferroelectric NAND. This paper investigates the utilization of poly-Si as a gate material for hafnia-based ferroelectric transistors in 3D NAND structures. Conventional gate materials, such as TiN or W, are usually deposited in 3D NAND structures by using the gate-last process, which requires an additional gate replacement process. We demonstrate that poly-Si can be used as a gate material for hafnia-based ferroelectric transistors. We show that the 3D ferroelectric NAND based on the poly-Si gate can be fabricated by a simpler gate-first process without requiring a gate replacement process. Our findings underscore the potential of poly-Si as a gate material for ferroelectric transistors and 3D ferroelectric NAND.

Impact of work function metal stacks on the performance and reliability of multi-Vth RMG CMOS technology

Multi-Vth CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device Vth’s are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low-Vth and ultra-high Vth pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability.

Taming the Distribution of Light in Gate-All-Around Semiconductor Devices.

Optical metrology is ubiquitous, but image-based methods cannot resolve features of dimensions much smaller than the wavelength. However, it has recently been demonstrated that light can be nanofocused into subwavelength semiconducting lines by setting the incident polarization along the direction of these lines. This Letter extends the previous studies to systems with two perpendicular gratings, as found e.g. after replacement gate processing of gate-all-around (GAA) field-effect transistors (FETs). We show that besides the nanofocusing effect, the incident polarization also offers control over which array of lines the light couples into. The interaction of the incident light occurs with the semiconducting lines to which the polarization is parallel with remarkably low interference from the existence of another perpendicular grating. We demonstrate the use of this effect with Raman spectroscopy to simultaneously extract the SiGe volume and the strain in the Si forksheet channels and in the SiGe layers of GAA FETs.

First-principles study of F adsorption by TiN with its oxide surface in three-dimensional NAND flash memory

Three-dimensional (3D) NAND flash memory is a key technology in the field of mainstream memory solutions, which is primarily due to its extremely low bit cost. The architecture of 3D NAND, characterized by its vertically stacked design, substantially enhances the capacity of individual chips. This advancement is completely consistent with the demands for high-capacity data storage in contemporary environments, securing its widespread adoption in diverse application scenarios. As storage density increases, the complexity of process integration increases, bringing new challenges. The word lines in 3D NAND are typically filled by using gate replacement techniques, and compared with chemical vapor deposition (CVD), atomic layer deposition (ALD) is favored for its superior step-coverage, especially for depositing tungsten (W) at the gate. However, due to the complexity of the replacement gate deposition structure, fluorine (F) residues are found in the voids of the tungsten metal gate filling structure and diffuse into the surrounding structure under subsequent process conditions, corroding other films such as silicon oxide and degrading device performance and reliability. To alleviate the problem of fluorine attack, a thin layer of titanium nitride is usually deposited as a barrier layer before deposition of tungsten gate, which blocks the fluorine in the tungsten gate and prevents its diffusion into the oxide layer. Previously, there were studies to increase the ability to stop F diffusion by varying the thickness of the F blocking layer (TiN). However, increasing the thickness of TiN will further increase the complexity of high aspect ratio etching in the 3D NAND process, which will have adverse effect on subsequent processes. To further minimize the effect of fluorine erosion, residual fluorine elements can be removed by introducing annealing in the subsequent process flow. In the actual 3D NAND process, elemental fluorine (F) is adsorbed and accumulates on the TiN surface, and is further activated by subsequent high-temperature processes, leading to severe fluorine erosion. The delay between TiN deposition and subsequent processing steps is hypothesized to facilitate fluorine adsorption due to the oxidation of TiN. This work corroborates this hypothesis through first-principles calculations, and demonstrates the role of TiN oxidation in fluorine adsorption. In this work, we evaluate the effect of this oxidation on the fluorine-blocking effectiveness of the TiN barrier layer. We simulate the adsorption of fluorine-containing by-products on TiN and its oxides, providing theoretical insights into mitigating fluorine attack. The higher degree of oxidation of TiN is more likely to cause F adsorption, and Ti exposed surface TiN is more prone to oxidation, which is more likely to cause F adsorption in unoxidized condition and oxidized condition. Based on these insights, we implemente an ammonia purge treatment in 3D NAND manufacturing, which effectively minimizes fluorine attack, reducing the leakage probability of word line by 25% and wafer warpage by 43%.

Single Event Effects in 3-D NAND Flash Memory Cells With Replacement Gate Technology

We studied the heavy-ion single event effect response of 3D NAND Flash memory cells with charge-trap based replacement gate technology. Error cross sections, threshold voltage shifts, and underlying mechanisms are discussed. The behavior of replacement gate cells is compared with previous generations of Flash NAND memory cells with floating gate architecture, both planar and 3D. The cell array structure, the technology parameters, and the materials impacting on radiation susceptibility of the different types of cells are discussed.

Lightweight PUF-Based Gate Replacement Technique to Reduce Leakage of Information through Power Profile Analysis

Lightweight PUF-Based Gate Replacement Technique to Reduce Leakage of Information through Power Profile Analysis

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS) field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs, which were formed with the process compatible in the main stream industry. The VSAFETs with self-aligned high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gates (HKMGs) were fabricated with epitaxy of Si/SiGe/Si sandwich structure, an isotropic quasi-atomic-layer-etch (qALE) process, and gate replacement process. The gate-length of VSAFETs is mainly determined by the thickness of SiGe film grown by epitaxy. The NW diameter and NS thickness could be obtained by the isotropic qALE method, which can be used to the Si-selective etching of SiGe. As a result, p-type NS and NW VSAFETs with good device characteristics were fabricated. Device performance and the influence of silicide, Ge fraction, Si cap, and high thermal process were investigated; threshold voltage tuning and reliability were also discussed.

Fast Auto-Correction algorithm for Digital VLSI Circuits

Digital integrated circuits represent a driving force in the evolution of high-performance computing and communication required for the implementation of 5G technology. The architecturally demanding nature of scaling down to ever more compact device dimensions has resulted in an increase in logic gate densities up to billions per millimeter square. Given this evolving complexity, formal verification techniques in modern digital very-large-scale integration (VLSI) designs now face a tremendously challenging search space explosion problem. Despite advances in design debugging approaches utilizing CAD tools in order to provide clarified diagnostic descriptions of bug locations, there remains a significant lack of research efforts toward efficient automatic correction approaches following bug location detection. Here, we introduce an enhanced auto-correction algorithm for fixing logic bugs of type - gate replacement, extra and missing inverters. The primary endpoints of the enhanced algorithm are reductions of logic fixing time as well as size of the compulsory injected circuit for selection of optimal designs using SAT engines. Therefore, the proposed correction algorithm avoids the trade-off between high performance and full percentage of accuracy by gradually shrinking the search space without negatively impacting the quality of the rectified design. Our findings indicate that the proposed correction algorithm outperforms previously published tools in terms of average size of injected design to about 1.5x using ISCAS’85 and ISCAS’89 benchmarks. In addition, average speed of generation of rectified digital designs is increased to about 60.73x and 4x in comparison to two recent rectification mechanisms.

(Invited) Stress Simulations of Fins, Wires, and Nanosheets

As the scalability of FinFET architectures is stretched to its limits in the most advanced technologies, industry and research are looking to the next candidates to scale the gate lengths a few nanometers closer to 10nm. Nanosheets and nanowires are such candidates, and specifically the introduction of the former is considered by a major industry player [1]. The inflection point of the transition from fins to sheets and wires depends on multiple trade-offs, of which channel stress is one: stress in the new architectures should preferably match the one in fins to become a viable contender to FinFET technologies. The introduction of stress in fins, wires and sheets, including devices with alternative channel materials, has been studied by several excellent publications from others [2-5], as well as by us [6-8].This work will focus on TCAD simulations of channel stress in fins, wires and sheets with typical 5nm-node dimensions. We focus on stress generation resulting from the following interacting stressors: 1. Lattice mismatch stress resulting from a different Ge composition between the substrate and the channel 2. lattice mismatch stress between the source/drain regions and the substrate (and channel) 3. for the case of wires and sheets, lattice mismatch stress from the sacrificial layers that are grown in between the wires and sheets, and that are removed in the replacement gate module. All simulations are performed with Sentaurus Process [9].For Si0.5Ge0.5 nanowires on a Si0.75Ge0.25 virtual substrate (Fig. 1) with Si0.5Ge0.5 epitaxially grown source/drains, the longitudinal channel stress at the end of processing in the top, middle and bottom wires is plotted in Fig. 2, and compared to the stress in corresponding fin structures. The following observations can be made: 1. Compressive (i.e. negative) channel stress is found, making this configuration suitable for p-type devices. 2. stresses are strongly dependent on the original fin or wire length, as stress relaxation occurs during fin/ wire cut. 3. there is significant difference between the stress in the top, middle and bottom wire, especially for short wire lengths. 4. (absolute) stresses in wires are higher than in fins, thanks to the presence of the sacrificial layers that limit stress relaxation in wires during wire cut [6].Scaling the devices from 8nm-node to 3nm-node dimensions decreases the absolute stress in fins and wires, Fig. 3. However, significant stress values are predicted down to the smallest nodes, especially for nanowires (> 1GPa). For all nodes, the stress in wires outperforms the one in fins by 50-70%.Fig. 4 shows the channel stress in nanowires and sheets versus device width. Moving from wires (i.e. a device width of 7nm) to larger widths, corresponding to sheets, tends to decrease the volume ratio of the source/drain stressor to the channel. As a consequence, lower absolute stresses are predicted for wider sheets, even when the wire/sheet pitch is scaled along with the device width. In general the highest stresses are found when the channels are thin, provided the mechanical stability of the channel is not compromised, which is something that has not been assessed in this work.Finally, the goal of this work is to study one particular concern for source/drain epitaxy in nanowires and nanosheets: in the presence of internal spacers, the source/drain epi starts from the nanowires as well as from the substrate, and may not join perfectly, leading to stress loss (Fig. 5). This work will perform a worst-case estimate of the stress loss in the presence of various defective interfaces. The TCAD results will be compared with experimentally measured strain using nano-beam diffraction [7-8].

PET expression vector customized for efficient seamless cloning.

Here we present a modification of the widely used pET29 expression vector for use in rapid and straightforward parallel cloning via a gene replacement and Golden Gate strategy. The modification can be applied to other expression vectors for Gram-negative bacteria. We have used the modified vectors to clone large numbers of bacterial natural enzyme variants from genomic and metagenomic sources for applications in biocatalysis.

RETRACTED ARTICLE: Bit-swapping linear feedback shift register (LFSR) for power reduction using pre-charged XOR with multiplexer technique in built in self-test

Testing becomes an inevitable part of the VLSI circuit. All the circuits or products must be verified before delivery. The data collected during testing is used to remove the faulty parts from the products and help to enhance the design and manufacturing process and improve the returns as well. There are several contributions made by researchers which are majorly based on Linear Feedback Shift Register (LFSR), bit swapping LFSR and dual threshold bit swapping LFSR methods. Reduction of delay, power consumptions and fault coverage are considered as major factors from the above methods. The proposed approach uses Bit Swapping-Linear Feedback Shift Register (BS-LFSR) architecture which integrates pre-charge, set-reset and gate replacement with mux techniques have alleviated the inherent drawbacks of linear feedback shift register and produced better results. Pre-charge method is reducing the delay and power consumption there by maximizing the operating frequency angle with high performance. High fault coverage is achieved through set and reset technique. Multiplexers mainly employed to minimize the delay and power consumption. BS-LFSR pattern generators are used to decrease the transition power from high switching action. These are producing an arbitrary test sequences with less power of switching by determining the pretense space between two subsequent designs. The area is reduced with the help of combinational logic. Experimental evaluation is done using ISCAS89 benchmark datasets. From the results, it is inferred that the fault coverage is increased and power consumptions are reduced.

Replacement Gate High-k/Metal Gate nMOSFETs Using a Self-Aligned Halo-Compensated Channel Implant

A device design technique for boosting output resistance (Rout) characteristics of long-channel halo-doped nMOSFETs for replacement gate (RMG) high-k/metal gate (HK/MG) devices is proposed based on numerical simulations. We show that the self-aligned halo-compensated channel implant (HCCI) that is carried out after dummy poly gate removal provides compensation for the conventional halo doping. This can be utilized to mitigate the magnitude of potential drop beyond saturation at the drain end so that the long-channel Rout can be boosted relative to the conventional halo-doped device. In addition, we achieve an improved Vt roll-off behavior, an advantage to hot carrier injection (HCI) characteristics at high voltage operation, and the lowered short-channel drain-induced barrier lowering (DIBL) and intrinsic delay via the optimization of the source/drain (S/D) doping profile. HCCI technique can be implemented using a process flow that is compatible with the RMG HK/MG system-on-chip (SoC) technology in the mass production.

FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

Field Programmable Gate Arrays (FPGA) offers a faster, increasingly adjustable arrangement. Earlier Data Encryption Standard (DES) algorithms have been developed, however it could not keep up with advancement in a technology and it is no longer appropriate for security. With this motivation, this work developed an efficient FPGA implementation of Advanced Encryption Standard (AES) targets to investigate a huge number of security processes followed in the TCP/IP protocol suite and to suggest a novel new architecture for the existing version. The first contribution of the studies turned into to provide the safety for packages of the utility layer protocols. The AES cryptographic encryption, decryption and key management set of rules to for the safety of transmission control protocol/internet protocol (TCP/IP) protocol suite turned into carried out. AES is one of the maximum famous cryptographic algorithms used for records safety. The cost and consumption of power in the AES can be decreased substantially by way of optimizing the structure of AES. This research article projects an implementation based on modification in Mix column in AES techniques which gives a compact structure with efficient mix column Boolean expression the usage of resource sharing architecture and gate replacement method. The ON-chip power utilization and area overhead of the proposed hardware implementation outperforms the preceding work performed in this area. The proposed architecture have been carried out on the most latest virtex 6 lower power Field programmable gate array (FPGA), whereas overhead and on-chip utilization of power are compared with the previous works and it is proved that proposed method has lower area utilization and ON-Chip utilization of power.

Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation

A new type of vertical nanowire (NW)/ nanosheet (NS) field-effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that is compatible with processes used in the mainstream industry is proposed for the VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were used to fabricate pVSAFETs for the first time. Vertical GAA FETs with self-aligned high-k metal gates and a small effective-gate-length variation were obtained. Isotropic qALE, including Si-selective etching of SiGe, was developed to control the diameter/thickness of the NW/NS channels. NWs with a diameter of 10 nm and NSs with a thickness of 20 nm were successfully fabricated, and good device characteristics were obtained. Finally, the device performance was investigated and is discussed in this work.

On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI

We investigate bias temperature instability (BTI) charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals (WFMs). Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at a constant oxide electric field for different WFM stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS replacement gate planar transistors with three selected WFM stacks (representative of high-, standard-, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy,” we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75 eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense

The increasing usage and popularity of the field-programmable gate array (FPGA) systems bring in security concerns. Existing countermeasures are mostly based on the assumption that the computer-aided design (CAD) tools for FPGA configuration are trusted. Unfortunately, this assumption does not always hold. In this paper, we investigate the potential security threats originated from the untrusted CAD tools. Furthermore, we exploit the principle of moving target defense (MTD) to propose an FPGA-oriented MTD (FOMTD) method. The three defense lines in the FOMTD generate uncertainties, from the attacker’s point of view, to thwart hardware Trojan insertion attacks. The theoretical upper bound of the hardware Trojan hit rate for each defense line is provided in this paper. Experimental results show that the proposed defense line 2 and defense line 3 reduce the Trojan hit rate by up to 40% and 91%, respectively, for the scenario where the malicious CAD tool can insert Trojans in the occupied FPGA slices. The proposed gate replacement technique in the defense line 3 further improves the attack resilience and obtains 88% reduction on the Trojan hit rate. Compared to the static redundancy-based Trojan detection method, the proposed method achieves better resilience against Trojan insertions and consumes 50% less dynamic power.

Faster manipulation of large quantum circuits using wire label reference diagrams

Large scale quantum computing is highly anticipated, and quantum circuit design automation needs to keep up with the transition from small scale to large scale problems. Methods to support fast quantum circuit manipulations (e.g. gate replacement, wire reordering, etc.) or specific circuit analysis operations have not been considered important and have been often implemented in a naive manner thus far. For example, quantum circuits are usually represented in term of one-dimensional gate lists or as directed acyclic graphs. Although implementations for quantum circuit manipulations are often only of polynomial complexity, the sheer number of possibilities to consider with increasing scales of quantum computations make these representations highly inefficient – constituting a serious bottleneck. At the same time, quantum circuits have structural characteristics, which allow for more specific and faster approaches. This work utilises these characteristics by introducing a dedicated representation for large quantum circuits, namely wire label reference diagrams. We apply the representation to a set of very common circuit transformations, and develop corresponding solutions which achieve orders of magnitude performance improvements for circuits which include up to 80 000 qubits and 200 000 gates. The implementation of the proposed method is available online.

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

In this paper, we demonstrate InGaAs FinFETs 3-D sequentially (3DS) integrated on top of a fully depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. We demonstrate that the low thermal budget of the top layer process does not affect the lower level FETs performance. An on-current of 200 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V) is achieved, representing the highest reported for 3DS integrated III-V FETs on silicon, showing a 50% improvement in RON compared to previous work. The achieved improved performance can be attributed to the introduction of spacers, doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

An Efficient Technique to Reverse Engineer Minterm Protection Based Camouflaged Circuit

Integrated circuit (IC) camouflaging technique has been applied as a countermeasure against reverse engineering (RE). However, its effectiveness is threatened by a boolean satisfiability (SAT) based de-camouflaging attack, which is able to restore the camouflaged circuit within only minutes. As a defense to the SAT-based de-camouflaging attack, a brand new camouflaging strategy (called CamoPerturb) has been proposed recently, which perturbs one minterm by changing one gate’s functionality and then restores the perturbed circuit with a separated camouflaged block, achieving good resistance against the SAT-based attack. In this paper, we analyze the security vulnerabilities of CamoPerturb by illustrating the mechanism of minterm perturbation induced by gate replacement, then propose an attack to restore the changed gate’s functionality, and recover the camouflaged circuit. The attack algorithm is facilitated by sensitization and implication principles in automatic test pattern generation (ATPG) techniques. Experimental results demonstrate that our method is able to restore the camouflaged circuits with very little time consumption.