Remote FPGA Research Articles

Remote side-channel analysis of the loop PUF using a TDC-based voltage sensor

FPGAs promise significant performance improvements for several computations in cloud applications. However, their shared use in multi-tenant scenarios makes them susceptible to attacks. Different from classical scenarios, where the attacker has hardware access to the device, in cloud scenarios the attack is possible only from remote. As a consequence remote SCA attacks gained increasing attention in the last years. These attacks exploit that attacker and victim share with the same FPGA also the same PDN so that operation-dependent voltage fluctuations caused by the victim’s IP are observable by a voltage sensor of the attacker. While previous attacks in this domain focused on cryptographic algorithms, this work provides insights in an attack on a PUF primitive, the Loop PUF. This primitive is an interesting target for the attack since it might be used, e.g., for storing or deriving secret keys on a remote FPGA. We introduce and discuss the setup of such a remote SCA using a TDC-based voltage sensor. With this sensor, we compare the performance of classical and remote SCA attacks on the Loop PUF using two different Artix-7 FPGA and demonstrate and discuss findings regarding sampling frequency and placement. This work extends and deepens the analysis from a previously published analysis at the ASHES Workshop 2022. In particular, it provides insights into the influence of repeated measurements, measurement time, and usage of multiple TDCs on the attack performance. It also discusses the applicability of the attack to further RO-based PUF primitives. Overall the results show that remote SCA attacks on PUFs in a multi-tenant FPGA scenario have to be considered as a severe attack vector in the future.

FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA

With the emerging cloud-computing development, FPGAs are being integrated with cloud servers for higher performance. Recently, it has been explored to enable multiple users to share the hardware resources of a remote FPGA, i.e., to execute their own applications simultaneously. Although being a promising technique, multi-tenant FPGA unfortunately brings its unique security concerns. It has been demonstrated that the capacitive crosstalk between FPGA long-wires can be a side-channel to extract secret information, giving adversaries the opportunity to implement crosstalk-based side-channel attacks. Moreover, recent work reveals that medium-wires and multiplexers in configurable logic block (CLB) are also vulnerable to crosstalk-based information leakage. In this work, we propose FPGAPRO: a defense framework leveraging P lacement, R outing, and O bfuscation to mitigate the secret leakage on FPGA components, including long-wires, medium-wires, and logic elements in CLB. As a user-friendly defense strategy, FPGAPRO focuses on protecting the security-sensitive instances meanwhile considering critical path delay for performance maintenance. As the proof-of-concept, the experimental result demonstrates that FPGAPRO can effectively reduce the crosstalk-caused side-channel leakage by 138 times. Besides, the performance analysis shows that this strategy prevents the maximum frequency from timing violation.

A 1553B Remote Terminal FPGA Interface Design Based on BU61580

In order to provide convenience for users to access the MIL-STD-1553B bus, a remote terminal FPGA interface is developed in this paper using 1553B protocol and BU61580 protocol chip. 1553B communication is implemented by a protocol chip which is controlled by FPGA logics. A simple port for users to receive and transmit data is designed. The operation mechanism of FPGA logics and the implementing methods of FPGA function modules are described in detail. Test results show the validity.

REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB

In today’s world, e-learning has proved to be a very useful technology. In addition to e-learning, e-labs are also being implemented. E-labs can be either virtual or remote. This paper is an initiative to create a remote fpga lab. The implementation of the same is also complete. The base kit used is the spartan 3E family of FPGA which is interfaced with an arduino board through a LabView interface for providing the input into the FPGA from the remote desktop. The outputs are displayed in the remote computer. The outputs can also be viewed through the webcam. The main intention of this project is to make distance learning easy. It is also an advantage for students as additional experiments that do not come under the syllabus can be performed anytime, anywhere.

Security Enhancement of Remote FPGA Devices By a Low Cost Embedded Network Processor

Security Enhancement of Remote FPGA Devices By a Low Cost Embedded Network Processor

Security Enhancement of Remote FPGA Devices By a Low Cost Embedded Network Processor

The incredible growth of FPGA capabilities in recent years and the new included features have made them more and more attractive for numerous embedded systems. There is however an important shortcoming concerning security of data and design. Data security implies the protection of the FPGA application in the sense that the data inside the circuit and the data transferred to/from the peripheral circuits during the communication are protected. This paper suggests a new method to support the security of any FPGA platform using network processor technology. Low cost IP2022 UBICOM network processor was used as a security shield in front of any FPGA device. It was supplied with the necessary security methods such as AES ciphering engine, SHA-1, HMAC and an embedded firewall to provide confidentiality, integrity, authenticity, and packets filtering features.

Remote FPGA Lab for Enhancing Learning of Digital Systems

Learning in digital systems can be enhanced through applying a learn-by-doing approach on practical hardware systems and by using Web-based technology to visualize and animate hardware behavior. The authors have reported the Web-based Remote FPGA Lab (RFL) which provides a novel, real-time control and visualization interface to a remote, always-on FPGA hardware implementation. The RFL helps students to understand and reason about digital systems operation, using interactive animation of signal behavior in an executing digital logic system, at any level of the design hierarchy. The RFL supports the creation of real-time interactive digital systems teaching demos. The article presents student RFL usage data and survey data which highlight improved student engagement, learning and achievement. The article describes the RFL architecture, communication interface, Web page functionality, user access administration and database management. The article also describes the RFLGen program, developed to automate user design integration into the Xilinx ISE VHDL-based RFL project wrapper for creation of FPGA configuration bitstreams and RFL animations.

A readout unit for high rate applications

The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via the PCI bus, which is hosted by a networked microprocessor card. Its main tasks are remote FPGA configuration and initialization of the PCI cards. The RU hardware architecture has been optimized for a throughput of up to 200 MB/s at a 1 MHz trigger rate, as required by the most demanding application, the LHCb level-1 trigger network. A custom traffic-scheduling link is available for applications like pipelined destination address allocation.