Regular Communication Patterns Research Articles

EA4RCA: Efficient AIE accelerator design framework for regular Communication-Avoiding Algorithm

With the introduction of the Adaptive Intelligence Engine (AIE), the Versal Adaptive Compute Acceleration Platform (Versal ACAP) has garnered great attention. However, the current focus of Vitis Libraries and limited research has mainly been on how to invoke AIE modules, without delving into a thorough discussion on effectively utilizing AIE in its typical use cases. As a result, the widespread adoption of Versal ACAP has been restricted. The Communication Avoidance (CA) algorithm is considered a typical application within the AIE architecture. Nevertheless, the effective utilization of AIE in CA applications remains an area that requires further exploration. We propose a top-down customized design framework, EA4RCA (Efficient AIE accelerator design framework for regular Communication-Avoiding Algorithm), specifically tailored for CA algorithms with regular communication patterns, and equipped with AIE Graph Code Generator software to accelerate the AIE design process. The primary objective of this framework is to maximize the performance of AIE while incorporating high-speed data streaming services. Experiments show that for the RCA algorithm Filter2D and Matrix Multiple (MM) with lower communication requirements and the RCA algorithm FFT with higher communication requirements, the accelerators implemented by the RA4RCA framework achieve the highest throughput improvements of 22.19x, 1.05x and 3.88x compared with the current highest performance acceleration scheme (SOTA), and the highest energy efficiency improvements of 6.11x, 1.30x and 7.00x.

An investigation of communication in virtual high schools

<p>Virtual schooling is an increasing trend for secondary education. Research of the communication practices in virtual schools has provided a myriad of suggestions for virtual school policies. The purpose of this qualitative study was to investigate the activities and processes involved in the daily rituals of virtual school teachers and learners with the goal of determining how regular phone calls by teachers contributed to the work habits of students. Eight virtual teachers were observed attempting to contact more than 60 struggling learners. Phone conversations with 12 of these learners showed that teachers repeatedly attempted to help them. Eleven students were interviewed and indicated preferences for written communications. Ten additional teachers who were interviewed emphasized the difficulty they had in reaching students by phone and the lack of student responses to phone-call attempts. The teachers in the study provided additional data regarding their regular communication patterns. Archival records from more than 100 contact attempts showed that approximately 20% of the students responded to teacher phone calls and less than half of these students completed the work requested. The interview data revealed that teachers believe written communications or multiple forms of communication may be more effective than regular phone calls. Future research should extend current research by expanding on sample size and investigating alternate methods of communication. Further investigation of learner responses to phone calls and of nonresponsive students could add to this data.</p><p> </p><p> </p><p> </p><p> </p>

HIERARCHICAL MAPPING FOR HPC APPLICATIONS

As the high performance computing systems scale up, mapping the tasks of a parallel application onto physical processors to allow efficient communication becomes one of the critical performance issues. Existing algorithms were usually designed to map applications with regular communication patterns. Their mapping criterion usually overlooks the size of communicated messages, which is the primary factor of communication time. In addition, most of their time complexities are too high to process large scale problems. In this paper, we present a hierarchical mapping algorithm (HMA), which is capable of mapping applications with irregular communication patterns. It first partitions tasks according to their run-time communication information. The tasks that communicate with each other more frequently are regarded as strongly connected. Based on their connectivity strength, the tasks are partitioned into supernodes based on the algorithms in spectral graph theory. The hierarchical partitioning reduces the mapping algorithm complexity to achieve scalability. Finally, the run-time communication information will be used again in fine tuning to explore better mappings. With the experiments, we show how the mapping algorithm helps to reduce the point-to-point communication time for the PDGEMM, a ScaLAPACK matrix multiplication computation kernel, up to 20% and the AMG2006, a tier 1 application of the Sequoia benchmark, up to 7%.

Passive-Logging Attacks Against Anonymous Communications Systems

Using analysis, simulation, and experimentation, we examine the threat against anonymous communications posed by passive-logging attacks. In previous work, we analyzed the success of such attacks under various assumptions. Here, we evaluate the effects of these assumptions more closely. First, we analyze the Onion Routing-based model used in prior work in which a fixed set of nodes remains in the system indefinitely. We show that for this model, by removing the assumption of uniformly random selection of nodes for placement in the path, initiators can greatly improve their anonymity. Second, we show by simulation that attack times are significantly lower in practice than bounds given by analytical results from prior work. Third, we analyze the effects of a dynamic membership model, in which nodes are allowed to join and leave the system; we show that all known defenses fail more quickly when the assumption of a static node set is relaxed. Fourth, intersection attacks against peer-to-peer systems are shown to be an additional danger, either on their own or in conjunction with the predecessor attack. Finally, we address the question of whether the regular communication patterns required by the attacks exist in real traffic. We collected and analyzed the Web requests of users to determine the extent to which basic patterns can be found. We show that, for our study, frequent and repeated communication to the same Web site is common.

What Goes Online Comes Offline: Knowledge Management System Use in a Soft Bureaucracy

This paper investigates when and how online practices (i.e. practices of management and use of web-based Information Technology) impact offline practices (i.e. regular work practices and communication patterns) within a bureaucratic environment. A case study of implementation and use of a Knowledge Management System by members of a network of practice within the bureaucratic environment of a public administration is interpreted through a situated learning perspective. This lens helps us to understand the process of emergence of continuity between online and offline practices. Findings indicate that the constructed continuity within the network of practice emerged from a combination of structural changes in the environment and of the involvement of key actors who actively encouraged others to integrate their online practices into their regular activities. The paper helps us to understand the processes of construction of continuity of online and offline practices and the bounded impacts of this continuity within bureaucracies. Such continuity may contribute to the circumscribed emergence of a soft bureaucracy in which professional competences and exchanges are recognized and encouraged, while the structural features of decision making, control, and resource allocation remain unchanged.

Cache aware optimization of stream programs

Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly prevalent in the embedded domain. We exploit the widespread parallelism and regular communication patterns in stream programs to formulate a set of cache aware optimizations that automatically improve instruction and data locality. Our work is in the context of the Synchronous Dataflow model, in which a program is described as a graph of independent actors that communicate over channels. The communication rates between actors are known at compile time, allowing the compiler to statically model the caching behavior.We present three cache aware optimizations: 1) execution scaling, which judiciously repeats actor executions to improve instruction locality, 2) cache aware fusion, which combines adjacent actors while respecting instruction cache constraints, and 3) scalar replacement, which converts certain data buffers into a sequence of scalar variables that can be register allocated. The optimizations are founded upon a simple and intuitive model that quantifies the temporal locality for a sequence of actor executions. Our implementation of cache aware optimizations in the StreamIt compiler yields a 249% average speedup (over unoptimized code) for our streaming benchmark suite on a StrongARM 1110 processor. The optimizations also yield a 154% speedup on a Pentium 3 and a 152% speedup on an Itanium 2.

Analysis of new pivoting strategy for the LDLT decomposition on a multiprocessor system with distributed memory

It is well known that optimal control techniques can provide the ability to design suitable strategies, however, the on-line computing requirements are excessive. The normal procedure is to make various assumptions so that the processing demands are reduced. Based on these assumptions, sequences of linear-quadratic-performance optimal control problems need to be considered. These in turn give rise to standard two-point-boundary-value problems. The solution to such problems involves the computation of the algebraic Riccati equations (AREs). The block diagonal decomposition LDLT, is the key step for those algorithms based on the matrix sign function that are used in solving the AREs. The last few years have witnessed a tremendous effort towards the development of reliable algorithms to solve the AREs and apply it in industrial situations. However, all the implementations and testing of the proposed algorithms have been performed on powerful machines thereby limiting their practical application. The authors present a pivoting strategy that: (i) requires only one-dimension of the matrix for the selection of the pivot; (ii) generates regular communication patterns; and (iii) establishes a software mechanism for the development of fault tolerant applications. The results obtained from a multiprocessor system with a one-way ring topology indicate that the block diagonal LDLT decomposition is a true candidate for real-time use and fault tolerant applications and also as a framework-test for the LAPACK library.

Compiler-Optimized Simulation of Large-Scale Applications on High Performance Architectures

In this paper, we propose and evaluate practical, automatic techniques that exploit compiler analysis to facilitate simulation of very large message-passing systems. We use compiler techniques and a compiler-synthesized static task graph model to identify the subset of the computations whose values have no significant effect on the performance of the program, and to generate symbolic estimates of the execution times of these computations. For programs with regular computation and communication patterns, this information allows us to avoid executing or simulating large portions of the computational code during the simulation. It also allows us to avoid performing some of the message data transfers, while still simulating the message performance in detail. We have used these techniques to integrate the MPI-Sim parallel simulator at UCLA with the Rice dHPF compiler infrastructure. We evaluate the accuracy and benefits of these techniques for three standard message-passing benchmarks on a wide range of problem and system sizes. The optimized simulator has errors of less than 16% compared with direct program measurement in all the cases we studied, and typically much smaller errors. Furthermore, it requires factors of 5 to 2000 less memory and up to a factor of 10 less time to execute than the original simulator. These dramatic savings allow us to simulate regular message-passing programs on systems and problem sizes 10 to 100 times larger than is possible with the original simulator, or other current state-of-the-art simulators.

Approximations for the general block distribution of a matrix

The general block distribution of a matrix is a rectilinear partition of the matrix into orthogonal blocks such that the maximum sum of the elements within a single block is minimized. This corresponds to partitioning the matrix onto parallel processors so as to minimize processor load while maintaining regular communication patterns. Applications of the problem include various parallel sparse matrix computations, compilers for high-performance languages, particle in cell computations, video and image compression, and simulations associated with a communication network. We analyze the performance guarantee of a natural and practical heuristic based on iterative refinement, which has previously been shown to give good empirical results. When p2 is the number of blocks, we show that the tight performance ratio is θ(p). When the matrix has rows of large cost, the details of the objective function of the algorithm are shown to be important, since a naive implementation can lead to a Ω(p) performance ratio. Extensions to more general cost functions, higher-dimensional arrays, and randomized initial configurations are also considered.

Dynamic process composition and communication patterns in irregularly structured applications

In this paper we describe one experiment in which a new co-ordination language, called Manifold, is used to restructure an existing sequential Fortran 77 code from computational fluid dynamics (CFD), into a parallel application. Manifold is a co-ordination language developed at CWI (Centrum voor Wiskunde en Informatica) in the Netherlands. It is very well suited for applications involving dynamic process creation and dynamically changing (ir)regular communication patterns among sets of independent concurrent co-operating processes. With a simple but generic master/worker protocol, written in the Manifold language, we are able to reuse the existing code without rethinking or rewriting it. The performance evaluation of a standard 3D CFD problem shows that Manifold performs very well. Copyright © 2000 John Wiley & Sons, Ltd.

Dynamic process composition and communication patterns in irregularly structured applications

In this paper we describe one experiment in which a new co-ordination language, called Manifold, is used to restructure an existing sequential Fortran 77 code from computational fluid dynamics (CFD), into a parallel application. Manifold is a co-ordination language developed at CWI (Centrum voor Wiskunde en Informatica) in the Netherlands. It is very well suited for applications involving dynamic process creation and dynamically changing (ir)regular communication patterns among sets of independent concurrent co-operating processes. With a simple but generic master/worker protocol, written in the Manifold language, we are able to reuse the existing code without rethinking or rewriting it. The performance evaluation of a standard 3D CFD problem shows that Manifold performs very well. Copyright © 2000 John Wiley & Sons, Ltd.

Producer-consumer communication in distributed shared memory multiprocessors

The shared memory abstraction supported by hardware based distributed shared memory (DSM) multiprocessors is an inherently consumer driven means of communication. When a process requires data, it retrieves them from the global shared memory. In distributed cache coherent systems, the data may reside in a remote memory module or in the producer's cache. Producer initiated mechanisms reduce communication latency by sending data to the consumer as soon as they are produced. We classify producer initiated mechanisms as implicit or explicit, according to whether the producer must know the identity of the consumer when data are transmitted. Explicit schemes include data forwarding and message passing. Implicit schemes include update based coherence, selective updates, and cache based locks. Several of these mechanisms are evaluated for performance and sensitivity to network parameters, using a common simulated architecture and a set of application kernel benchmarks. StreamLine, a cache based message passing mechanism, provides the best performance on the benchmarks with regular communication patterns. Forwarding write and cache based locks are also among the best performing producer initiated mechanisms. Consumer initiated prefetch, however, has good average performance and is the least expensive to implement.

Data-parallel load balancing strategies

Programming irregular and dynamic data-parallel algorithms must consider the effect of data distribution. The implementation of a load balancing algorithm is quite a difficult task for the programmer. However, a load balancing strategy may be developed independently of the application. The integration of such a strategy into the data-parallel algorithm may be relevant to a library or a data-parallel compiler run-time. We propose load distribution data-parallel algorithms for a class of irregular data-parallel algorithms called stack algorithms. Our algorithms allow the use of regular and/or irregular communication patterns to exchange the works between processors. The results of theoretical analysis of these algorithms are presented. They allow different load balancing algorithms to be compared and the identification of criteria to choose between them.

SCALABLE MULTIFOLDED HYPERCUBES FOR VERSATILE PARALLEL COMPUTERS

This paper introduces the family of scalable multifolded hypercube (SMH) architectures for parallel computers. Scalability and versatility at resonable cost are the major characteristics of these architectures. SMHs perform comparable to generalized hypercubes for important classes of algorithms that use regular communication patterns. In addition, they often achieve better performance than the popular direct binary hypercubes because they can emulate efficiently a powerful family of multifolded direct binary hypercubes. Extensive comparison of cost with binary and generalized hypercubes is also included. The hardware cost of SMH's is shown to be even lower than that of fat trees. Therefore, SMH's are viable candidates for the construction of versatile parallel computers.

Annealed embeddings of communication patterns in an interconnection cached network

The communication needs of many parallel applications exhibit what we call switching locality. In such applications, each computation entity (process, thread, etc.) tends to restrict its communication to a small set of other entities. The physical location or proximity of these entities can be arbitrary, as long as the communication degree is small. The Interconnection Cached Network (ICN) is a reconfigurable network ideally suited for exploiting such locality. The use of fast small crossbar switches (Interconnection Caches) with a larger, but slower, reconfigurable network (optimized for connectivity) lets the ICN adapt to the communication requirements of individual applications, potentially achieving higher performance. Embedding communication patterns efficiently in an ICN, requires finding a bounded l-contraction of the underlying communication graph. The problem of identifying whether a graph has a bounded and l-contraction for a given integer l is known to be NP-complete for l>2. We describe a heuristic algorithm based on simulated annealing for this problem. We test the effectiveness of our approach by using it to embed graphs, representing regular communication patterns, for which the best solutions are deterministically known. The algorithm does not rely on any structural information of the communication pattern and is therefore applicable to irregular patterns as well. The results of applying our heuristics to embed such irregular graphs are also presented.

A systolic algorithm for hidden surface removal

With the advent of VLSI it has become possible to map parallel algorithms for compute-bound problems directly on silicon. Systolic architecture is very good candidate for VLSI implementation because of its regular and simple design, and regular communication pattern. In this paper, a systolic algorithm and corresponding systolic architecture, a linear systolic array, for the scanline-based hidden surface removal problem in three-dimensional computer graphics have been proposed. The algorithm is based on the concept of sample spans or intervals. The worst case time taken by the algorithm is O( n), n being the number of segments in a scanline. The time taken by the algorithm for a given scene depends on the scene itself, and on an average considerable improvement over the worst case behaviour is expected. A pipeline scheme for handling the I/O process has also been proposed which is suitable for VLSI implementation of the algorithm.