Register-transfer Level Power Estimation Research Articles

<I>SCoPE</I>: Statistical Regression Based Power Models for Co-Processors Power Estimation

Simulation of a System-on-Chip (SoC) design at register transfer level (RTL) containing various co-processors and logic units is often too time consuming. This poses a problem for power estimation because the best available tools for power estimation today (e.g., PowerTheater) require RTL simulation. Therefore, it is important to obtain abstract power models of the various components that can be utilized at levels higher than the RTL. Availability of such power models can speed up power estimation of the entire chip without resorting to full-chip simulation of the RTL model. However, to be useful, power estimates obtained from such abstract models must be sufficiently accurate. In this paper, we present Statistical regression based Co-processor Power Estimation (SCoPE) methodology, which utilizes cycle accurate Finite State Machine with Datapath (FSMD) models for various co-processors to obtain accurate power estimation. We show through a number of experiments that hardware design implemented on 180 nm technology library show no more than 6% worst-case loss of accuracy, and 9% for 90 nm, with respect to the state-of-the-art RTL power estimation techniques.

RTL-Aware Cycle-Accurate Functional Power Estimation

Most methods for hardware power estimation operate at the register-transfer level (RTL) or lower levels of design abstraction. Since cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows, power estimation can potentially benefit from the inherent increase in the efficiency of a cycle-based functional simulation. However, attempts at power estimation for functional descriptions have suffered from a poor accuracy because the design decisions performed during their synthesis lead to an unavoidable large uncertainty in any power estimate that is based solely on the functional description. The authors propose a methodology for a CAFD power estimation that combines the accuracy achieved by structural RTL power estimation with the efficiency of cycle-accurate functional simulation. This goal is achieved by viewing a CAFD as an abstraction of a specific known RTL implementation that is synthesized from it. The authors identify correlations between a CAFD and its RTL implementation and back-annotate information into the CAFD solely for power estimation. The resulting RTL-aware CAFD contains a layer of code that instantiates virtual placeholders for RTL components and maps values of CAFD variables into the RTL components' inputs/outputs, thus enabling efficient and accurate power estimation. Power estimation is performed in the proposed methodology by simply cosimulating the RTL-aware CAFD with a simulatable power-model library that contains power macromodels for each RTL component. Techniques to further improve the speed of CAFD power estimation through the use of control-state-based adaptive power sampling are presented. The authors have implemented and evaluated the proposed techniques in the context of a commercial C-based hardware design flow. Experiments with a number of large industrial designs (up to 1 000 000 gates) demonstrate that the proposed methodology achieves an accuracy very close to RTL power estimation with two-three orders of magnitude speedup in estimation times

RTL power estimation in an HDL-based design flow

Power estimation at the register-transfer level (RTL) is usually narrowed down to the problem of building accurate power models for the modules corresponding to RTL operators. It is shown that, when RTL power estimation is integrated into a realistic design flow based on an HDL description, other types of primitives need to be accurately modelled. In particular, a significant part of the RTL functionality is realised by sparse logic elements. The proposed estimation strategy replaces the low-effort synthesis that is typically used for this type of fine-grain primitives with an empirical power model based on parameters that can be extracted from either the internal representation of the design or from RTL simulation data. The model can be made scalable with respect to technology, and provides very good accuracy (13% on average, measured on a set of industrial benchmarks). Using a similar statistical paradigm, accurate (about 20% average error) models for the power consumption of internal wires are also presented.

Register-transfer-level power estimation based on technology decomposition

A new register-transfer level power estimation technique based on technology decomposition is presented. The power dissipation is estimated by predicting the node distribution, capacitance distribution and entropy distribution of the minimum area implementation of a given Boolean functional description. This approach makes it possible to capture the structural information of a circuit without actual gate-level implementation. Compared to the exact values of power obtained from a logic synthesis system, the estimator produces an average percentage error of 7.5%, which is a significant improvement over previous techniques.

Regression-based RTL power modeling

Register-transfer level (RTL) power estimation is a key feature for synthesis-based design flows. The main challenge in establishing a sound RTL power estimation methodology is the construction of accurate, yet efficient, models of the power dissipation of functional macros. Such models should be automatically built, and should produce reliable average power estimates. In this paper we propose a general methodology for building and tuning RTL power models. We address both hard macros (presynthesized functional blocks)and soft macros (functional units for which only a synthesizable HDL description is provided). We exploit linear regression and its nonparametric extensions to express the dependency of power dissipation on input and output activity. Bottom-up off-line characterization of regression-based power macromodels is discussed in detail. Moreover, we introduce a low overhead on-line characterization method for enhancing the accuracy of off-line characterization.