Reed-Muller Forms Research Articles

Cube‐Based Synthesis of ESOPs for Large Functions

This study focuses on low-complexity synthesis of Exclusive-or sum-of-products expansions (ESOPs). A scalable cube-based method, which only uses iterative executions of cube intersection and subcover minimization for cube set expressions, is presented to obtain quasi-optimal ESOPs for completely specified multi-output functions. For deriving canonical Reed-Muller (RM) forms, four conversion rules of cubes are proposed to achieve fast conversion between a canonical form and an Exclusiveor sum-of-products (ESOP) or between different canonical forms. Numerical examples are given to verify the correctness of cube-based minimization and conversion methods. The proposed methods have been implemented in C language and tested on a large set of MCNC benchmark functions (ranging from 5 to 201 inputs). Experimental results show that, compared with existing methods, ours can reduce the number of cubes by 27% and save the CPU time by 74% on average in the final solution of minimization, and consume less time as well during the conversion process. As a whole, our methods are efficient in terms of both memory space and CPU time and can be able to deal with very large functions.

КОНЦЕПЦІЯ ОПТИМАЛЬНОЇ ФОРМИ ПРЕДСТАВЛЕННЯ ЛОГІЧНИХ ФУНКЦІЙ ТА ПРОБЛЕМИ ЇЇ ВПРОВАДЖЕННЯ

In scientific publications and conducted studies, the possibility of representing logical functions (LF) in alternative forms of representation is demonstrated, the characteristic feature of which is a polynomial entity, which reduces to the representation of LF in the form of series different from the traditional classical representation by adding members of a series - in particular, for an algebraic form, the addition is carried out algebraically with weight coefficients, and in the case of the use of the Reed-Muller form addition is made for mod 2. The results of complete sets of logical functions studies proved that the traditional classical form does not always ensure the minimality of indicators for the structural complexity of the logical functions implementation, which makes relevant further steps in determining the optimal forms for representing logical functions in the problems of discrete devices analysis and synthesis. The implementation of the combination scheme for a given logical function from n arguments is carried out by some set of variants of structures. In problems of analysis and synthesis of combinational circuits of discrete devices it is necessary to evaluate the quality of their possible structures, to provide identification and selection of the most successful or optimal ones. The concept of the logical functions optimal form of representation is presented in the article as an important direction of structural perfection of discrete devices on the basis of their logical functions realization in alternative forms of representation. The existence of the OFR-concept, which takes into account different forms of representation, makes it highly efficient to use alternative forms of logical functions representation from the point of the structural complexity parameters of the combinational schemes implementation in comparison with traditional classical form. The article outlines the factors for the further improvement of the OFR-concept by filling it with new scientific achievements, which will allow to completely or partially remove difficulties with the introduction of the optimal FR into broad engineering practice

An extended Green-Sasao hierarchy of canonical ternary Galois forms and Universal Logic Modules

A new extended Green-Sasao hierarchy of families and forms with a new sub-family for many-valued Reed-Muller logic is introduced. Recently, two families of binary canonical Reed-Muller forms, called Inclusive Forms (IFs) and Generalized Inclusive Forms (GIFs) have been proposed, where the second family was the first to include all minimum Exclusive Sum-Of-Products (ESOPs). In this paper, we propose, analogously to the binary case, two general families of canonical ternary Reed-Muller forms, called Ternary Inclusive Forms (TIFs) and their generalization of Ternary Generalized Inclusive Forms (TGIFs), where the second family includes minimum Galois Field Sum-Of-Products (GFSOPs) over ternary Galois field GF(3). One of the basic motivations in this work is the application of these TIFs and TGIFs to find the minimum GFSOP for many-valued input-output functions within logic synthesis, where a GFSOP minimizer based on IF polarity can be used to minimize the many-valued GFSOP expression for any given function. The realization of the presented S/D trees using Universal Logic Modules (ULMs) is also introduced, whereULMs are complete systems that can implement all possible logic functions utilizing the corresponding S/D expansions of many-valued Shannon and Davio spectral transforms.

Secure Testable S-box Architecture for Cryptographic Hardware Implementation

It has been recently shown that observability of design for testability techniques compromises cryptographic hardware implementation security in a straightforward manner. During test, the chip can be configured so that it is possible to observe temporal data resulting from the encryption process of a plaintext that eventually exposes the secret key. To this end, we propose a C-testable S-box implementation which is one of the most complex blocks in advanced encryption standard hardware implementation. We divide the S-box structure into a positive polarity Reed–Muller form and tested independently using a BIST circuit. The proposed structure does not use any scan chain for testability, hence avoiding the vulnerability of the chip during testing. Only 14 constant vectors are sufficient to achieve 100% fault coverage in the S-box. The C-testable feature comes with an extra hardware overhead of 15 per cent. By introducing an on-chip testing feature one can avoid potential paths for introducing unwanted access into the on-chip security blocks.

Novel Synthesis and Optimization of Multi-Level Mixed Polarity Reed-Muller Functions

Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum shrinkage (GSS), elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented to derive a compact Multi-level Mixed Polarity Reed-Muller Form (MMPRMF) starting from a given fixed polarity truth vector. The results show that a significant area improvement can be made compared with published results.

Generalized reed-muller forms as a tool to detect symmetries

This comment relates to two published articles by Tsai et al. (ibid. vol.45(1), 1996 and vol.46(2), 1997) that used four types of two-variable Boolean symmetries and explained their transitivity conditions and relations with Reed-Muller transform. We show that some research in this area had been done earlier about which the authors are unaware.

Power minimization of FPRM functions based on polarity conversion

For an n-variable Boolean function, there are 2n fixed polarity Reed-Muller (FPRM) forms. In this paper, a frame of power dissipation estimation for FPRM functions is presented and the polarity conversion is introduced to minimize the power for FPRM functions. Based on searching the best polarity for low power dissipation, an optimal algorithm is proposed and implemented in C. The algorithm is tested on seven single output functions from MCNC benchmark circuits. The experimental results are shown in this paper.

Efficient polarity conversion for large Boolean functions

The concept of polarity for canonical sum-of-products (SOP) Boolean functions is introduced. This facilitates efficient conversion between SOP and fixed polarity Reed-Muller (FPRM) forms. New algorithms are presented for the bidirectional conversion between the two paradigms. Multiple segment and multiple pointer techniques are employed to achieve fast conversion for large Boolean functions. Experimental results are given using a personal computer with a Cyrix 6x86-166 CPU and 32MB RAM. The results show that the algorithm is very efficient in terms of time and space for large Boolean functions.

Boolean functions classification via fixed polarity Reed-Muller forms

In this paper, we present a new method to characterize completely specified Boolean functions. The central theme of the classification is the functional equivalence (a.k.a. Boolean matching). Two Boolean functions are equivalent if there exists input permutation, input negation, or output negation that can transform one function to the other. We have derived a method that can efficiently identify equivalence classes of Boolean functions. The well-known canonical Fixed Polarity Reed-Muller (FPRM) forms are used as a powerful analysis tool. The necessary transformations to derive one function from the other are inherent in the FPRM representations. To identify uniquely each equivalence class, a set of well-known characteristics of Boolean functions and their variables (including linearity, symmetry, total symmetry, self-complement, and self-duality) are employed. It is shown that all the equivalence classes of four-variable functions are uniquely identified where majority of the classes have a single FPRM form as their representative. The Boolean matching has applications in technology mapping and in design of standard cell libraries.

Generalized Reed-Muller forms as a tool to detect symmetries

In this paper, we present a new method for detecting groups of symmetric variables of completely specified Boolean functions. The canonical Generalized Reed-Muller (GRM) forms are used as a powerful analysis tool. To reduce the search space we have developed a set of signatures that allow us to identify quickly sets of potentially symmetric variables. Our approach allows for detecting symmetries of any number of inputs simultaneously. Totally symmetric functions can be detected very quickly. The traditional definitions of symmetry have also been extended to include more types. This extension has the advantage of grouping input variables into more classes. Experiments have been performed on MCNC benchmark cases and the results verify the efficiency of our method.

Complexity of Boolean functions in the class of polarized polynomial forms

It is proved that values of Shannon functions in the class of polarized polynomial forms (generalized Reed-Muller forms) coincide for classes of all Boolean functions and all symmetric Boolean functions; a formula computing estimates for these functions is derived.

Minimisation of fixed-polarity AND/XOR canonical networks

A method for extracting the cubes of the generalised Reed-Muller (GRM) form of a Boolean function with a given polarity is presented. The method does not require exponential space and time complexity and it achieves the lower-bound time complexity. The proof of the method's correctness constitutes the first half of the paper. Also, a separate heuristic algorithm to find the optimal polarity that requires the least number of cubes in the GRM representation is proposed. The algorithm is fast and derives the polarity for variables and extracts all cubes simultaneously. It is based on the concept of a Boolean centre for vertices, which emulates the centre of gravity concept in geometry. The experimental results for the heuristic algorithm agree strongly with the authors observations and analysis.

Tabular simplification method for switching functions expressed in Reed-Muller algebraic form

A tabulation method for the simplification of arbitrary modulo-2 sums-of-products expressions is described. The concept of the factorant is introduced and the means whereby the factorant structure of an expression can be determined is described. The simplified form is then expressed as an optimum sum of factorants which has the same truth vector as the original expression. The method avoids the use of large matrices or maps and is limited more by the number of product terms in the original expression than by the number of variables. The effectiveness of the procedure and modified versions of the basic algorithm are assessed by applying these to a large number of randomly generated expressions.

Reed-Muller universal logic module networks

The paper describes Reed-Muller universal logic modules (RM-ULMs) and their use for the implementation of logic functions given in Reed-Muller (RM) form. A programmed algorithm is presented for the synthesis and optimisation of RM-ULM networks. The level-by-level minimisation procedure is based on the selection of control variables at different levels with the aim of maximising the number of discontinued branches and hence minimising the number of modules required to implement a given function. The algorithm is programmed in Fortran and can be used to realise fixed-polarity generalised Reed-Muller (GRM) expansions of any polarity and any number of variables.

Canonical restricted mixed-polarity exclusive-OR sums of products and the efficient algorithm for their minimisation

The concept of canonical restricted mixed polarity (CRMP) exclusive-OR sum of products forms is introduced. The CRMP forms include the inconsistent canonical Reed-Muller forms and the fixed-polarity Reed-Muller (FPRM) forms as special cases. The set of CRMP forms is included in the set of exclusive-OR sum-of-product (ESOP) expressions. An attempt to characterise minimal CRMP forms for completely specified Boolean functions is presented as well as an insight into the complexity of computation needed to find such a form. Some fundamental properties unique to CRMPs are proven. It is also proven that the upper bound on the number of terms in the CRMP form is smaller than that in the conventional normal forms and equal to that of the ESOPs. A theorem providing a lower bound on the number of CRMP terms is given. Finally, based on these theoretical results, a heuristic algorithm and its implementation to obtain a quasiminimal CRMP form for a multioutput function are presented.

Multiple valued input generalised reed—muller forms

The concept of canonical multiple valued input generalised Reed-Muller (MIGRM) forms is introduced. The MIGRM is a direct extension of the well known generalised Reed-Muller (GRM) forms to the logic with multiple valued inputs. The concept of the polarity of a GRM form is generalised to the polarity matrix of a MIGRM form. A tabular pattern-matching method is presented for the calculation of a MIGRM form. The MIGRM transform has been implemented for further investigations of such forms and their comparison with other circuit realisations.

Reed-Muller canonical forms with mixed polarity and their manipulations

The set of 3/sup n/ consistent mixed-polarity Reed-Muller canonical forms of an n-variable switching function is described and the means whereby each form may be derived by a transform on the zero-polarity form is investigated. The computational cost of deducing the optimum polarity expansion is evaluated for various strategies. A ternary map-based method is introduced which enables this search and other operations to be performed in a compact and efficient manner.

Efficient algorithm for canonical Reed-Muller expansions of Boolean functions

The paper presents a new method for computing all 2n canonical Reed-Muller forms (RMC forms) of a Boolean function. The method constructs the coefficients directly and no matrix-multiplication is needed. It is also usable for incompletely specified functions and for calculating a single RMC form. The method exhibits a high degree of parallelism.

Systematic method of searching for minimum generalised Reed-Muller forms using a variable state function

A binary function of the state of any variable is introduced to calculate the number of terms obtained by a generalised Reed-Muller expansion of a sum of minterms. A systematic method of searching for the minimum Reed-Muller form is thus available.

Synthesis procedures for switching circuits represented Reed-Muller form over a finite field

The synthesis of economical multilevel circuits for binary and multiple-valued switching circuits is described. The mode of function description is that provided by the algebra of finite fields and this leads to a highly modular form of circuit representation. A universal-logic tree composed of GF(q) adders and multipliers is used as a template on which to construct specific multilevel circuits. The paper describes methods for assigning the input variables to the network so as to reduce the complexity of the general tree by removing the redundant circuit elements. The resulting networks are invariably less costly than those from the direct synthesis of two-level sum-of-products expressions and they use only a restricted set of circuit elements.