Reduction In Switching Energy Research Articles

An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme

An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of 103.5μW, leading to a Figure of Merit of 8.93 fJ/Conversion-step.

Impact of Bottom Electrode in HfO2-Based Rram Devices on Switching Characteristics

Resistive random-access memory (RRAM) devices with hydrogen plasma treated HfO2 have shown low power switching (1) and good conductance quantization with programing pulsed operation (2) that qualify them to be used for in-memory computing. Engineering the distribution of defects or oxygen vacancies near the top and bottom electrodes has a significant impact on reducing the switching power and improving the multi-level cell (MLC) characteristics of the device. A graded distribution with higher concentration of oxygen vacancies closer to the top electrode (TE) due to hydrogen plasma treatment and lower concentration near the bottom electrode (BE) reduces switching energy (power) (1). However, the impact of the bottom electrode is not well understood. In this work we investigated three RRAM stacks as shown in Figure 1 that have the same top electrode metal (50nm PVD TiN/5nm ALD TiN) and dielectric (HfO2 with hydrogen plasma treatment at the mid-point) but with different BE for each stack: TiN (device A (control)), TiN plus Mo with thermal anneal (device B), and TiN plus Mo with plasma nitridation (device C). Choosing a more inert metal as the BE provides a lower oxygen vacancy concentration at the interface between the BE and the dielectric (3) which in turn reduces the switching power as noted with device C (TiN plus Mo with plasma nitridation) which switches at a minimum compliance current (Icc) of 500pA. It is possible that the presence of nitrogen prevents the increase in oxygen vacancy concentration near the BE. On the other hand, a higher concentration of oxygen vacancies at the BE and the dielectric interface leads to a larger magnitude of band bending and increases the height of Schottky barrier. This possibly leads to an increase in the switching power in device A and device B as compared to device C (3-4). Note that device A (TiN) switched at Icc=30µA and device B (TiN plus Mo with thermal anneal) switched at Icc=8µA, which is superior compared to device A in switching power. This suggests that the alloy of TiN with Mo is reducing the oxygen vacancies near the BE. To study the MLC characteristics of the devices, we performed a train of 36 RESET pulses with fixed amplitude Vp= -1V and pulse width starting at 4µs and increasing by 20µs every 3 pulses, while we applied Vr=0.1V and tr=10µs after each pulse to measure the conductance. Figure 2 shows that device B (TiN plus Mo with thermal anneal) has good MLC with no overlap between the states while device A shows unstable MLC behavior due to time constant variation. Figure 3a shows the results of device C for the same RESET pulse train that was applied to devices A and B. Since device C switches at very low current and voltage, the conductance quantization was unstable after 15 pulses due to overstress of the conductive filament. Figure 3b shows the results after selecting the proper pulse set Vp= -0.5V and pulse width starting at tp=100ns and increasing by 100ns every 3 pulses, while we applied Vr=0.05V and tr=100ns after each pulse, resulting in a better conductance quantization compared to the previous setup. Appropriate engineering of the BE and managing of the oxygen vacancy distribution by hydrogen plasma treatment can significantly reduce the switching power.

Advanced interfacial phase change material: Structurally confined and interfacially extended superlattice

Interfacial Phase Change Memory (iPCM) retrench unnecessary power consumption due to wasted heat generated during phase change by reducing unnecessary entropic loss. In this study, an advanced iPCM (GeTe/Ti-Sb2Te3 Superlattice) is synthesized by doping Ti into Sb2Te3. Structural analysis and density functional theory (DFT) calculations confirm that bonding distortion and structurally well-confined layers contribute to improve phase change properties in iPCM. Ti-Sb2Te3 acts as an effective thermal barrier to localize the generated heat inside active region, which leads to reduction of switching energy. Since Ge-Te bonds adjacent to short and strong Ti-Te bonds are more elongated than the bonds near Sb-Te, it is easier for Ge atoms to break the bond with Te due to strengthened Peierls distortions (Rlong/Rshort) during phase change process. Properties of advanced iPCM (cycling endurance, write speed/energy) exceed previous records. Moreover, well-confined multi-level states are obtained with advanced iPCM, showing potential as a neuromorphic memory. Our work paves the way for designing superlattice based PCM by controlling confinement layers.

A 99.93% energy-efficient switching scheme for SAR ADC without switching energy in the first three MSBs

This paper presents a highly energy-efficient and area-saving switching scheme for successive approximation register (SAR) analog-to-digital converters. By switching the voltages of all the bottom plates of capacitors in one side simultaneously by the same voltage level, the proposed switching scheme consumes no switching energy in the first three comparison cycles during which most of the switching energy is consumed. This switching method achieves a 99.93% reduction in switching energy and 97.6% less number of total capacitors over the conventional SAR switching scheme. In addition, the root mean square (RMS) of the maximum differential nonlinearity (DNL) and the maximum integral nonlinearity (INL) are 0.318 LSB and 0.32 LSB, respectively.

Process Optimization to Reduce Power in HfO2-Based Rram Devices for in-Memory Computing

Recently, HfO2-based resistive random-access memory (RRAM) devices have shown promise as candidates for in-memory computing applications. By engineering the distribution of defects or oxygen vacancies, the switching dielectric can potentially enable low power switching and multi-conductance levels. A higher concentration of oxygen vacancies closer to the top electrode a two-terminal RRAM device with a HfO2/Al2O3 bilayer structure reduces switching energy (1). Introducing excess oxygen vacancies near the top electrode through a hydrogen plasma treatment with a Ru as top electrode reduces the switching power of the device (2).In this work we study the pulsed SET operation of different HfO2-based RRAM devices for their possible uses as multi-level cells. We have compared two different RRAM devices with HfO2-based dielectrics. Device-A is prepared with hydrogen plasma treatment at mid-point of HfO2 deposition (10nm Ti/50nmTiN/3nm HfO2(plasma treatment) 3nm HfO2/5nm Ru/5nm ALD TiN/ 50nm PVD TiN). Whereas Device-B constitutes a HfO2/Al2O3 bilayer structure (10nm Ti/50nmTiN/7nm HfO2/1nm Al2O3/5nm Ru/5nm ALD TiN/50nm PVD TiN). Both the devices have Ru as the top metal.Fig. 1 and Fig. 2 show the conductance modulation obtained by applying successive pulse sequences (80 pulses) with increasing the pulse width tp (from 4 \U0001d707s to 10 ms) every 20 pulses where the pulse height, Vp, remained fixed at 2V during the experiment. A read pulse with voltage Vr=0.1V and pulse width tr=1ms is applied immediately after each pulse. The forming compliance current in Device-A is seven time lower than Device-B. Both devices clearly show promising behavior of multi-level conductance. Figure 1

A low‐power and area‐efficient ultrasound receiver using beamforming successive approximation register analog‐to‐digital converter with capacitive digital‐to‐analog converter combined delay cell structure for 3‐D imaging systems

The authors present a low-power area-efficient subarray beamforming receiver (RX) structure for a miniaturized 3-D ultrasound imaging system. Given that the delay-and-sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog-to-digital converter (ADC) shares its capacitive digital-to-analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power-hungry ADC buffers. Furthermore, the dual reference 10-bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.

Ultra-low-energy programmable non-volatile silicon photonics based on phase-change materials with graphene heaters.

Silicon photonics is evolving from laboratory research to real-world applications with the potential to transform many technologies, including optical neural networks and quantum information processing. A key element for these applications is a reconfigurable switch operating at ultra-low programming energy-a challenging proposition for traditional thermo-optic or free carrier switches. Recent advances in non-volatile programmable silicon photonics based on phase-change materials (PCMs) provide an attractive solution to energy-efficient photonic switches with zero static power, but the programming energy density remains high (hundreds of attojoules per cubic nanometre). Here we demonstrate a non-volatile electrically reconfigurable silicon photonic platform leveraging a monolayer graphene heater with high energy efficiency and endurance. In particular, we show a broadband switch based on the technologically mature PCM Ge2Sb2Te5 and a phase shifter employing the emerging low-loss PCM Sb2Se3. The graphene-assisted photonic switches exhibited an endurance of over 1,000 cycles and a programming energy density of 8.7 ± 1.4 aJ nm-3, that is, within an order of magnitude of the PCM thermodynamic switching energy limit (~1.2 aJ nm-3) and at least a 20-fold reduction in switching energy compared with the state of the art. Our work shows that graphene is a reliable and energy-efficient heater compatible with dielectric platforms, including Si3N4, for technologically relevant non-volatile programmable silicon photonics.

A Low Power Fully Differential Level-Crossing ADC With Low Power Charge Redistribution Input for Biomedical Applications

A low-power fully differential level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. Different from conventional ADCs based on the uniform sampling rate, LC-ADC generates fewer samples for biomedical signals and leads to less power consumption in the following blocks. In this design, the power consumption of n-bit DAC and digital parts is reduced significantly with respect to the conventional LC-ADCs. The proposed method uses a charge redistribution block (CRB) instead of the n-bit DAC, which leads to a large reduction in average switching energy. Besides energy-saving, the proposed switching scheme also reduces the complexity of the controlling logic circuit, providing reduced complexity and low power consumption. Another advantage of the proposed LC-ADC is its fully differential structure. As a result, SNDR is improved by decreasing the levels of even harmonics. The proposed LC-ADC is designed in 0.18 um CMOS technology. Post-layout simulation results show an effective number of bits (ENOB) of up to 6.8 bits with about 97-188 nW power consumption under 0.8 V supply voltage and input signal bandwidth from 1 Hz to 4 kHz. The ADC occupies a silicon area of only 60×65 μm2.

MSB-split VCM-based charge recovery symmetrical switching with set-and-down asymmetrical switching method for dual-capacitive arrays SAR ADC

With the advanced development of CMOS manufacturing process, the capacitive-array in the successive approximation register analog-to-digital converters (SAR ADCs) has become the dominant source of energy consumption and silicon area. This requires an immediate attention to design a more energy-efficient capacitive switching method while maintaining excellent linearity and noise rejection. A hybrid switching method is proposed for the SAR ADC with dual-capacitive arrays architecture, which consists of MSB-split $$V_{CM}$$ -based charge recovery symmetrical switching and set-and-down asymmetrical switching methods for the coarse and fine resolution conversions, respectively. As a result, it has achieved 99.53% switching energy reduction and 73.44% area reduction compared to the conventional switching method.

A high energy-efficiency and low-area switching scheme for SAR ADCs

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC switches is lower than the conventional and some other methods, which avoids further complicating the logic circuit as well as increasing wiring and area. Moreover, only one voltage source is used as a reference voltage, which makes us needless to have an extra voltage source that must be very accurate.

Techniques to Reduce Switching and Leakage Energy in Unrolled Block Ciphers

Energy consumption of block ciphers is critical in resource constrained devices. Unrolling has been explored in literature as a technique to increase efficiency by eliminating energy spent in loop control elements such as registers and multiplexers. However these savings are minimal and are offset by the increase in glitching power that comes with unrolling. We propose an efficient latch-based glitch filter for unrolled designs that reduces energy per encryption by an order of magnitude over a straightforward implementation, and by 28-45 percent over the best existing glitch filtering schemes. We explore the optimal number of glitch filters that should be used in order to minimize total energy, and provide estimates of the area cost. Partially unrolled designs also benefit from using our scheme with energies competitive to fully serialized implementations. Power gating to reduce leakage power and reuse of computed key enable unrolled designs to be more efficient than serialized ones without compromising latency advantages. We demonstrate our approach on the SIMON-128 and AES-128 block ciphers.

Online parameter tuning of the flow classification method in the energy-efficient data center network “HOLST”

An online parameter-tuning method for the energy-efficient data center network (DCN) named HOLST (high-speed optical layer 1 switch system for time-slot-switching-based optical data center networks) is proposed. HOLST comprises an optical circuit switching network, optical slot switching network, and electrical packet switching network for the spine layer. It requires flows to be assigned to optimal switches to achieve high power savings. In this study, first we experimentally confirm that the change in the DCN characteristics in the short term of actual data center traffic downgrades the accuracy of flow classification. Subsequently, we propose a procedure for reconfiguring a flow classification function and a method for online parameter tuning for this function. Finally, the accuracy of the flow classification method using the proposed tuning and estimated switching energy consumption in the spine layer are evaluated. The proposed online parameter-tuning function increases the accuracy of flow classification and reduces switching energy consumption relative to the conventional flow classification function.

Energy efficient switching scheme based on MSB-split structure for SAR ADC

An energy efficient switching algorithm for low voltage SAR ADC is presented. By the combination of MSB-split and merge-and-split techniques, this switching method consumes negative energy in the MSB bit switching, which contributes to 99.76% switching energy reduction comparing to the conventional solution. Furthermore, without requiring for a third reference voltage makes it especially suitable for ADC design under low supply voltage. Additionally, LSB-down technique is employed, which reduces the total capacitor DAC area by 50%. The simulated differential-nonlinearity and integrated-nonlinearity are 0.27 and 0.21LSB, respectively, demonstrating that the proposed switching algorithm has a relatively good linearity.

(Invited) Suspended Graphene Monolayers for Low Voltage Switches

Since the dawn of electronics, the energy efficiency of computation has been a driving force for change, motivating disruptive technology advances from vacuum tubes to discrete semiconductor devices to ultra-large-scale integrated circuits [1]. Modern society’s reliance on the electronics behind digital hardware will continue to grow, with accelerating demand for computing power driven by advances such as artificial intelligence and machine learning. Improving energy efficiency while maintaining functional density of integrated electronics is widely acknowledged as the most important technological challenge for electronics in the 21st century [2-7]. The thermodynamic limit to irreversible computation at room temperature is ~ kBT ln 2 = 18 meV per bit of information erasure, corresponding roughly to a limit of 18 meV per logical operation in a transistor based logic. By contrast, the energy consumed in a modern integrated circuit per logical operation is of the order 104-105 kBT ~ 0.6-6 keV, as a result of the energy consumed to transmit information between transistors by charging interconnect capacitance up to the operating voltage of the transistor.The mean energy consumed per transistor per clock-cycle in a digital circuit [7]: E = CV 2 [α + (I off/I on)β] where C ~ 10 fF is the average load capacitance dominated by interconnects, V ~ 1 V is the transistor operating voltage, α ~ 1% is the fraction of transistors that switch per clock-cycle, I on/I off ~ 106 is the on/off current ratio of the transistor, and β ~ 100-1000 is the ratio of clock period (~1 ns) to the intrinsic transistor switching delay time (~1 ps). Improving the energy efficiency of a transistor circuit can thus be achieved by reducing operating voltage V while maintaining the on/off current ratio I on/I off . Transistors are limited by the sub-threshold swing of current versus voltage, S = ∂VG/∂log(ID), which is typically subject to the thermionic limit ~(kT/e)×ln10 ≈ 60 mV/decade, although tunneling transistors can modestly surpass this limit but at the cost of a significant loss of current drive [2-7]. Switches with improved sub-threshold swing S are known as steep-slope devices.We propose a new approach to energy efficient electronics, consisting of nanomechanical suspended graphene steep-slope switches. The mechanical properties of graphene are ideally suited to nanoelectromechanical systems (NEMS). Graphene’s Young’s modulus Y ~ 1 TPa [8] is higher than any other material, but the atomic thinness of graphene t = 0.34 nm results in an elastic modulus for deflection of Ee = Et/(1−υ) ~ 400 N/m for an unstrained membrane. Graphene monolayers are the most flexible membranes known, and thus require less voltage than any other membrane for electrostatically actuated deflection. Adopting graphene as a membrane material can in principle achieve a ~10 fold reduction in operating voltage to ~0.1 V and thus a ~100 fold reduction in switching energy, as a direct result of suspended monolayer graphene’s uniquely low deflection modulus [9]. Experimental realization of such low-voltage operation poses challenges in device fabrication and scaling.

A 99.43% Energy Saving Switching Scheme with Asymmetric Binary Search Algorithm for SAR ADCs

In this paper, a low-energy switching scheme based on the asymmetric binary search algorithm for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. To reduce switching energy and area, the proposed scheme uses the single-side switching method and the least significant bit (LSB) capacitor is split into two one-half unit capacitors. Using the series capacitance scheme, the capacitance mismatch caused by process deviation is effectively improved. Compared with the conventional switching method, the switching energy of this scheme is decreased by 99.43% and the area is saved by 87.2%. MATLAB simulation results show that this scheme also has a low nonlinearity that the maximum differential nonlinearity is only 0.37 LSB and the maximum integral nonlinearity is only 0.43 LSB.

An energy-efficient RAM cell based on novel majority gate in QCA technology

The limitations of the Complementary Metal–Oxide–Semiconductor (CMOS) technology such as the dissipated power, hard lithography, and short channel effects, led the researchers to look for an alternative technology. The unique properties of the QCA technology such as low dissipated power, speed, and the small feature size were the reason for considering it as a CMOS alternative in this work. In this paper, a new layout for five input single layer majority gate is proposed. The proposed majority gate is used in order to carry out new low power RAM cell with the ability to set the output or to reset it. Designing a cost efficient memory cell is an important issue because it is a brick unit for the whole RAM that considers the most essential component in the digital system. The proposed RAM cell shows improvement around 7% in terms of cost function and a noticeable reduction in switching energy. The QCADesigner tool is used in this work for circuit design and verification while the QCAPro tool is used for power analysis.

Large voltage control of magnetic anisotropy in CoFeB/MgO/OX structures at room temperature

Voltage control of magnetic anisotropy (VCMA) provides an energy-efficient approach to manipulate spintronic devices. Currently, VCMA only shows a weak effect in magnetic tunnel junctions (MTJs) composed of CoFeB/MgO/CoFeB that are the core structure of spintronic memories and logic devices. Multiple approaches have been proposed and studied by researchers to increase the VCMA effect. Here, we demonstrate a large VCMA effect in the CoFeB/MgO/SiO2 double-oxide structure, which can be potentially modified to be compatible with the MTJ cell. The VCMA coefficient as high as 174 fJ/Vm is achieved in this structure at room temperature, with its magnitude comparable to the reported ion-driven VCMA with a high ion-conductive oxide at an elevated temperature. Theoretical analysis indicates that the large VCMA is a magnetoionic effect, which is dominated by ion migration and can be explained by a nanograin cluster model. This double-oxide structure is promising to be extended to an MTJ structure to reduce switching energy in spintronic devices.

Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin–Orbit Devices Toward 100-mV Logic

The supply voltage scaling has become increasingly challenging in the advanced CMOS technology due to the threshold voltage requirement for transistor OFF leakage, limiting the system energy efficiency. Spintronic logic utilizes the physical quantity of magnetization or spin as a computation variable, offering new design paradigms in terms of ultralow voltage operation and nonvolatility, but suffering from switching inefficiency of the charge-to-spin conversion. The magnetoelectric spin–orbit (MESO) device has been proposed as a new alternative logic device candidate to solve these issues by magnetoelectric transduction using a novel multiferroic oxide [both ferroelectric (FE) and antiferromagnetic], a ferromagnet and a spin injection layer. It enables a path toward 10–100 $\times $ switching energy reduction compared to CMOS inverter in 2018 node, due to the device and material innovations of a novel switching mechanism. In this paper, in order to build a MESO logic family for new circuit and architecture exploration, we propose for the first time the fundamental building blocks such as MESO sequential and combinatorial circuits for the synchronous logic operation. We employ a transistor sharing and a novel multiphase clocking scheme to address the circuit design issues such as clock control, directionality of state propagation, and power gating and enable the design exploration for MESO digital logic. Based on the proposed circuit techniques, we demonstrate these MESO logic functions operating at a supply voltage of 100 mV and a clock period of 1.2 ns with 320-ac FE polarization through the circuit simulations.

An efficient-energy switching scheme with 99.57% reduction in switching energy for SAR ADC

An efficient-energy switching scheme for a successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed switching scheme combines a new switching method and the spilt capacitor technique. The new switching method consumes no energy in the first three comparison cycles and introduces negative energy (Tong and Zhang in Electron Lett 51(14):1052–1054, 2015; Osipov and Paul in Two advanced energy-back SAR ADC architectures with 99.21 and 99.37% reduction in switching energy, Kluwer Academic Publishers, Dordrecht, 2016) in the following comparisons. The proposed switching scheme achieves 99.57% less switching energy and 75% less area over the conventional architecture, besides the proposed switching scheme achieves high linearity at the same time which DNL is just 0.119 LSB, INL is 0.119LSB.

In situ observations of the reversible vacancy ordering process in van der Waals-bonded Ge-Sb-Te thin films and GeTe-Sb2Te3 superlattices.

Chalcogenide-based thin films are employed in data storage and memory technology whereas van der Waals-bonded layered chalcogenide heterostructures are considered to be a main contender for memory devices with low power consumption. The reduction of switching energy is due to the lowering of entropic losses governed by the restricted motion of atoms in one dimension within the crystalline states. The investigations of switching mechanisms in such superlattices have recently attracted much attention and the proposed models are still under debate. This is partially due to the lack of direct observation of atomic scale processes, which might occur in these chalcogenide systems. This work reports direct, nanoscale observations of the order-disorder processes in van der Waals bonded Ge-Sb-Te thin films and GeTe-Sb2Te3-based superlattices using in situ experiments inside an aberration-corrected transmission electron microscope. The findings reveal a reversible self-assembled reconfiguration of the structural order in these materials. This process is associated with the ordering of randomly distributed vacancies within the studied materials into ordered vacancy layers and with readjustment of the lattice plane distances within the newly formed layered structures, indicating the high flexibility of these layered chalcogenide-based systems. Thus, the ordering process results in the formation of vacancy-bonded building blocks intercalated within van der Waals-bonded units. Moreover, vacancy-bonded building blocks can be reconfigured to the initial structure under the influence of an electron beam, while in situ exposure of the recovered layers to a targeted electron beam leads to the reverse process. Overall, the outcomes provide new insights into local structure and switching mechanism in chalcogenide superlattices.