Reduction Of Self-heating Effect Research Articles

Retracted: Improvement and Reduction of Self-Heating Effect in AlGaN/GaN HEMT Devices

Retracted: Improvement and Reduction of Self-Heating Effect in AlGaN/GaN HEMT Devices

Improvement and Reduction of Self-Heating Effect in AlGaN/GaN HEMT Devices

GaN is one of the third-generation broadband semiconductor materials developed rapidly in recent years, and Algan/GanHEMT has a broad application prospect in the fields of high temperature, high power, high frequency and radiation resistance, etc. In recent years, gallium nitride based high electron mobility transistors have been widely used in emerging industries, such as 5G technology, new energy vehicles, unmanned aircraft and other fields, due to their high power and high voltage resistance. However, due to the high power density of HEMT devices, the self-heating effect will lead to a significant increase in the junction temperature of the device, which will seriously affect the performance, reliability, and lifetime of the device. In this paper, the temperature characteristics of GaN high electron mobility transistors (GaN HEMTs) are studied, and the effect of self-heating effect on GaN HEMT devices is analyzed. In order to reduce the device temperature and improve the reliability of the device, a new device structure is proposed in this paper. The new structure replaces the conventional silicon and Si3N4 with highly thermally conductive diamond and SiC as the substrate and passivation layer of the device, which facilitates the heat dissipation from the substrate and passivation layer. Also, the new structure employs a hybrid barrier layer and field plate. Simulation results show that the new structure has about 30% lower temperature peak, 47% higher output current, 28% higher transconductivity, and up to 18.22% higher current collapse rate compared to the conventional structure.

Reduction in Self-Heating Effect of SOI MOSFETs by Three Vertical 4H-SiC Layers in the BOX

In this paper a novel structure is proposed for silicon on insulator MOSFETs which improves DC and RF characteristics by three vertical layers of 4H-SiC. Vertical layers are in parallel and extended from silicon drift region toward the substrate through oxide region as heating passageways. These additional layers absorb the heat of active region and transfer to the substrate area. Thus, large value of temperature variation arising from high gate and drain biasing in SOI devices is reduced by applying the proposed structure. It reduced from ~690 K to ~353 K at VG = 10 V. The negative differential resistance is diminished and carriers mobility improved which result in higher and more stable saturation current in comparison with conventional structure. Also, the resultant device has lower delay time. Gate capacitances are approximately equal to the conventional structure but its higher transconductance results in more than 3-times higher cut-off frequency and about 75% improvement in maximum oscillation frequency, at VG = 10 V and VD = 3.5 V. Widespread simulations and comparisons demonstrate that this structure can be considered in high power and RF applications.

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.

Reduction of self-heating effect in (Ga)ZnO thin film transistor

ABSTRACTRF magnetron sputtering technique was employed to fabricate gallium zinc oxide ((Ga)ZnO) semiconductor thin film transistor (TFT) at 100°C. X-ray diffraction and Scanning electron microscopy were used to identify the structure and morphology of (Ga)ZnO layer. Self-heating effect was very much reduced when compared with output characteristics of a TFT fabricated using undoped zinc oxide. The low deposition and processing temperatures make (Ga)ZnO-TFTs very promising for the flexible electronics.

RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

In this work three different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard HR-SOI and two types of trap-rich high resistivity HR-SOI substrates named enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) provided by SOITEC are studied and compared. The DC and RF performances of these wafers are compared by means of passive and active devices such as coplanar waveguide (CPW) lines, crosstalk- and noise injection-structures as well as partially-depleted (PD) SOI MOSFETs. It is demonstrated that by employing enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) compared to HR-SOI wafer, a reduction of 24dB is measured on both generations of trap-rich HR-SOI for 2nd harmonics. Furthermore, it is shown that in eSI HR-SOI, digital substrate noise is effectively reduced compared with HR-SOI. Purely capacitive behavior of eSI HR-SOI is demonstrated by crosstalk structure. Reduction of self-heating effect in the trap-rich HR-SOI with thinner BOX is finally studied.

Self-Heating Characterization and Extraction Method for Thermal Resistance and Capacitance in HV MOSFETs

This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 μs and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.

Reduction of self-heating effect on SOIM devices

The silicon-on-insulator (SOI) power devices have an inherent self-heating effect, which limits their operation at high current levels. This is a consequence of the very low thermal conductivity of the thick buried oxide layer. A novel solution to reduce the self-heating effect is proposed in this paper, based on silicon-over-insulator-multilayer (SOIM) emerging technology. A significant reduction of the insulator layer thermal resistance is achieved while keeping constant the electrical behaviour of integrated power devices in comparison to the conventional SOI counterparts. The effectiveness of the proposed solution has been corroborated with numerical simulations. Moreover, no additional steps in fabrication processes are required with regard to the conventional SOI technology.