Reduction Of Parasitic Capacitance Research Articles

Realization of an ultra-scaled novel Ga2O3 FinFET for sub-terahertz applications

This study involves in-depth simulations focused on gate-electrode and channel-doping engineering in ultra-scaled Ga2O3 FinFETs. Silvaco TCAD software was employed as a simulation tool to explore the suitability of these designs for sub-terahertz applications. The focus of the present study is the simultaneous enhancement in current drivability as well as the reduction in parasitic capacitances without any trade-off, to achieve superior performance for sub-terahertz applications. Along with the analog characteristics of the proposed device, various critical high-frequency figures of merit have also been evaluated. Furthermore, scattering parameters have also been studied with variations in frequency to gain insights into the performance of the proposed device at high frequencies. In addition, a thorough comparison of the proposed device with the conventional device has been carried out. It has been demonstrated that the proposed device is an excellent contender for ultra-high-frequency applications with remarkable high-frequency figures of merit.

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

In this manuscript, we present a negative capacitance TFET with extended back gate-drain overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance. TCAD-based simulations reveal that DEBG-NC-TFET offers a significant enhancement in ION and SS because of a Ferroelectric (FE) layer introduced into the gate-oxide layer of the device, without deteriorating its other parameters. This work examines the effects of various factors of NC including coercive electric field (Ec) and remnant polarization (Pr) on memory window (MW) to improve the read margin of the device. With an optimum thickness of FE layer, DEBG-NC-TFET is found to offer a huge reduction in the ambipolar current (Iamb) with unchanged IOFF and ION as compared with those of symmetric gate-drain overlap (DSYG) and conventional DG-NC-TFET. The vertical component of the field induced inside the drain region increases the layer of depleted charge at the channel-drain interface, which enhances the barrier width and restricts the charge carriers from tunneling at the ambipolar state. Furthermore, incorporating back gate-drain overlap into DG-NC-TFET resolves the trade-off between parasitic capacitances and ambipolarity as overall gate capacitance is found to be reduced for DEBG-NC-TFET. Apart from reduction in gate parasitic capacitance, various HF parameters like gain–bandwidth product (GBWP) and cutoff-frequency (fT) are also found to be improved for DEBG-NC-TFET as compared to DSYG-NC-TFET. Finally, a resistive load inverter analysis shows that various parameters like propagation delay, full swing, and peak over- and undershoots are significantly improved when only the back gate overlaps the drain region of DG-NC-TFET.

Improved breakdown voltage mechanism in AlGaN/GaN HEMT for RF/Microwave applications: Design and physical insights of dual field plate

This work investigated and proposed the source–gate dual field plate (SG-FP) AlGaN/GaN HEMT for different gate-to-drain drift distances with a fixed gate length of 0.25 μm using ATLAS-TCAD. The increment in the GaN buffer thickness and gate-to-drain drift distance with the variation in the field plate length improves the device performance and breakdown voltages by maintaining the impact ionization mechanism. The breakdown voltage behavior, physical insights of electric field contour, impact generation rate, and potential profile intricacies of source field plate (S-FP), gate field plate (G-FP), and dual field plate (SG-FP) are illustrated. The proposed source–gate dual field plate (SG-FP) with the SiN passivation interfacial layer, SiO2, thicker GaN buffer, and extended gate-to-source drift region is best suited for optimal performance in high breakdown voltage, with optimum cut-off frequency and low gate-leakage current. The proposed dual field plate AlGaN/GaN device with the source field plate (LS-FP = 4 μm), gate field plate (LG-FP = 2 μm), the AlGaN buffer thickness of 3.697 μm, and gate-to-drain drift distance of 8 μm show the highest breakdown voltage of 562 V with the optimum frequency of 8.861 GHz. Finally, the AC/DC characteristics of the optimized dual field plate (SG-FP) are demonstrated. We observed that the source–gate dual field plate (SG-FP) device shows a 6.70% and 4.09% improvement in breakdown voltage compared to individual source field plate (S-FP) and gate field plate (G-FP) designs, respectively. This work shows that the proposed dual field plate device is used in power switching, high-power, and RF/Microwave applications due to its superior breakdown voltage performance, reduction in parasitic capacitances, and optimal cut-off frequency.

Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors.

The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). The gate length (LG) depends on the TIS. Thus, the DC/AC performance is significantly affected by ΔTIS. Because the effects of ΔTIS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔTIS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (trpbt) should be considered with ΔTIS because the gate controllability over trpbt is significantly dependent on ΔTIS,B. If the S/D recess depth (TSD) variation cannot be completely eliminated, reducing ΔTIS,B is crucial for suppressing the effects of trpbt. It is noteworthy that reducing ΔTIS,B is the most important factor when the TSD variation occurs, whereas reducing ΔTIS,T and ΔTIS,M is crucial in the absence of TSD variation to minimize the DC performance variation. As the TIS increases, the gate capacitance (Cgg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of Cgg to each ΔTIS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since TSD of 5 nm increases the off-state current (Ioff) sensitivity to ΔTIS,B by a factor of 22.5 in NFETs, the ΔTIS,B below 1 nm is essential for further scaling and yield enhancement.

Design and Investigation of F-shaped Tunnel FET with Enhanced Analog/RF Parameters

In this manuscript, a novel physically doped single gate F-shaped tunnel FET is simulated and optimized. The designed configuration is well optimized and analyzed for different source thickness, source length, drain length with different lateral tunneling lengths between the source edge and gate dielectric. Also, we optimized some stand-points like threshold voltage, ION to IOFF current ratio, ambipolar conduction range, sub-threshold swing and various capacitance to rectify the analog/RF performance of single gate F-shaped TFET. Regarding this, we concurrently optimize the lateral tunneling length between source and gate with optimization of source thickness. The variation in lateral tunneling length, the potential and strength of electric field at fixed Vgs voltage is varied which leads to effective change in the ON-current, average sub-threshold swing, and turn ON-voltage. Another side, as well as the source thickness vary, the electric field variation takes place near the edge of source, which leads to variation in the ON-current and ON-voltage. The performance parameters of single gate F-TFET is compared with single gate L-TFET, which is the incentive of this submitted work. The optimized single gate F-TFET have 0.30 V turn ON-voltage with 7.4 mV/decade average sub-threshold swing and high Ion/Ioff ratio approx 1013. Besides, a significant reduction in parasitic capacitance is beneficial to enhanced RF performance with better controllability on channel.

III–V nanowire backward diodes with high sensitivity above 1 MV W−1 for low-power microwave energy harvesting

Improved sensitivity of over 1 MV W−1, which exceeds that of conventional well-designed Schottky barrier diodes, was achieved in p-GaAs0.4Sb0.6/n-InAs nanowire backward diodes (NW BWDs) for low-power microwave energy harvesting at 2.4 GHz under zero-bias. The antimony composition in the GaAsSb NWs was increased to 0.6 to form proper interband tunneling of the BWDs. A linear detected characteristic of detection was obtained even when microwave input power was less than 1 μW. Furthermore, the reduction of parasitic capacitance due to the adoption of a reduced pad area helped in the improvement of the sensitivity of the NW BWDs. A large dynamic range in detection of low-power microwaves was obtained through the employment of an extended anode structure. Device simulations clarified that carrier depletion in GaAsSb NWs was the main cause of increased forward breakdown voltage, which resulted in the large dynamic range exhibited by the NW BWDs.

Thermal and Electrical Performance in High-Voltage Power Modules With Nonmetallic Additively Manufactured Impingement Coolers

As high voltage, wide-band-gap power modules increase in power density with high switching frequency, they create localized hot spots and harmful electromagnetic interference (EMI). If not treated properly, these issues can drastically reduce the reliability of the devices. In this article, we propose a solution to address both of these challenges created by power module building blocks which are designed for use in a hybrid-electric aircraft traction inverter. Additive manufacturing is used to fabricate a nonmetallic jet impingement device to decrease power module temperatures. Moreover, the nonmetallic structure limits the accentuation of EMI created by the module operating at high switching frequencies. Conjugate heat transfer simulations are used to predict the thermal performance of the cooler. In this article, a reduction of maximum die temperatures is observed, along with an increase in temperature uniformity throughout the base plate. Experimental results show a minimum thermal resistance of 0.1 K/W and an average heat transfer coefficient up to 3600 W/m2.K at peak operation. Finally, EMI tests are performed to show a two orders of magnitude reduction of parasitic capacitance using the nonmetallic cooler compared with a metallic heat sink. This directly leads to a 25 dB decrease in the common mode noise.

Fabrication of 2D Capacitive Micromachined Ultrasonic Transducer (CMUT) Arrays on Insulating Substrates With Through-Wafer Interconnects Using Sacrificial Release Process

A critical component in a three-dimensional (3D) ultrasound imaging system is a two-dimensional (2D) transducer array. A 2D transducer array is also essential for the implementation of a compact form factor focused ultrasound system for therapeutic applications. Considering the difficulty associated with developing 2D transducer arrays using piezoelectric technology, capacitive micromachined ultrasonic transducer (CMUT) technology with the inherent advantages has emerged as a candidate to develop these devices. Previously, we demonstrated that 2D CMUT arrays can be fabricated with through-glass-via interconnects on borosilicate substrates using anodic bonding. In this paper, we present a fabrication process for implementing $16\times 16$ -element 2D CMUT arrays on an alkali-free glass substrate using the sacrificial release method. The vacuum-sealed $16\times 16$ -element 2D CMUT array is built on an SGW3 glass substrate with copper through-glass interconnects. The fabrication process developed for the 2D CMUT array is described in detail. Across the 256 elements of the 2D CMUT array, the mean resonant frequency is measured as 4.76 MHz with a standard deviation of 46.6 kHz. Also, the mean device capacitance across the array is measured as 1.17 pF with a standard deviation of 0.12 pF, and these results agree with the finite-element analysis. This study shows an alternative method to fabricate 2D CMUT arrays on glass substrates with metal interconnects, especially when the substrate is not suitable for anodic bonding. In addition to improved reliability and reduction in parasitic interconnect capacitance and resistance, this fabrication method benefits from the flexibility of developing 2D CMUT arrays on any type of insulating substrate, and still attain optimum uniformity in both yield and functionality of the fabricated devices. [2019-0246]

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable low-power and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1–5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C OV) and 3% reduction in ring oscillator effective capacitance (C EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V BD) and leakage current (I LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.

An EMI Suppression Method in SiC Half-bridge Power Module Design

Abstract This paper presents a 1200V/24A SiC half-bridge power module with ultra-low parasitic capacitance and inductance for low CM EMI. This module is improved from a stacked substrate hybrid packaging structure by optimizing the copper pattern. The parasitic capacitance reduction methods and the trade-off optimization for geometrical parameters are given. The parasitic capacitance of the output node is reduced by 70% compared to the original module. The parasitic capacitance and inductance of the proposed module are 6.8pF and 5.5nH respectively. The EMI simulation shows the proposed module can reduce CM EMI by about 9 dB, while the EMI test result shows a maximum of 6 dB reduction.

Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain

Structural modifications of 5-nm node nanosheet FETs (NSFETs) were quantitatively analyzed using fully calibrated TCAD. The NSFETs with crescent inner spacer improve the short-channel effects by increasing effective gate lengths but also increase the parasitic capacitances by greater outer fringing electric field. The NSFETs with a crescent inner spacer and slanted source/drain (S/D) increase the physical gate lengths of bottom NS channel, but the anisotropic over-etching of substrate regions induces punchthrough effect at the bottom transistor. Bottom isolation by depositing dielectrics prior to S/D formation is effective to eliminate the punchthrough effect as well as to attain shorter RC delay by better electrostatics and parasitic capacitance reduction. In addition, the isolated S/D NSFETs without punchthrough stopper decrease parasitic and gate capacitances further at the frequency greater than 600 MHz at which the inversion carriers are not formed at the bottom transistor. Thus, although the crescent inner spacer and slanted S/D structure are unintendedly formed under process, these modifications lead to the performance boosting and the process simplicity of the 5-nm node NSFETs.

Improved Performance of CMOS Terahertz Detectors by Reducing MOSFET Parasitic Capacitance

The parasitic circuit elements significantly affect rectification performance of metal-oxide-semiconductor field-effect transistor devices. In this paper, we develop a gate-source parasitic capacitance reduction technique by shifting the source lightly doped drain region and analyze the effectiveness on the improved performance of complementary metal-oxide-semiconductor (CMOS) terahertz (THz) detectors. It is experimentally found that for a 0.65-THz integrated CMOS detector, the maximum improvement of voltage responsivity and noise-equivalent power can be 155% and 70%, respectively, by suppressing the gate-source parasitic capacitance. The device simulation further quantitatively evaluates the gate-source parasitic capacitance under different gate-source overlap areas in the novel fabricated transistor structure. It reveals that a smaller gate-source overlap area can result in a lower gate-source parasitic capacitance, which is more favorable for reducing input THz signal leakage and therefore for increasing the THz responsivity. The works open a wide range of possibilities for the ease of design and fabrication of the high-performance THz detectors in standard CMOS technology.

Reduction of Parasitic Capacitance in Indium‐Gallium‐Zinc Oxide (a‐IGZO) Thin‐Film Transistors (TFTs) without Scarifying Drain Currents by Using Stripe‐Patterned Source/Drain Electrodes

AbstractA new device structure of oxide thin‐film transistor (TFT) having lower overlap capacitance without scarifying the drain current is proposed. This can be used for high‐speed circuits and high frame rate displays using the conventional TFT manufacturing process. The existence of spreading currents in amorphous indium‐gallium‐zinc oxide (a‐IGZO) TFTs with stripe‐patterned source/drain (S/D) electrodes is demonstrated. The device performances of the a‐IGZO TFTs with various widths of stripe‐patterned S/D electrodes and open spaces between them are compared. The drain currents of the a‐IGZO TFTs are almost same when the width of open space changes from 0 to 10 µm because of the existence of spreading currents. The overlap capacitance between gate and S/D of the a‐IGZO TFTs can be significantly reduced without scarifying drain currents by using stripe‐patterned S/D electrodes. The operation frequency of the ring oscillator made of the TFTs with stripe S/D electrodes with 10 µm open space width is 2.5 times that made of the conventional a‐IGZO TFTs. This spreading current concept can be widely used for the design of oxide TFT array with low RC (resistance capacitance product) delay for high‐speed circuits.

Integration scheme and 3D RC extractions of three-level supervia at 16 nm half-pitch

A multi-level via or ‘supervia’ (SV) is considered as a scaling booster for the next technology nodes, as it may lower routing resistance and parasitic capacitance as compared to a conventional dual damascene (DD) via. In this paper, we present a three-level SV integration scheme at 16 nm half-pitch along with its 3-D RC extraction. 3-D interconnect geometries are modeled by means of process emulations, performed by using Synopsys' Sentaurus Process Explorer. The resistance of DD vias is also extracted for comparing with SV for various metal and barrier-liner (M-BL) combinations. The R extraction is done based on a resistivity model, calibrated to imec hardware and integrated into Synopsys' Raphael™ tool [1]. Simulations of SV structures with novel M-BL combinations show up to 60% resistance reduction for the investigated interconnect configurations with respect to the DD Cu-TaNCo reference (R = 105 Ω) at a total BL thickness of 3 nm. Furthermore, an approach to compare SV vs DD via capacitance is proposed, which suggests ~16% reduction in parasitic capacitance of SV schemes compared to DD schemes.

Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance

With the last decade’s advances in sensor technologies and packaging techniques, there are several applications where the input capacitance and the leakage current of the integrated circuit (IC) front-end limit the readout accuracy of sensor systems. In particular, optimization of the electrostatic discharge (ESD) protection devices at the IC input could improve performance. Specifically, such optimization should involve reduction of parasitic capacitance and leakage current while maintaining the ESD robustness. Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS). The target fabrication process is 180 nm CMOS. Theoretical analysis of capacitance simulated with Cadence® in 180 nm CMOS design kit including layout extracted parasitics in combination with TCAD Sentaurus® simulations of current density and temperature is presented for selected ESD devices.

In-Plane-Gate GaN Transistors for High-Power RF Applications

In-plane-gate field-effect transistors (IPGFETs) offer an innovative device architecture in which the channel conductivity is modulated by the electric field from the 2D electron gas in the two adjacent in-plane gates, isolated by etched trenches. The planar nature of the gate electrode yields a huge reduction in parasitic gate capacitance, which can lead to much higher frequency. Moreover, the fabrication process for these devices is extremely simple and with inherently self-aligned gates. Here, we combine for the first time the promising architecture of IPGFETs with the exceptional properties of III-Nitrides, such as large carrier density and breakdown field, to reveal their enormous potential for high-power RF devices. AlGaN/GaN IPGFETs demonstrated large drain current up to 1.4 A/mm and transconductance up to 665 mS/mm, which are, respectively, nine times- and five times-larger than the best IPGFETs demonstrated in other semiconductors. These devices presented excellent gate control with ON–OFF ratio up to $10^{7}$ along with ultra-low capacitances down to 0.7 aF, leading to an estimated $f_{T}$ up to 0.89 THz. Extremely large breakdown voltage of 500 V was observed despite their nanoscale dimensions, with small leakage current below 1 nA up to 300 V. These results reveal that III-Nitride IPGFETs offer a promising pathway for future terahertz devices delivering large output powers.

A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET

This paper investigates for the first time the temperature dependence of the digital/analog parameters and RF figure of merits (FOMs) of a spacer based reconfigurable field-effect transistor (RFET) and compares the same with the existing RFET topology and other devices which depend on band-to-band tunneling (BTBT) for their on-current generation. It is observed that the output characteristics of the device are less sensitive to the temperature in the BTBT dominated on-state region as compared to the subthreshold one which is thermionic emission dependent. Having a better thermal stability over tunnel field effect transistor (TFET) and significantly lesser Vth roll-off, the proposed device portrays orders of magnitude reduction in parasitic gate capacitances and intrinsic delay as compared to gate-all-around (GAA) and hetero gate dielectric GAA TFET devices over the considered range of temperature, thus assuring higher switching speed for digital applications. Moreover, superior analog/RF performance is also exhibited by the device under consideration for all temperatures in contrast to SiGe, full silicon TFETs, and conventional RFET topology owing to higher BTBT dominance and better gate controllability. Apart from all of these performance gains, the device FOMs are found to be less sensitive to temperature variations making it more suitable for applications where temperature fluctuation is a major concern.

On-Chip Meander Line N-Well Resistor with Shielded Ground Conductor for Q-Factor Improvement

ABSTRACTThe on-chip meander line n-well resistor with a shielded ground conductor inserted parallel between the meander line on the silicon substrate is studied. The new design configuration concept with the shielded ground conductor improved the Q factor compared to those without the shielded ground conductor operating at high frequency. It was confirmed that the design configuration for the shielded ground conductor with a larger coverage area and increasing the number of parallel with the meander signal line was significant in improving the Q-factor performance operating at high frequency. Using this improvement method, the Q-factor value for proposed design meander line n-well structure with shielded ground conductor at 2 µm width in two T shapes has improved around 8% to 9% at 8, 9, and 10 GHz and reduced the parasitic mutual capacitance by 49.35 fF at 10 GHz when compared to the conventional structure of meander line n-well resistors. Shielded ground conductor technique is effective due to reduction of parasitic mutual capacitance. The resulting simulation of the return loss was improved using the shielded ground conductor method, but has poor of insertion loss, due to the skin effect. Overall, it has better performance compared to other designs because it has had significant improvement for Q factor to beyond 4 GHz and better return loss for all the range of frequency.

LLC Converters With Planar Transformers: Issues and Mitigation

The use of $LLC$ resonant converters has gained popularity in multiple applications that require high conversion efficiency and galvanic isolation. In particular, many applications like portable devices, flat TVs, and electric vehicle battery chargers require demanding slim-profile packaging and enforce the use of planar transformers (PTs) with low-height, low leakage inductance, excellent thermal characteristics, and manufacturing simplicity. The main challenge in successfully designing $LLC$ converters with PT resides in controlling high-parasitic capacitances produced by large overlapping layers in PT windings. When the parasitic capacitances are not controlled, they severely impair the converters’ performance and regulation, and limit the application of PTs in high-frequency $LLC$ converters. This paper characterizes the PT capacitance issue in detail and proposes mitigation strategies to improve the performance of $LLC$ converters with PTs. A systematic analysis is performed, and six PT winding layouts are introduced and benchmarked with a traditional design. As a result of the investigation, an optimized structure is obtained, which minimizes both the interwinding capacitance and ac resistance, while improving the regulation performance of $LLC$ converters. Experimental measurements are presented and show a significant reduction of parasitic capacitance by up to 21.2 intra- and 16.6 interwinding capacitances, without compromising resistance. This substantial capacitance reduction has a tangible effect on the regulation performance of $LLC$ resonant converters. Experimental results of the proposed PT structure in a 1.2 kW $LLC$ resonant converter show a reduction in common-mode noise, extended output voltage regulation, and improved overall efficiency of the converter.