Reduce Test Application Time Research Articles

A Modified and Customized Wingsuit Flying Search (MCWFS)-based Approach for the Circular Scan Architecture

The circular scan architecture (CSA) is a widely used scan design technique in digital circuit testing that involves scanning test data through a circuit in a circular pattern. Several optimization approaches have been suggested so far to lessen the Test Data Volume (TDV), but no one has shown satisfactory results. Therefore, this paper proposes a Modified and Customized Wingsuit Flying Search algorithm to decrease the test data volume time. The proposed MCWFS-SBA-CSA introduces some novel features that distinguish it from traditional circular scan approaches. The concept of wingsuit flying is an innovative approach in the field of scan systems. This allows the scan that moves more dynamically and efficiently, enabling it to cover a larger area in a shorter time than traditional circular-scan approaches. After this phase, only scan-chosen inputs are required to obtain the next test pattern from the captured response. Therefore, required less Automatic test equipment (ATE) memory in this research so there is a Decreased cost in system-on-chip (SOC). The proposed method attains fast global searching capacity. The efficiency of the proposed technique attains 26.42%, 32.45%, and 29.34% higher compression ratio (CR), Test Application Time (TAT) reduction of SC-128 attains 29.45%, 34.67%, and 40.22% higher, TDV of SC-256 attains 32.23%, 36.34%, and 39.23% higher than existing methods, such as TDV for Circular Scan Approaches utilizing Modified Shuffled Shepard Optimization (TDV-CSA-MSSO), Effectual Very-large-scale integration Test data compression system for CSA under modified and colony metaheuristic (ETDC-CSA-MACMH), and Test Data Compression Utilizing Tetrad state Skip System (TDC-DC-TSSC) for Digital Circuits, respectively.

An Efficient Segmented Random Access Scan Architecture with Test Compression

Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time compared to the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time. Also presented is another enhancement to incorporate a scan channel multiplex block at hierarchy segments which helps drastically decrease the area and routing overhead of the original architecture to practically implementable levels on commercial circuits. The extra Segment Data Multiplexor (SDM) blocks reduce the area overhead of other components by the multiplexing factor, and the reduction in overall area is significant based on experimental data. Test data compression and auto addressing of segments are achieved by transmitting a seed address to select segments with auto-increment or auto-decrement capability followed by either single cell selection or entire leaf cell segment selection. To further reduce the area overhead and test power, this architecture is enhanced to contain multiple channels at a cost of increased overall test application time with no increase in test data volume. Results of applying the enhancements to a large circuit with one level of intermediate segments with each of them having 256 leaf segments are presented in the paper with and without multichannel multiplexing for comparison.

Implementation of Energy Efficient BIST Architecture by Using Verilog

In a random testing environment, a significant amount of energy is wasted in the LFSR and in the CUT by useless patterns that do not contribute to fault dropping. Another major source of energy drainage is the loss due to random switching activity in the CUT and in the scan path between applications of two successive vectors. In this work, a new built-in self-test (BIST) scheme for scan-based circuits is proposed for reducing such energy consumption. A mapping logic is designed which modifies the state transitions of the LFSR such that only the useful vectors are generated according to a desired sequence. Further, it reduces test application time without affecting fault coverage. Experimental results on circuits reveal a significant amount of energy savings in the LFSR during random testing.

An Efficient VLSI Test Data Compression Scheme for Circular Scan Architecture Based on Modified Ant Colony Meta-heuristic

A new test data compression scheme for circular scan architecture is proposed in this paper. A stochastic heuristic based bio-inspired optimization approach namely ant colony algorithm (ACO) is applied after modification and customization to improve compression efficiency. In circular scan architecture, test data compression is achieved by updating the conflicting bits between the most recently captured response and test vector to be applied next. The quantity of conflicting bits also manifests the Hamming distance between the most recently captured response and the next test vector. A significant reduction in test data volume and test application time is achieved by reducing Hamming distance. The problem is renovated as a traveling salesman problem (TSP). The test vectors are presumed as cities and Hamming distance between a pair of test vectors is treated as intercity distance and a modified ACO algorithm in combination with mutation operator is applied here to resolve this combinatorial optimization problem. The experimental results confirm the efficacy of this approach. An average improvement of 6.36% in compression ratio and 4.77% in test application time is achieved. The exhibited technique sustains an optimal level of performance without incurring any extra DFT (design for testability) cost.

Reduction of Test Data with Hybrid Test Points

ATPG vectors for a combinational circuit exhibit correlations among the bits of a test vector. We propose a BIST circuit design methodology using spectral methods which utilizes the correlation information. This circuit serves dual purposes. It generates BIST vectors that are similar to the ATPG vectors with higher test coverage as compared to random and weighted random vectors. The same circuit can also function as a test data de-compressor for compressed ATPG vectors applied from an external tester. Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts cannot guarantee desired random testability. We present a hybrid test point technology designed to reduce deterministic pattern counts and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. We also exhibit test data compression capabilities of the proposed BIST architecture. This architecture provides a maximum test data compression exceeding and a proportional test time reduction for serial interface reseeding.

Logic BIST With Capture-Per-Clock Hybrid Test Points

Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts (PCs) cannot guarantee desired random testability. In this paper, we present a hybrid test point technology designed to reduce deterministic PCs and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a test pattern has been shifted-in. Experimental results obtained for industrial designs confirm feasibility of the new schemes, and they are reported herein.

Trimodal Scan-Based Test Paradigm

This paper presents a novel scan-based design for test (DFT) paradigm. Compared with conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage or allows applying a much larger number of vectors within the same time interval. An equally important factor is the toggling activity during test—with this scheme, it remains similar to that of the mission mode. Several techniques are introduced that allow integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.

IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs

A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%.

Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system‐on‐chip

Signature-based authentication is used often to authenticate hardware intellectual property (IP) when it is reused on a plug-and-play system-on-chip. A signature embedded in the functional/test component of a hardware IP can easily be verified as it can be generated and observed as functional/scan output of the hardware IP for a certain input key vector. An existing scan-based approach for embedding signature inserts signature through reordering of scan cells in a single scan (SS) chain. However, it is not applicable to the recent reconfigurable scan architectures having reduced test application time. We propose a scheme for embedding two distinct signatures separately in a reconfigurable scan architecture and verifying those without conflict from the packaged chip by using two distinct test modes of the reconfigurable architecture: namely, scan tree mode and SS mode. The two signatures may include one from logic IP source and the other from physical IP source. The overhead in both routing and power has been minimised in our scheme. Experimental results on design overhead and robustness for ISCAS89 benchmarks are very encouraging.

Applications of Mixed-Signal Technology in Digital Testing

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary and MVL is accomplished by digital to analog and analog to digital converters available in the mixed-signal technology. To support MVL test application and avoid reliability issues, we add necessary modifications on ATE and DUT sides. Theoretical calculation and a prototype experiment demonstrate significant data rate increase. We integrate the proposed MVL technique into test methodologies involving reduced pin-count test (RPCT) for multi-core system-on-chip (SoC) and test compression. An actual automatic test equipment (ATE) based test of a DUT shows notable reduction in test application time with MVL test application.

A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability

Wafer testing (wafer sort) is used in the semiconductor industry to reduce test costs. High parallelism is important to reduce test application time. However, increasing parallelism is becoming more difficult because the elements that drive test costs are increases in the pin count of the system on chip (SOC), and required automated test equipment (ATE) channels. While the need for parallelism has been growing, a reliability problem in which fault distribution causes good devices under test (DUT) to be improperly tested is becoming a concern. To achieve high parallelism and reliability, we propose a novel, massively parallel testing method using multi-root. In addition, we develop a test setup for setting the root-DUT location and the path of all DUTs. Using the proposed wafer testing method, test data can be transferred between the ATE and dies using multi-roots. The experimental results using ITC 02 SOC benchmarks show that the proposed method can reduce test costs up to 90%, and achieve nearly 94.84% test reliability without affecting yield.

A hybrid method for segmented test data compression

This paper presents a hybrid compression method for scan-based testing. Four distinctive compression techniques, i.e. frequency-directed run-length codes (FDR), inverting FDR, option coding technique, and optimal selective Huffman code are selected for compression of a given test set. To lift the potential compression limit, we properly cluster scan cells to classify test data as four subsets respectively, by majorities of 0s, 1s, Xs, and a roughly equal number of 0s and 1s to match specific properties of the compression techniques. Segments are then, respectively, compressed by the technique that fits best to achieve an overall good compression effect. Experimental results for the larger ISCAS’89 benchmark circuits show that up to 69.9% of average compression ratio and significant test application time reduction can be achieved.

Concurrent Core Test Based on Partial Test Set Reusing

A novel concurrent core test approach is proposed to reduce the test cost of SoC. Before test, a novel test set sharing strategy is proposed to obtain a minimum size of merged test set by merging the test sets corresponding to cores under test (CUT).Moreover, it can be used in conjunction with general compression/decompression techniques to further reduce test data volume (TDV). During test, the proposed vector separating device which is composed of a set of simple combinational logical circuit (CLC) is designed for separating the vector from the merged test set to the correspondent test core. This approach does not add any test vector for each core and can test synchronously to reduce test application time (TAT). Experimental results for ISCAS’ 89 benchmarks have been rproven the efficiency of the proposed approach.

Test Time Reduction in EDT Bandwidth Management for SoC Designs

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

Elimination of output gating performance overhead for critical paths in scan test

Excessive switching activity in test mode results in higher power dissipation than normal mode of operation and becoming a serious issue, in order to avoid reliability problems. Scanning of test vectors in test mode causes unnecessary switching in combinational block which can be reduced by gating methods. Gating the outputs of scan cells is a recently proposed very efficient low power test technique, which reduces the scan shift power significantly. However, the output gating techniques impacts the performance severely. In this paper, we propose a modified transistor level design of a scan flip-flop for critical paths, which eliminates the unnecessary switching in combinational circuit during shift phase of a scan-based test, without the impact on performance as in earlier scan flip-flop output gating schemes (Khatri and Ganeshan, 2008). The new scan flop design not only eliminates the performance overhead of output gating but also improves the performance of the scan flop by 32.84% (Khatri and Ganeshan, 2008) and 11.5% (Yang et al., 2008). The new flip-flop disables the output and uses an alternate path for shifting the test vectors. This approach have area overhead of six extra transistors but improves the overall performance of scan flip-flop, so this approach is better suited for critical paths. This also allows us to increase the shift frequency in designs where shift power dissipation puts upper bound on the frequency, and hence reduces test application time.

Reduction of test data volume and test application time by scan chain disabling technique

This article presents a method for test data compression aiming at simultaneously reducing test data volume and test application time for the scan sequential circuits. Compatible columns in the test set are repeatedly merged such that test data in the corresponding scan cells can be shared. To decode the compressed test data, a scan chain disabling technique is employed. Experimental results for the large ISCAS’89 benchmarks have demonstrated that significant reductions in both test data volume and test application time can be achieved.

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit model can specify many more inputs. A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for LOC delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group, where all scan flip-flops in the same group are assigned the same values for all test pairs. Sufficient conditions are presented for including any pair of scan flip-flops into the same group for LOC transition, non-robust path delay, and robust path delay fault testing. Test data for LOC delay testing based on the new scan architecture can be compressed significantly. Test application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for LOC transition, non-robust, and robust path delay fault testing. Folded scan forest and test response compactor are constructed for further test data compression. Sufficient experimental results are presented to show the effectiveness of the method.

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

In this paper, we present a technique called Digital Captureless Delay Testing Sensors (DCDTS). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions due to excessive resources (mainly test time or tester memory) requirements, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The DCDTS random patterns are internally generated, requiring virtually no additional test application time or tester memory. As such, DCDTS can be seen as a new way to save both test time and tester memory. Results show that DCDTS can achieve pattern volume and test time reduction factors of up to 3. When used in complement to existing compression techniques, DCDTS has the potential to triple their pattern volume (test application time) compression (reduction) rate. Area/performance overhead and technical obstacles to automation are minimal. An automated sensor selection procedure is proposed, with reasonable CPU time.

A Routing-Aware ILS Design Technique

The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flip-flops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

Scheduling Tests for 3D Stacked Chips under Power Constraints

This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.