Redistribution Layer Research Articles

Inspection Solution for 2μm RDL from Wafer-Level to Panel-Level Fan-out Process

In the advanced packaging industry, both fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP) have grown quickly in recent years since they are compatible with largescale, low-cost manufacturing and are key enablers for ultra-thin and high-density packages. However, the commercialization of the fan-out process continues to face technical challenges with the rapid adoption of finer pitch and width of the Cu redistribution layer (RDL) in die-first or die-last integration approaches. AOI has been widely used in the advanced packaging industry as a major tool for defect inspection during various process steps. The conventional bright field and dark field imaging techniques suffer from a high nuisance rate for RDL inspection; in many cases, the RDL metal grain size could be larger than the defect of interest, and the interferences from underneath the pattern, such as bottom RDL layers or molding compounds, can increase the difficulties of defect detection. In this paper, we present Onto Innovation’s innovative fluorescence technology to enhance contrasts between organic material, such as polyimide, or photoresists and metals that enable fine-pitch RDL inspection with increased accuracy by eliminating nuisance defects. By using powerful fluorescence technology, in conjunction with higher resolution, high-definition inspection (HDI) technology, fine-pitch RDL defect inspections on both wafer-level and panel-level packaging were studied and shown to enable accelerated development cycles in the R&D stage, as well enable rapid yield enhancements in the HVM environment.

Influence of Rigid Carrier Substrate and its Release Layer on Warpage of Fan-out chip last WLPs & PLPs

In recent years, the need for ultra-high density chip packaging devices and heterogenous integration devices require strategic placement of various components for high-performance computing (HPC), artificial intelligence (AI), etc. The fan-out chip last process with redistribution layer (RDL) first is expected as a solution to assemble these modules in advanced packages, which is essential for avoiding the risk of known good die (KGD) loss. During the assembly of the fan-out chip last WLP, elimination or minimizing warpage is an inherent challenge. It is caused by a thermal mismatch between various organic-inorganic – metallic – non-metallic – composite materials used in different layers of the package. If not controlled, then warpage from stresses induces alignment mismatch impacting package yield loss and reliability related issues. Warpage is minimized by using a rigid carrier substrate to build the RDL layers. The selection of this rigid carrier and its release layer influence the package warpage during the fan-out chip last WLP fabrication process. This paper focuses on the influence of rigid carrier substrate and its release layer on the warpage of fan-out chip last WLPs. Further, a solution towards controlling warpage has been provided using a novel material set referred to as HRDP® (High Resolution Debondable Panel). This is a drop-in approach compatible with the existing assembly flow. One of the important features of the HRDP® carrier is that it is offered in various dimensions and thicknesses. The HRDP® carrier is available for round wafers as well as for square/rectangular panel shapes in glass or silicon substrates to match the coefficient of thermal expansion (CTE) of the metal RDL, dielectric material, and Epoxy molding compound (EMC). This contributes to optimizing CTE related interfacial stresses and minimizes assembly warpage. Another key attribute of the HRDP® is its ease of debonding. Contrary to conventional debonding/release polymer layers, the HRDP® structure is composed of 100% inorganic material. It improves processing capability during RDL manufacturing, showing better chemical resistance and heat resistance than alternate technologies such as laser lift-off (LLO) type carrier

Prevention of Cu Electrolytic Migration Defects on RDL by a Cu-Selective Passivation to Enhance Reliability

Copper (Cu) is the metal of choice for the redistribution layer (RDL) to facilitate fast I/O communication in an integrated circuit (IC). Cu can electrochemically migrate (ECM) between the array of electrodes under bias, electrolyte, and moisture. IC packages fail miserably when exposed to various ion impurities and moisture. Copper at the anode dissolves to form Cu+1, +2 ions. As the anodic dissolution continues, the concentration of copper ion increases. These anions deposit on cathode leading to Cu dendrite formation. To achieve the near zero ppb defectivity goal, elimination of (ECM) defects in packaged devices is critical. This work discusses development of a novel Cu-selective passivation and a method to accelerate reliability testing. A hydrophobic passivation with minimum stress to the IC package is proposed in this work. The new passivation coating is thermally stable, strongly adheres to Cu, corrosion resistant, low cost and shows good potential to prevent ECM defects. The coated packaged devices were tested by an accelerated PEG drop test (PDT) to explore its ECM prevention capabilities.

Maskless direct write lithography for 3D wafer-level-system-integration

This publication presents lithography results for 3D wafer-level system integration applications using a reticle free maskless lithography system VPG+ 400 from Heidelberg Instruments. The focus is on high density Cu redistribution layer (RDL) formation with <2µm L/S used in polymer RDL stacks, overlay accuracy determination better than ±150nm and hybrid bond interconnect formation for 2µm interconnects, all processed on 300mm wafer size substrates.

A novel hybrid method to integrate delicate MEMS components into a FOWLP

A steep increase in IoT- and smart devices fuels the need for ever more miniaturized and highly integrated microelectronic packages. Fan-Out technology is well suited for this task, as it allows for heterogeneous (co-)integration of sensor elements and corresponding circuitry. Following a Chip-First approach in Fan-Out Wafer-Level Packaging (FOWLP), protection of delicate sensor areas during compression molding and formation of redistribution layers (RDL) becomes a key part of the manufacturing process chain. Such areas include thin membranes, antireflective coatings, air bridges or media access for gas sensors. We demonstrate a novel packaging method for a MEMS pressure sensor with corresponding ASIC (application-specific integrated circuit). We integrate vertical interconnect elements (VIE), instead of employing laser drilling for via formation and thereby avoid debris and reduce the overall package thickness. The hybrid approach, at heart, relies on a structured adhesive layer, onto which components are placed prior to compression molding. Due to its thermal and mechanical stability, the patterned thin film adhesive serves as a (first) dielectric layer. Process development includes warpage management to allow for laser debonding from temporary glass carriers and RDL processing compatible with delicate MEMS surfaces. Summarizing, we present a novel process variant to avoid common issues related to sensor surface integrity using Fan Out technology and thus allow for highly miniaturized System in Package (SiP) concepts with sensor integration by mold embedding.

The Study of Highest Thickness Photo Resist for Cu Post of Fan-Out Wafer Level Packaging

The mobile device’s limited thermal budget hardly allows the use of a high-performance application (AP) at its full speed. However, as artificial intelligence technologies has been rapidly applied for mobile devices, the demand like high-speed and large-capacity signal processing is continuously increasing. Therefore, controlling the heat generation of AP chip is becoming a key factor, and it is necessary to develop a Re-Distribution Layer (RDL) based Fan-Out Package (FOPKG) structure that does not increase the thickness of the package while maximizing the die thickness for heat dissipation. The height of Cu post is getting higher for the production of FOPKG that can apply thick die, and in this study, the world’s thickest photoresist material (>350um thickness) was developed for the production of Cu post (>300um thickness). The effect of light transmittance of the photoresist and the effect of solubility depending on the molecular structure of the main polymer were studied for lithography process of thick photoresist. Based on the understanding of this thick photoresist behavior, the optimal liquid type photoresist composition was developed. Through lithography evaluation based on thick photoresist characteristics, deep-hole via implementation and Cu electro-plating were performed to obtain a yield of Cpk 1.27 in the AP product design applied wafer. Depending on this in-depth understanding and experimentation on thick photoresist, it is possible to build an advanced research foundation of increasing the photoresist thickness and finer Cu post pitch to secure heat dissipation characteristics and improve the degree of freedom of architecture.

A high-efficiency transformer-in-package isolated DC-DC converter using glass-based fan-out wafer-level packaging

A transformer-in-package (TiP) isolated direct current–direct current (DC-DC) converter using glass-based fan-out wafer-level packaging (FOWLP) is proposed. By using 3-layer redistribution layers (RDLs), both the transformer and interconnections are built without an additional transformer chip, and the converter only has 2 dies: a transmitter (TX) chip and a receiver (RX) chip. The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density. Moreover, the transformer built by the RDLs achieves a high quality factor (Q) and high coupling factor (k), and the efficiency of the converter is thus improved. The TX and RX chips were implemented in a 0.18 µm Biopolar CMOS DMOS (BCD) process and embedded in a compact package with a size of 5 mm × 5 mm. With an output capacitance of 10 µF, the converter achieves a peak efficiency of 46.5% at 0.3 W output power and a maximum delivery power of 1.25 W, achieving a maximum power density of 50 mW/mm2.

Heterogeneous Integration Hybrid Substrate with Ajinomoto Build-Up Film

The design, materials, process, and fabrication of a hybrid substrate for the heterogeneous integration of chips with 50μm-pitch (minimum) by fan-out chip-last panel-level packaging are presented. The hybrid substrate consists of a fine metal linewidth (L), spacing (S), and thickness (H) RDL (redistribution-layer) substrate, solder joints with underfill, and a build-up package substrate. The dielectric material for the fine metal L/S/H RDL-substrate is an Ajinomoto build-up film (ABF).

Glass Substrate for Co-Packaged Optics

Co-packaged optics leads to significant power reduction by placing the electronic and photonic chiplets in a single package. An integrated electro-optical substrate made of glass with optical waveguides, through vias and electrical redistribution layers inside a single-sided cavity enables fine-line electrical routing and low-cost assembly. Existing glass and thin film technologies were evaluated and combined into a single process stream including photonic assembly. Photonic chips with silicon nitride waveguides were optically coupled to integrated low-loss (<0.1 dB/cm) glass waveguides with minimum loss of 0.65 dB achieved by fiducial alignment and pick-and-place assembly.

Efficient transient thermal analysis of chiplet heterogeneous integration

Thermal issue has significant effect on the reliability and performance of integrated circuits with the increase of integrated density, especially for 2.5-D and 3-D heterogeneous integration packaging systems. In this paper, a new highly efficient 3-D transient thermal distribution model has been constructed to capture the heat conduction behavior of multiple heat sources for chiplet heterogeneous integration (CHI) by improving the alternating direction implicit finite difference method (ADI-FDM). Firstly, a new floating optimization algorithm (FOA) of coefficient matrix assignment of heat conduction equation and a new boundary treatment utilizing virtual points are proposed to modify the ADI-FDM and improve the model efficiency of thermal analysis. Furthermore, a universal equivalent thermal conductivity model is also built up to describe the design features of through silicon via (TSV), bump and redistribution layer structures, which can enhance the flexibility of FDM-based thermal simulator. Compared with previous finite element analysis results, the present FOA-accelerated thermal model can not only obtain an accurate simulation result of temperature profile, but also give a simulation efficiency of 3.74 times faster than Douglas-Gunn approach for the coefficient matrix assignment. Finally, the effect of power consumption variation and the floorplaning effects of chiplets, TSVs and bumps on the temperature distribution are investigated in detail by utilizing the present FOA-based thermal solver. The simulated results of the present work demonstrate the viability and computational efficiency for temperature field optimization and indicate that the new proposed simulator is helpful in thermal analysis of packaging structures and can be adopted to assist in physical design optimization of 2.5-D CHI or 3-D heterogeneous stacked chips.

Chemical and Morphological Modifications Induced by Argon Plasma Treatments on Fluorinated Polybenzoxazole Films.

Fluorinated photodefinable polymers are widely employed as re-distribution layers in wafer-level packaging to produce microelectronic devices because of their suitable low dielectric constant and moisture absorption, high mechanical toughness, thermal conductivity and stability, and chemical inertness. Typically, fluorinated photodefinable polybenzoxazoles (F-PBOs) are the most used in this field. In the present work, we investigated by atomic force microscopy, X-ray photoelectron spectroscopy, and Fourier transform infrared spectroscopy the morphological and chemical modifications induced by Ar plasma treatments on F-PBO films. This process, used to remove surface contaminant species, as well as increase the polymeric surface roughness, to improve the adhesion to the other components during electronic packaging, is a crucial step during the manufacturing of some microelectronic devices. We found that argon plasma treatments determine the wanted drastic increase of the polymer surface roughness but, in the presence of a patterned silver layer on F-PBO, needed for the fabrication of electric contacts in microelectronic devices, also induce some unwanted formation of silver fluoride species.

Investigation into Impact of Redistribution Layer Design on Thermomechanical Stress in Embedded-Die Package

Thermomechanical stress generation on a silicon chip in an embedded-die package (EDP) was investigated. Change in thermomechanical stress on the chip with temperature was evaluated using piezo-resistance gauges fabricated on the chip. To investigate the impact of a redistribution layer (RDL) on stress generation, an EDP where filling materials facing the top and bottom sides and the periphery of the embedded die were entirely removed was fabricated. The removal of filling materials was carried out by using the CO2 laser ablation technology. RDL having diagonal paths from the substrate to the chip was designed and fabricated in addition to the conventional orthogonal RDL. RDLs were made of copper. Temperature tests were carried out in the range from 260 degrees C to 100 degrees C. The experimental results indicate that, while the origin of thermomechanical stress is a mismatch in coefficients of thermal expansion (CTE) between the chip and the organic substrate, RDL plays a significant role in generating the thermomechanical stress on the chip. The results also show that the diagonal RDL design effectively reduces thermomechanical stress from the orthogonal RDL design owing to its spring characteristic.

Thermomechanical Oriented Reliability Enhancement of Si MOSFET Panel-Level Packaging Fusing Ant Colony Optimization With Backpropagation Neural Network

Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a Fan-Out Panel-Level Packaging (FOPLP) design for 30V Si based Metal Oxide Semiconductor Field Effect Transistor (MOSFET). To achieve superior reliability of the packaging, we applied the Nondominated Sorting Genetic Algorithm with elitist strategy (NSGA-II) and Ant Colony Optimization–Backpropagation Neural Network (ACO–BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermo-mechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO–BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability ageing tests on the prepared devices.

Warpage Estimation and Demonstration of Panel-Level Fan-Out Packaging With Cu Pillars Applied on a Highly Integrated Architecture

Fan-out panel-level packaging (FO-PLP) has become a critical forward-looking technology because it can meet the demands for small size, high input/output counts, and multi-chip functions. Moreover, a three-dimensional stacked architecture called packaging-on-packaging can be achieved using the interconnects of Cu pillars. However, the serious warpage issue of FO-PLP during the manufacturing process causes many problems, such as assembly difficulty, low device reliability, and poor product yield. To address these problems, this study presents a process-oriented finite element analysis method to estimate the variation of the whole warpage resulting from the mismatch among the coefficients of thermal expansion of dissimilar materials during the fabrication procedures. Notably, the model construction of the complex redistribution layer in the proposed FO-PLP encounters a serious challenge when the simulated estimation is performed. Consequently, an equivalent mechanical characteristic extracted through simulation is adopted to redefine the material properties of RDL and Cu pillars separately. Moreover, modified Timoshenko bi-layered theory is employed with the process-oriented FEA of FO-PLP to clarify the stress-free temperature of the equivalent RDL. An actual FO-PLP vehicle with Cu pillars is fabricated and measured to demonstrate the reliability of the proposed simulation methodology. An average deviation of less than 10% is obtained between the simulated prediction and experiments. The results of factorial design indicate that the mechanical properties of dielectrics and RDL are the dominant factors and have an interactive effect on the warpage magnitude of FO-PLP.

High Gain and Wideband Antenna-in-Package Solution Using Fan-Out Technology

AbstractThe technology of fan-out wafer level packaging (FOWLP) has been widely adopted for millimeter wave antenna-in-package (AiP) system integration with low interconnection parasitic parameters. Present AiP solutions using FOWLP technology generally form antenna pattern on redistribution layer, which brings design inconvenience. In our work, a low-cost printed circuit board RO4350B laminate for substrate-integrated waveguide (SIW) antenna with a relatively large size is integrated, forms a three-dimensional stacked structure. The AiP employs a right-angle transition board embedded in epoxy molding compound (EMC), which transmits millimeter-wave signal to the SIW antenna stacked on the backside of EMC. The SIW antenna consists of 4 × 4 radiation slots with modified magneto-electric dipole for bandwidth enhancement. The measured gain is 14dBi at 60 GHz with bandwidth beyond 55–65 GHz. The three-dimensional AiP structure improves heat dissipation, no extra thermal design is needed for applications under 0.5 W mm-wave chip power consumption. The AiP module is manufactured and measured on the test board. The proposed approach is a convenient solution for wide band and high gain millimeter wave AiP system integration.

Impact of TSV bump and redistribution layer on crosstalk delay and power loss

The performance of a 3D IC is primarily reliant on the selection of an appropriate bump shape. The most prevalent bump shape (cylindrical) is experiencing substantial stress, power loss and crosstalk issues. TSV bump with a tapered structure have recently attracted considerable attention owing to its low volume fraction and coupling capacitance, that can substantially reduce the stress and crosstalk concerns. An impact of the redistribution layer (RDL), intermetal dielectric and high frequency skin effect are appropriately taken into account for the tapered TSV (T-TSV) with a cylindrical, barrel and tapered bump shape. A mathematical framework of the resistance–inductance–conductance–capacitance (RLGC) structure of the proposed T-TSV have been formulated by effectively considering the coupling, passivation and fringing capacitance of the RDL. In order to benchmark the proposed electrical equivalent circuit, the structural model of the T-TSV is validated against the fabrication based experimental results, and a subsequent analysis have been performed for the stress, crosstalk induced delay, and power loss. The proposed TSV structure is in good agreement with the experimental results with an average deviation of only 2.8%. Furthermore, irrespective of bump height, the tapered bump based T-TSV can effectively reduce the overall crosstalk induced delay, stress, power delay product (PDP), insertion and reflection losses with an average deviation of 20.22%, 22.30%, 23.55%, 8.01%, and 10.32%, respectively, when compared to the barrel and cylindrical bumps. In addition, it has been observed that the overall rate of change in PDP, power losses and crosstalk induced delay with considering RDL are 18.8%, 20.50%, and 25.22%, respectively independent of the bump shapes.

Non-integral depth measurement of high-aspect-ratio multi-layer microstructures using numerical-aperture shaped beams

This work presents a new optical metrology technique for accurate depth measurement of individual high-aspect-ratio (HAR) multi-layer microstructures with high spatial resolution and signal-to-noise ratio (SNR). To resolve the limitations of existing optical metrology techniques, light shaping with high light efficiency is optimized using numerical-aperture controlled laser beams. Experimental tests evidenced a 28-fold improvement in SNR for measuring large-depth structures when compared with measurements obtained using traditional broadband incoherent illumination. More importantly, instead of integral measurement characteristics currently limited by conventional spectral reflectometry or scatterometry, non-integral depth measurement of an individual microstructure from densely spaced microstructures such as through-silicon vias (TSV) and redistribution layers (RDL) can be realized using the developed optical measuring system with desired numerical aperture and field of view achieved simultaneously. As demonstrated by the measurement of a single submicron structure with linewidth as small as 0.6 µm and an aspect ratio of 5, the precision of depth measurement can be kept within a few nanometers.

A Critical Review of Lithography Methodologies and Impacts of Topography on 2.5-D/3-D Interposers

This paper analyzes the lithography design rules in package foundry and wafer foundry and reviews the major lithography techniques for package redistribution layer (RDL) fabrication for panel level 2.5D/3D interposers, fan-out packages and heterogeneous integration. The techniques surveyed in this paper are- contact aligners, projection aligners/steppers, laser direct writing (LDW) and laser ablation, capable of resolving routing line and space (L/S) of 0.8-1.5 μm with aspect ratio (AR) ≤ 5 and creating microvia with diameter of 1.5-2.0 μm at via pitch ≤5μm. The biggest challenge of advanced packaging is scaling the critical dimensions (CDs) on package to keep up with the pace of scaling of the bump pitch. In addition, there is a critical need for patterning fine lines-and-spaces with high aspect ratio to have low resistance traces. These high AR ultra-fine lines and ultra-fine pitch vias are crucial for meeting the needs of high-bandwidth die-to-die interconnections at high input/output (I/O) densities. All these challenges are mainly driven by lithography. With the development of advanced photoresists (PRs), the resolution factor K1 in projection lithography reduces from 0.66 to 0.39, improving the resolution by 40% without the negative impacts on the depth-of-focus (DOF). This paper also discusses the specific lithography challenges associated with topography of multi-layer RDL as well as their impacts on the fabrication of fine features. The fine pitch microvias can be a solution for scaling the I/O pitch down to 5-10 μm as a bumpless way to connect copper pads of known-good-dies to known-good- substrates in fan-out packages.

Proof of Concept for Sustainable Manufacturing of Neural Electrode Array for In Vivo Recording.

Increasing requirements for neural implantation are helping to expand our understanding of nervous systems and generate new developmental approaches. It is thanks to advanced semiconductor technologies that we can achieve the high-density complementary metal-oxide-semiconductor electrode array for the improvement of the quantity and quality of neural recordings. Although the microfabricated neural implantable device holds much promise in the biosensing field, there are some significant technological challenges. The most advanced neural implantable device relies on complex semiconductor manufacturing processes, which are required for the use of expensive masks and specific clean room facilities. In addition, these processes based on a conventional photolithography technique are suitable for mass production, which is not applicable for custom-made manufacturing in response to individual experimental requirements. The microfabricated complexity of the implantable neural device is increasing, as is the associated energy consumption, and corresponding emissions of carbon dioxide and other greenhouse gases, resulting in environmental deterioration. Herein, we developed a fabless fabricated process for a neural electrode array that was simple, fast, sustainable, and customizable. An effective strategy to produce conductive patterns as the redistribution layers (RDLs) includes implementing microelectrodes, traces, and bonding pads onto the polyimide (PI) substrate by laser micromachining techniques combined with the drop coating of the silver glue to stack the laser grooving lines. The process of electroplating platinum on the RDLs was performed to increase corresponding conductivity. Sequentially, Parylene C was deposited onto the PI substrate to form the insulation layer for the protection of inner RDLs. Following the deposition of Parylene C, the via holes over microelectrodes and the corresponding probe shape of the neural electrode array was also etched by laser micromachining. To increase the neural recording capability, three-dimensional microelectrodes with a high surface area were formed by electroplating gold. Our eco-electrode array showed reliable electrical characteristics of impedance under harsh cyclic bending conditions of over 90 degrees. For in vivo application, our flexible neural electrode array demonstrated more stable and higher neural recording quality and better biocompatibility as well during the 2-week implantation compared with those of the silicon-based neural electrode array. In this study, our proposed eco-manufacturing process for fabricating the neural electrode array reduced 63 times of carbon emissions compared to the traditional semiconductor manufacturing process and provided freedom in the customized design of the implantable electronic devices as well.

Design and optimization of on-chip thick-plated copper-transformers for galvanic isolated DC-DC converter achieving up to 38.9% peak efficiency

In this article, an approach for on-chip coreless transformers design and optimization is proposed and demonstrated for isolated DC-DC converter applications. This available approach was successfully executed by one fabricated sample and then with the aid of measurement and simulation its accuracy has been validated. Using the provided guidelines by EM simulation, transformers with different geometrical parameters were simulated and optimized based on the provided analytic model. The on-chip transformers within 6 μm thick-plated copper were implemented by re-distribution layer technique on 0.35 μm BCD platform. The proposed architecture was ultimately benefited from these evidences and fabricated as a stand-alone die. Finally, the targeted coreless transformer was integrated with oscillator and rectifier to verify the combined work and their efficiency. Results show that the transformers strictly follow the derived rule-set and meet the desired expectation. The assembled DC-DC converter is able to work effectively. Thanks to the optimization of fabricated structure of transformer, designed DC-DC converter delivers an excellent 38.9% efficiency at 3.3 V regulated output voltage in room temperature, while exhibiting isolated rating of better than 5 kVrms over a minute duration with 16 μm polyimide.