We demonstrate a polymeric vertical coupler for optical redistribution applications. The device is fabricated using a hybrid-lithography process, combining ultraviolet (UV) lithography for a planar optical redistribution layer (ORDL) with two-photon polymerization (TPP) for the vertical coupling micromirrors. By leveraging the high refractive-index contrast between the core and cladding, we realized an all-solid total internal reflection (TIR) mirror, eliminating the need for complex metallization or air cavities. To ensure manufacturability, we incorporated a support structure into the coupler design. Theoretical study predicts coupling efficiencies of 89.4% and 81.6% for the unsupported and supported structures, respectively. Experimental characterization of the fabricated device demonstrates a coupling loss of approximately 3.3 dB at a telecommunication wavelength of 1310 nm. This work provides a scalable and cost-effective approach for integrating high-performance vertical interconnects into 3D photonic systems.

This paper presents the electromigration (EM) performance of an embedded trace redistribution layer (ETR) in which the Cu trace features a rounded-bottom cross-sectional geometry and is encapsulated by a Ti barrier layer except for the top surface, with an optional top-side Ti cap. The ETR (with and without top-side Ti capping) and the conventional semi-additive-process (SAP) redistribution layer (RDL) are comparatively evaluated in terms of EM reliability. The ETR demonstrates a marked lifetime improvement compared with the SAP RDL. Notably, the Ti-capped ETR exhibits a minimal resistance increase in less than 10% even after a test duration of 4000 h. We discuss the key contributing factors and underlying mechanisms that support these improvements. Transmission electron microscopy (TEM) combined with atomic-percentage mapping confirms the effectiveness of Ti capping as a Cu diffusion barrier, showing continuous Ti coverage and no observable Cu diffusion. Electro-thermal simulations co-locate predicted thermal hot spots with experimentally observed open-failure sites, highlighting temperature-driven EM acceleration and the necessity of a barrier to suppress Cu–polymer interfacial oxidation. Stress simulations, together with EM failure analysis, indicate that the rounded-bottom Cu geometry alleviates local stress concentration and stress gradients, thereby creating conditions favorable for enhanced EM resistance.

The growing demand for lightweight and cost-effective vehicular armor systems has driven the development of hybrid multilayer architectures capable of improving ballistic resistance while reducing structural mass. This study evaluates the ballistic performance of a functionally graded aluminum–Kevlar–cabuya fiber composite system designed for vehicle door protection. A combined experimental–numerical framework was implemented, integrating ballistic testing according to NIJ 0108.01 and STANAG 4569 Level 1 standards with explicit dynamic finite element modeling based on the Johnson–Cook constitutive formulation for AA5083-H32. The multilayer configuration (25 mm aluminum/15 mm Kevlar 29/15 mm treated cabuya composite) successfully resisted 9 × 19 mm and 5.56 × 45 mm FMJ threats without complete perforation. Numerical simulations predicted a maximum back-face deformation of 52.75 mm under 9 mm impact, showing strong agreement with the experimental measurements (mean ± SD, n = 3). Post-impact microstructural analysis revealed a sequential energy dissipation mechanism governed by plastic deformation of the aluminum layer, Kevlar fibrillation and fragment retention, and controlled micro-cracking within the treated cabuya backing layer. With an areal density of 140.87 kg/m2, the system achieved a 19% weight reduction compared with conventional steel-based solutions. These results demonstrate the structural-scale feasibility of integrating treated cabuya fiber composites as active energy redistribution layers in certified hybrid vehicular armor systems.

Redistribution Layer (RDL), composed of layered dielectrics and electroplated copper materials, is a basic structure to rearrange numerous I/O pads on the chip surface in wafer-level advanced packaging. As the key chemicals in electrolyte baths, electroplating additives have undergone continuous development to meet the industrial needs for high-speed and fine-line/fine-pitch applications. Meanwhile, the intricate relationships between additive chemical structures and electroplated copper properties are yet to be well understood. In this work, a pair of triphenylmethane-based dye molecules, i.e., gentian violet (GV) and methyl green (MG), was comparatively investigated as levelers for high-speed RDL copper electroplating. Compared to GV, significantly stronger electrochemical polarization and tunable deposit morphology can be achieved by MG with just one extra quaternized amine terminal. Combining quantum chemical computations, in situ spectroelectrochemical analyses, and microstructural characterization, it is found that MG possesses enhanced electrostatic adsorption, surface coverage and multi-additive synergies, enabling tailored copper trace morphology. This study elaborates the adsorption mechanism and screening criteria of triphenylmethane-derived levelers, and presents a candidate additive structure for high-speed copper electroplating.

Fine-pitch redistribution layers (RDLs) are key enabling technologies for fan-out wafer-level packaging (FOWLP)-based interposers used in chiplet and high-bandwidth memory (HBM) integration. In this study, a CAR-based photolithography process optimized for fine-pitch RDL fabrication was evaluated to realize 2 μm/2 μm line/space (L/S) RDL structures in an FOWLP environment. Key lithographic parameters, including exposure energy, focus offset, and thermal processing conditions, were systematically optimized to establish a stable and reproducible process window. Cross-sectional analysis confirmed the structural integrity of the electroplated RDL features formed under the optimized conditions. To assess functional feasibility, channel-level electrical simulations were performed using JEDEC-defined HBM3 signal assignments. Simulated eye diagrams indicate that the fabricated fine-pitch RDL interconnects are capable of supporting HBM3-class signal transmission with a moderate level of signal integrity. The presence of jitter and noise suggests that further optimization of RDL transmission line impedance is required. Rather than presenting a fully optimized interposer solution, this work provides an engineering-level assessment of lithographic and process constraints associated with implementing 2 μm class RDLs in FOWLP-based interposers, offering practical insight into fine-pitch RDL process window definition for advanced packaging applications. This work uniquely combines systematic CAR-based lithography optimization with cross-sectional structural validation and HBM3-class channel-level simulations to define a practical process window for 2 μm/2 μm RDLs in an FOWLP environment.

Abstract In this study, 2D, 2.1D, 2.3D, 2.5D, 3D. 3.3D, and 3.5D IC integrations will be presented and updated. Chiplet communication such as bridges embedded in build-up package substrate and fan-out epoxy molding compound (EMC) with RDLs (redistribution layers) will be examined and updated. The high volume products by Cu–Cu hybrid bonding will be presented. High bandwidth memory (HBM) and customized HBM (cHBM) and CoWoS (chip on wafer on substrate) and CoPoS (chip on panel on substrate) are the key elements of high-performance computing (HPC) products driven by artificial intelligence (AI) will be discussed. CoWoS-S, CoWoS-R, and CoWoS-L will be systematically presented. Glass-core substrates and glass-core interposers will be provided. 3D heterogeneous integration of photonic IC (integrated circuits) (PIC) and electronic IC (EIC) driven by AI and high-speed communications will be presented. Some recommendations will be provided.

2.5D packaging has become a popular alternative to integrate advanced logic and memory chiplets for high-performance computing and artificial intelligence systems. In the conventional design flow, chiplets and packages are independently designed and then integrated at the assembly stage. To bridge the gap between chiplet designs and package designs, existing chiplet-package co-design methods iteratively optimize chiplet layouts to improve the performance of the entire system. However, Redistribution Layer (RDL) routing, which finishes the interconnections between chiplets at the package level and significantly affects the system performance, is neglected in the existing co-design flows. Therefore, this article proposes an effective chiplet-package co-design flow focusing on the RDL routing to optimize the package system performance dynamically. The proposed co-design flow can fill in the missing link, package-level co-optimization, of previous design flows. In the proposed co-design flow, we propose an efficient RDL routing algorithm to iteratively optimize the substrate layout based on the cross-boundary timing context extracted from both chiplets and the package. The proposed RDL routing algorithm has two critical techniques, including (1) a Maximal Independent Set-based (MIS-based) pin assignment method to dynamically optimize the pin positions of nets and (2) a network-flow-based router to generate routing layouts. Experimental results show that the proposed design flow can gradually improve the maximum frequency of a real design to the target performance, 400 MHz.

Abstract The advancement of Chip-on-Wafer-on-Substrate (CoWoS) technology has positioned three-dimensional (3D) packaging as a key enabler for next-generation artificial intelligence (AI) chips, thereby sustaining the trajectory of Moore’s Law. However, the continued scaling of critical dimensions (CDs), such as through-silicon vias (TSVs) and redistribution layers (RDLs), presents major challenges for CD metrology, primarily due to the difficulty of characterizing submicron hidden structures and limited light penetration. This study introduces an optimization framework based on global sensitivity analysis (GSA) to quantify the impact of CDs on optical responses and assess interaction effects on metrology performance. By combining GSA with rigorous electromagnetic simulations, the proposed approach enhances the extraction of CD information in optical critical dimension (OCD) metrology. In particular, this work systematically analyzes key structural parameters in both submicron silicon trench structures and copper redistribution layers (Cu RDLs), providing a unified evaluation across two representative classes of semiconductor architectures. Key structural parameters, including depth, top critical dimension (TCD), sidewall angle (SWA), and trench spacing, are systematically analyzed in submicron silicon structures. Furthermore, polarization optimization guided by sensitivity analysis is applied to maximize optical response sensitivity. Experimental validation shows that the GSA-optimized scatterometry setup achieves high measurement accuracy, maintaining a bias below 2% relative to focused ion beam/scanning electron microscope (FIB/SEM) benchmarks. The findings demonstrate that critical dimensions traditionally difficult to measure, such as depth and SWA of hidden submicron microstructures, can be accurately determined. Overall, the proposed methodology significantly enhances the accuracy and robustness of OCD metrology, providing valuable insights for advancing measurement strategies in 3D semiconductor packaging.

Abstract Geomorphometric methods can be used for improving the visibility of distribution data maps. The results of the finite element modeling, scanning electron microscopy and atomic force microscopy data processing are presented. The mechanical stresses in the redistribution layers structure, the homogeneity of the multilayer film, and the surface morphological features were studied. It was shown that the use of morphometric variable maps is effective for localizing inhomogeneities and makes it possible to detect structural features that are almost invisible in the original distribution data maps.

In heterogeneous three-dimensional integrated circuits, the vertical stacking of chiplets with different heat powers can lead to excessive overall temperature and poor stability in the heterogeneous integration system. This paper proposes an optimized thermal modeling approach for the layout of chiplets to enhance thermal performance. By extracting equivalent thermal conductivities for silicon through vias, microbumps, and redistribution layers in both horizontal and vertical directions, a multi-layer chiplet thermal model is established. This thermal model effectively estimates the peak temperatures in the heterogeneous integration system. In various stacking cases, the evaluation function with a proportional factor of heat dissipation in the central region is presented to evaluate the optimized layout of chiplets, thereby reducing peak temperatures in the system. The COMSOL simulations validate the proposed approach and demonstrate that the peak temperatures in the multi-layer chiplet models decrease by 21.73K, 19.12K, and 19.65K, respectively, with the optimized layout of chiplets. The thermal modeling approach exhibits a deviation of less than 3%, compared to the COMSOL results, with more uniform temperature distributions. The proposed approach is promising to provide a framework for thermal modeling and analysis in chiplets of heterogeneous integration systems.

The electromigration (EM) can introduce voids and hillocks in through-silicon vias (TSVs) and redistributed layer (RDL) interconnects, increasing the risks of short-circuit and open-circuit failures and thereby severely affecting the reliability of chiplet systems. In this article, the EM failure mechanism of the interconnects under electrical–thermal–stress multiphysics coupling is investigated, and a novel method for EM lifetime prediction based on coupled multiphysics modeling and finite element simulation is proposed. The implementation of dynamic failure simulation through element activation/deactivation technology employs a 20% void area ratio as the interconnect failure criterion, allowing for quantitative lifetime prediction. The consistency between the experimental and simulation results demonstrated the accuracy and effectiveness of the proposed lifetime prediction method. The overall prediction error is reduced by 11% with the state-of-the-art EM prediction method. Furthermore, based on this method, the effect of different interposer materials and TSV radii on interconnect EM is investigated. The evidence exhibits that using diamond as an interposer material can significantly mitigate interconnect EM phenomenon and enhance the reliability of the whole structure compared with silicon and glass. Furthermore, increasing the radius of TSV enhances EM resistance in interconnects, with each <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu $</tex-math> </inline-formula>m increase in radius extending the average interconnect lifetime by 12.75 h. Finally, the sensitivity analysis of diffusion-related constants further validates the robustness of the proposed model to critical parameters.

Purpose In the past 10 years, excessive research enthusiasm has been focused on 2.5D/3D advanced packaging (e.g. CoWoS/SoIC) used for data-center artificial intelligence (AI) chips and high bandwidth memory integration. For the edge AI chips with lightweight computing power, very thin FBGA (VFBGA), low power double data rate 5/5X (LPDDR5/5X) and wafer-level (WL) packaging with the redistribution layer (RDL)-first process are the integration technology trends. This paper focuses on AI system on chip (SoC) and LPDDR5X on-package integration design only using 3 RDL on the WL package. This paper aims to examine the influence to explore the trace routing scheme and corresponding signal integrity (SI) performance of the RDL interconnection for the on-package LPDDR5X, thereby providing RDL design and simulation reference for the ever-increasing demand for AI SoC and LPDDR5X on-package integration that is an alternative for on-board interconnection. Design/methodology/approach A design practice is used with type selection design and physical design. SI design and SI simulation are used to ensure the performance of the design practice. Detailed approach for the SI analysis consists of frequency domain and time domain simulation that are transmission line characteristics with coupled frequency domain and eye diagram analysis in the time domain. Findings Through the design practice and SI simulation analysis, VFBGA LPDDR5X and RDL-first technology are suitable for integration with AI SoC using WL packaging. Sub-10 µm line width and space design rule is required for the practice. The on-package integration SI performance is higher than that of on-board. Originality/value This paper is a technology application exploration and focuses on the design and SI simulation field. The main value is two-fold: on one side, providing a new solution for AI SoC and LPDDR5X integration; on the other side, extending the application range for WL packaging technology. The design and simulation results are valuable for the reference with the similar application.

Advanced packaging allows chiplet integration and maximizes device performance with faster product development cycle, lower cost, and higher yield. As the package size becomes bigger and the device is getting more complicated, there is growing motivation to employ manufacturing process simulation, Artificial Intelligence (AI) assisted process optimization, yield and reliability prediction, rather than conventional methods, to ramp the yield and to ensure the reliability of a new product. The key for an accurate process simulation model is to input precise material properties, such as modulus, Coefficient of Thermal Expansion (CTE), dielectric constant, glass transition temperature, etc., which could change non-linearly with temperature, moisture, as well as other environmental factors and process conditions. Molecular modeling and molecular dynamics can provide insights into post chemical reactions or physical transformations via atomic and molecular simulations Lithography Techniques for Redistribution Layer (RDL) fabrication are the foundation of Advanced Packaging techniques, such as Fan Out Wafer Level Packaging (FOWLP), Fan Out Panel Level Packaging (FOPLP), 2.5D, 3D, and 3.5D packaging with RDL interposers. The continuous scaling-down of critical dimensions (CDs) in advanced packages, including via diameters, routing line and space (L/S), to a few microns, or submicron level, as well as the increasing number of RDL layers at panel scale pose significant challenges in RDL lithography techniques. For example, the Photo Imageable Dielectric (PID) or other build-up dielectric materials used in multilayer RDL fabrication are polymers, having low Young’s modulus, high CTE, and big volume shrinkage after curing. These material properties could cause fabrication process induced warpage and surface topography deformations, such as non-planarity, roughness, contamination, defects, and dimensional variations, which could potentially lead to massive yield loss when forming fine features during the multilayer RDL patterning. This paper presents material simulation methodologies based on quantum mechanics (QM), molecular dynamics (MD), and Machine Learning (ML), which are adopted to predict the material properties of a PID material, including glass transition temperature (Tg), CTE, mechanical properties, dielectric properties, as well as volume shrinkage after curing. Comparison between the simulation results and the experimental data is performed to validate the methodology. Similar methodology could be used to predict material properties of other organic packaging materials, which is crucial for building up accurate process, yield, and reliability simulation or digital twin of advanced packaging.

There is an increasing demand for advanced substrates and interposers with fine line RDL to support complex 2.5D/3D packaging structures and thereby increasing data rate transmission on substrates/interposers. In addition, multiple interposer material designs, such as organic, glass, and silicon, are being explored in the industry to suit a wide variety of end applications. Novel dielectric dry film materials are needed to meet this demand across different designs. Filler-rich buildup films are well-suited for panel-level processing and have a well-established track record for reliability. With nanofiller technology, buildup film resolution has significantly improved. However, it remains a challenge for this strategy to deliver a smooth interface with high filler content and achieve high throughput with the laser ablation process. While polyimide-based materials have shown good utility in wafer level applications, they face additional rheological challenges in a dry film format, limiting their conformal planarization performance over topology and through cavity filling, such as through glass vias (TGV) and die-encapsulation in substrates. To meet the needs for finer pitch redistribution layer (RDL) designs with panel-level processing, the CYCLOTENETM photoimageable dielectric (PID) dry film (DF) platform has been developed. This PID platform is based on an aqueous-developable benzocyclobutene (AD-BCB) material and is suitable for embedded trace dual damascene processes with plasma descum and sputtering for seed layer deposition. The AD-BCB based PID has excellent cavity filling capability via vacuum lamination and is able to fill void-free up to 100µm diameter TGVs in a 400µm thick glass panel with 20µm thickness PID dry film. Over L/S 10/10µm Cu trace, 10µm PID dry film can achieve perfect filling between Cu traces without detectable top surface dimples with a two-stage Meiki laminator. Early generation DF6800 PID has been fabricated over a wide range of coating thicknesses, from 5µm to 40µm, with &lt;10% thickness variation. DF6800 has high resolution patterning capability for single-side PET-off processing. It can achieve &gt;2:1 aspect ratio for 20µm films with i-line stepper or LDI lithographic exposure tools. Cured films have passed bias HAST testing (130°C, 85% RH, 96hr, 5V) with line space patterning of 13 µm and 9 µm with no change in resistance and no copper dendrite formation. To further improve the utilization of the CYCLOTENE™ PID dryfilm platform in panel-level processing, a new generation of PID DF6800M has been developed to enable a PET-on dual-sided RDL buildup process. DF6800M is a PFAS-free formulation with a US-based material and supply chain. It is self-priming on Cu surfaces treated with MEC Etch Bond CZ8401 and achieves a 5B rating in the cross-hatch peel test post 96hr HAST. It retains high-resolution patternability with a low NA stepper, achieving &lt;10µm vias and &lt;7µm trenches on a copper-coated substrate treated with MEC Etch Bond CZ8100 &amp; CZ8401. Furthermore, DF6800M demonstrates robust post exposure delay (PED) stability for more than 24 hours. Since DF6800M is based on the same AD-BCB material, we expect it to deliver the same excellent cavity filling capability and reliability performance as demonstrated by DF6800. Based on these attributes, we believe DF6800M is highly suitable as a photo-imageable dielectric for advanced substrates and interposers needing fine line RDL required by 2.5D and 3D advanced heterogeneous chiplet integration schemes.

With the rapid advancement of artificial intelligence (AI) and high-performance computing (HPC), there is an increasing demand for sophisticated semiconductor technologies that can support complex computations and massive data processing. These technologies require advanced packaging solutions that deliver high performance, reliability, and miniaturization. High-density interconnect (HDI) technology plays a crucial role in meeting these requirements, particularly through modified semi-additive processing (mSAP) techniques. As AI and HPC applications push the limits of performance and miniaturization, HDI technology has evolved to meet the growing demands for integrated circuit (IC) substrates and printed circuit boards (PCBs). The move from traditional subtractive print and etch processes to mSAP has enabled the fabrication of finer features such as stacked vias, plated fine traces, and through holes. This shift supports the direct attachment of chips to organic IC substrates and increases the density of redistribution layers, which is essential for routing high-speed signals in advanced computing applications. The mSAP process enhances reliability by starting with a thin copper foil laminated onto an organic prepreg, which improves adhesion for fine lines. Copper is deposited onto this foil with precise imaging patterns, and a subsequent flash etching step removes the foil and electroless copper layer after the resist is stripped, resulting in highly accurate, rectangular fine lines. These fine lines are crucial for maximizing circuit density and achieving precise impedance control with minimal signal loss, which is vital for AI and HPC applications. However, one of the challenges in mSAP is the occurrence of V-pits during the flash etching step, which can compromise the reliability of the final product. To address this issue, some fabricators use an additional baking step to mitigate pitting, but this increases production costs and reduces throughput. Therefore, there is a need for innovative copper electroplating solutions that can provide consistent etching during the flash etching step, effective via filling, and fine line resolution.This study explores the mechanisms behind pitting and proposes new processes to reduce its formation. We investigate various factors affecting pitting, including the choice of plating electrolytes, additive concentrations, plating current densities, etching rates, and baking conditions. Analytical techniques such as X-ray diffraction and focused ion beam scanning electron microscopy (FIB/SEM) were used to analyze the grain structure of the copper deposits.The optimized copper electroplating process discussed in this study demonstrates excellent via filling capabilities, high fine line resolution, and robust through-hole plating in a single bath. The resulting deposits exhibit superior physical properties, such as tensile strength and elongation, exceeding IPC class III requirements. These advancements ensure that HDI technologies can meet the stringent demands of AI and HPC applications, offering reliable and high-performance solutions for the future of computing.

As the influence of artificial intelligence (AI) continues to grow, it shapes the future of advanced packaging by enabling smarter designs and adaptive manufacturing processes that address emerging challenges. Advanced packaging through chiplet integration offers significant value for applications that demand high performance and high-density requirements, such as AI, high performance computing (HPC), and data centers. One of the novel advanced packaging platforms for this solution is the fan-out embedded bridge technology. This technology integrates multiple chiplets with diverse functions into one single package using a small silicon (Si) bridge die which is embedded in the fan-out organic redistribution layer (RDL) interposer layers. This design enables ultra-high-density die-to-die (D2D) connections with line/space (L/S) dimensions of less than 1/1 um. In addition to providing flexibility in Si bridge and L/S design selections for various applications, this technology is also more cost-effective than 2.5D Si Interposer package with through-silicon via (TSV) structure. Moreover, this bridge technology facilitates the integration of other components by strategically embedding it beneath the active die for die-to-die interconnects or embedded power modules. In this paper, we will explore the warpage behavior on complex integration of embedded bridge technology with and without embedded power module components. Both Si bridge die and the power components have small, and thin structures with various thicknesses, presenting challenges during package assembly processes that can exacerbate warpage on top of existing chiplet integration in embedded bridge technology. High warpage result, which is typically measured using the Shadow Moiré technique on finished chip module (CM) may lead to possible defects during assembly process, like non-contact open, bridge, non-wet or stretch joint. These issues can lead to failures at time-zero and during reliability tests. Additionally, we will analyze various warpage behaviors and performance scenarios through simulations that involve only Si bridge dies, and power components in conjunction with Si bridge dies. Finally, this paper elaborates on methods to control warpages to ensure high-quality integration, which is crucial for outsourced semiconductor assembly and tests (OSATs).

As the industry moves toward High Performance Computing(HPC) for huge data transmission with low power consumption. The requirements for PKG structure have become more challenging. The major engineering requirements for HPC application are high-density, high-speed data transmission, low loss, precision manufacturing with low-cost process. High pin count need large area package with high mechanical stability and low warpage. The demand for high density and high-speed data transmission becomes strong needs for leading edge semiconductor packaging. 2.5D and 3D heterogenous package realize this solution. On the 2.5D heterogenous package structure, key technology is fine wiring connected with CPU chip and HBM chips. The fine wires needed high speed transmission. Silicon interposers with through silicon vias (TSVs) have developed to meet this demand, but face three major barriers high electrical loss, package size and cost. On the other hand, glass has many properties that make it an ideal substrate for BGA core substrates such as ultra-low loss tangent, adjustable thermal expansion (CTE), mechanical stability and manufacturability with large panel size. This paper presents the demonstration of Fine line Redistribution Layer (RDL) on Glass and Glass Core Substrate with fine pitch metalized through via. The ultra-high density RDL process using non-organic protective layer fabricated on the glass substrate. High aspect ratio 3 traces enable to minimum 3um pitch, high transmission rate and high reliability. We also focus on the potential for applying high-speed transmission performance to the next generation such as HBM3 and UCIe 1.0 based on the analysis of electromagnetic field simulation and the measurement results obtained from the fine pitch wiring composed on the glass material. We conducted experimental measurement on the electrical transmission characteristics of fine-wiring with a width ranging from 1.5 µm to 3 µm. Furthermore, our proposed fine wiring structure of covered with inorganic material had less influence on signal transmission performance. We have done actual measurement comparison with inorganic protective layers and without inorganic protective layers. we checked a comparative evaluation of eye patterns using measured S-parameters at the high-speed signal transmission condition with transient analysis. Furthermore, we utilized the obtained measurement results to validate their applicability for next- generation high-speed transmission, and we report the findings of our verification.

We present silicon nitride photonics on glass (SING), demonstrated at the wafer-level, establishing its feasibility for high-density optical redistribution layers (RDLs) in panel-level packaging. Demonstrated passive components support 106 Gbps transmission, enabling scalable wafer-level optical interconnects with grating couplers, ring resonators, MMI couplers, MZIs, and stitched waveguides. With a compact 100 µm bend radius, SING enables a 10× higher density than LDW or IOX glass platforms, while remaining compatible with large-panel processing. This positions SING as a promising and scalable solution for next-generation optical RDLs.

A novel four-in-one (4-in-series) MicroLED-in-Package (MiP4) architecture is demonstrated for the first time, integrating four sub-85 µm blue micro-LED (µ-LED) dies on a transparent glass substrate through a redistribution-layer (RDL) interconnection process. The MiP4 device operates natively at 16 V, eliminating the need for step-down converters and simplifying high-voltage backlight driving circuits. The transparent glass carrier enables efficient light extraction, excellent thermal dissipation, and uniform emission. Electrical and optical characterization of dual- (B2), triple- (B3), and quad-chip (B4) devices shows ideal voltage scalability (8 V, 12 V, 16 V) and stable emission at 450 ± 2 nm with minimal FWHM broadening (22-29 nm). Compared with a commercial LED, the MiP4 delivers 1.8× higher optical power (~41.8 mW) despite its active area being only ~1/70 that of the reference device (20,000 µm2 vs. 1,350,000 µm2), yielding a dramatically enhanced luminous flux density of 64 lm/mm2 at 50 mA. Furthermore, pulse-driven measurements under 2%, 5%, and 10% duty cycles verify excellent thermal stability and minimal spectral shift (<1 nm), confirming the device's robustness and energy efficiency. This first-of-its-kind 4-in-1 high-voltage glass-based µ-LED package provides a scalable and manufacturable route toward next-generation ultra-thin, high-brightness Mini-LED backlight and optical communication systems.

The growing demand in the industry for high-performance electronic devices that offer enhanced functionality, reduced power consumption, and increased speed is fueling innovation in advanced packaging technology. Enhancing semiconductor chip performance and advancing package features are essential. One approach to producing high-performance electrical systems that meet compute-intensive requirements in space-constrained products is to use miniaturized packages with advanced embedded components. In addition to ensuring sufficient yield from the lithographic process to maintain high density and preserve valuable components, a key aspect of RDL formation is accurately aligning each layer of the production board with the corresponding component during lithography. A viable solution is to measure the deviation between the target and actual positions, digitally recalculate and reroute the interconnects in the RDL pattern, and then process the adjusted data into a raster image format for a maskless direct imaging process. The paper presents results from the EU-funded CHARM project, in which AT&amp;S supplied FHG IZM with embedded components measuring 26 mm x 18 mm x 110 µm. During the embedding process, build-up (BU) polymer resin (ABF®) material was used to symmetrically embed temporarily fixed components using a carrier. After exposing the copper pillars (30 µm diameter) through the BU film, a PVD technique was used to deposit titanium and copper on the surface. To connect the embedded components, IZM developed an adaptive patterning process that includes an optical measurement routine and software to digitally correct the manufacturing data. The corrected data is then fed into a maskless lithography tool, ensuring that each unique device on each panel is accurately registered. In addition, results will be presented on how the semi-additive process (SAP) can be improved by using an enhanced direct imaging process on an embedded die to achieve a resolution of 5 µm L/S despite the challenges posed by topography and surface roughness. Furthermore, this paper briefly discusses the development of the essential technology blocks for high-density redistribution layers required for the realization of organic substrate-based packages. The chosen technological approach is advanced semi-additive processing (aSAP) on a large scale. This method includes the use of dielectric layers such as ABF or similar materials, PVD seeding and additive electrolytic copper deposition. It also describes the application of thin PVD seeding layers below 50 nm and the incorporation of plasma processes for dry etching of photoresists, surface cleaning and back etching of seed layers on 610 mm x 457 mm panels.