Recovery Circuit Research Articles

Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

Selective Recovery of Copper from a Synthetic Metalliferous Waste Stream Using the Thiourea-Functionalized Ion Exchange Resin Puromet MTS9140

The extraction of Cu from mixed-metal acidic solutions by the thiourea-functionalized resin Puromet MTS9140 was studied. Despite being originally manufactured for precious metal recovery, a high selectivity towards Cu was observed over other first-row transition metals (>90% removal), highlighting a potential for this resin in base metal recovery circuits. Resin behaviour was characterised in batch-mode under a range of pH and sulphate concentrations and as a function of flow rate in a fixed-bed setup. In each instance, a high selectivity and capacity (max. 32.04 mg/g) towards Cu was observed and was unaffected by changes in solution chemistry. The mechanism of extraction was determined by XPS to be through reduction of Cu(II) to Cu(I) rather than chelation. Elution of Cu was achieved by the use of 0.5 M–1 M NaClO3. Despite effective Cu elution (82%), degradation of resin functionality was observed, and further detailed through the application of IC analysis to identify degradation by-products. This work is the first detailed study of a thiourea-functionalized resin being used to selectively target Cu from a complex multi-metal solution.

A 10.4–16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD

A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This wide-range FD is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five samples on the five-bit data patterns, the FFD performs an error-free operation within a frequency error of 7.7%. Therefore, the CDR has a robust FD-to-PD transition. By using the proposed FD, this CDR circuit not only achieves a wide frequency capture range of 43%, but also has a short frequency settling time of $680~\mu \text{s}$ . This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b.

Thermodynamic cycles and electrical charge recovery in high-efficiency electrocaloric cooling systems

• A linearized model provides insight into electrocaloric cooling thermodynamic cycles. • Derivations for Brayton, Carnot, and Otto cycles are provided. • Modeling results highlight the importance of efficient charge recovery. • Brayton and Otto cycles can be more efficient than Carnot cycles in practical systems. This paper introduces a linearized model of electrocaloric cooling. The model is derived for electrocaloric Brayton, Carnot, and Otto cycles, and a more practical hybrid constant voltage-charge (HCVC) variation of the Otto cycle. It is then parametrized for a benchmark terpolymer material. Model outputs are used to examine the system performance under each cycle as a function of temperature lift. The impact of electrical charge recovery efficiency on performance is then investigated to provide insight into system optimization requirements. Practical limitations of charge recovery circuits are discussed in the context of heat and work transfer in each cycle leg. Results indicate that electrical charge recovery efficiency greater than 95% is needed to achieve competitive system efficiency and that this is challenging with a Carnot cycle, despite its theoretical optimality. The Brayton and Otto cycles, in contrast, can achieve cooling efficiencies that approach the theoretical maximum.

Моделювання та програмний комплекс для дослідження функціонування ежектора в змінних режимах

One of the current directions of development of modern energy-saving and energy-efficient technologies for ship and stationery (including municipal) energy is the use of ejector refrigeration machines, which can be used for air conditioning systems together with an absorption refrigeration machine (cascade cycle) or vapor compressor refrigeration machine as part of cogeneration or trigeneration units. Such circuit solutions can be used together with ensuring the rational organization of work processes in the main elements of the refrigeration machine, in particular in the jet device - ejector, the appropriate design of which, in turn, will further increase the thermal coefficient. Improving the design of the ejector is a rather complex and long process and does not always give positive results. It is primarily because many tests are required on full-scale models. Therefore, computer simulation of the ejector operation at different variable input parameters, considering the geometric characteristics of the flow part and variable mode characteristics during operation is more attractive in terms of finding options for rational (optimal) design. The paper presents the results of software development for modeling hydrodynamic processes in the flowing part of the ejector, considering the variable operating modes of the ejector refrigeration machine. The existing method for calculating the pressure and circulation characteristics of jet devices is used. The developed software complex "RefJet" in the design mode defines the maximum achievable coefficients of ejection of a jet ejector. In the simulation mode - provides determination of the ejection coefficients of the already designed (certain sizes) ejector at variable values of pressure at the inlet and outlet in specific operating conditions, considering its operation at the limit and partial modes. The work of the software package was tested in the development and analysis of circuit solutions of ejector refrigeration machines as part of the heat recovery circuits of three-generation units based on internal combustion engines and gas turbine engines.

Design and Evaluation of Clocked Differential Adiabatic Logic Families for Low Power Applications

In this paper, clocked differential adiabatic logic families, namely, Clocked CMOS Differential Adiabatic Logic (CCDAL) and Clocked Differential Cascode Adiabatic Logic (CDCAL) pertinent to low power applications have been presented. Charge recovery operation of these circuits are realized by the use of complementary two phase sinusoidal power signals. CCDAL uses clocked control transistor in addition to the differential CMOS logic structure which makes it suitable for higher frequency operation. Compared to the existing charge recovery circuits, CCDAL achieves reduced floating nodal output problem resulting in improved drivability and circuit robustness. CDCAL a variant of CCDAL has also been presented which displays enhanced frequency over CCDAL. The feasibility of operating these logic families at a system level design has been evaluated through design of a digital FIR filter which could be used in magnetic disk drive applications. A 4-tap 6-bit FIR filter has been designed using 90nm CMOS technology library and simulations are carried out using industry standard Cadence® Virtuoso tool. The simulation results prove that proposed adiabatic FIR filter achieves significant energy savings compared to its pipelined static CMOS logic counterpart.

Economic Geology Models 5. Specialty, Critical, Battery, Magnet and Photovoltaic Materials: Market Facts, Projections and Implications for Exploration and Development

Many exploration companies are now focusing on specialty materials that are associated with so-called ‘green technology’. These include ‘battery materials’, ‘magnet materials’ and ‘photovoltaic materials’, and many such commodities are also broadly labelled as ‘critical materials’ because they are seen as vital for industrial development, societal needs or national security. The definitions used for such materials are not always consistent among jurisdictions or across industry, and this paper attempts to clarify the criteria and address some common misconceptions. The distinction between major minerals (e.g. base metals) and ‘specialty materials’ (i.e. those mined or produced in much smaller amounts) is particularly important. The markets for many specialty materials are growing faster than those for traditional ferrous, precious and base metals and they are often portrayed as excellent long-term investment opportunities. However, the small market bases for specialty materials and considerable uncertainty around growth projections (especially related to material substitutions and rapid technological change) need to be taken into consideration for objective assessment of the development potential of any proposed project, establishment of new supply chains by major corporations, and responsible decision-making (mineral policy) by government. In the short-term, projects aimed at specialty materials (materials with a small market base) cannot benefit from economy of scale, and their development hinges on commercially proven metallurgical processes, unless they are supported by governments or end-users. Several specialty metals (e.g. germanium, indium, cadmium, and cobalt) are commonly obtained as by-product of base metal extraction. In such cases, systematic testing of base metal ores for their specialty metal content may justify the addition of relevant recovery circuits to existing smelters. If positive results are obtained, the need for targeting new sources of such specialty metals as primary exploration targets may be reduced or eliminated. Where market conditions permit and concerns about the future availability of materials seem reliable, grass-roots exploration for specialty materials is warranted, and pre-competitive government involvement may be justified to promote such development efforts.

Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits

In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter between the recovery clock and the input data can be estimated with a sub-picosecond accuracy, as demonstrated in the simulation results of a 56 Gb/s quarter-rate MM-CDR implemented in 28 nm CMOS.

Diesel fuel substitution using forestry biomass producer gas: Effects of dual fuel combustion on performance and emissions of a micro-CHP system

Despite the massive electrification of the energy sector, combustion-based technologies will continue to play a key role for decades to come. Therefore, to meet the ambitious target of decarbonization of the energy sector, adapting current technologies to alternative energy sources, like biofuels, is a must. The proposed work aims at investigating the role of biomass producer gas in compression ignition (CI) engines, as a substitute of diesel fuel. A micro combined heat and power generation system (CHP) consisting of an open-top downdraft gasifier, a single-cylinder water-cooled CI engine and a waste heat recovery circuit have been set-up with the aim to investigate emissions and performance at several Diesel Substitution Rates (DSR), up to 50 %. Maximum substitution levels – which occur due to knocking limitations and combustion instabilities - have been also identified. The main results show: i) a decrease of thermal and electrical efficiencies in the range of 10–30 %; ii) strong NOx and smoke opacity reductions (with peaks close to 80 %); iii) an increase of CO emissions (above 50 %); iv) the assessment of a decreasing maximum DSR as the power load increase (98 % at the lowest load, up to 46 % at full load). Such findings offer quantitative results through which multi-objective optimization procedures could be implemented. Moreover, experimental results indicate the need for a diesel injection timing optimization strategy to mitigate CO emissions.

Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation

This article proposes compact expressions for the jitter in clock and data recovery (CDR) circuits based on bang-bang phase detector including the phase noise of the transmitter and receiver oscillators as well as the quantization noise associated with the finite number of phases of the phase interpolator (PI) that align the receiver clock to the incoming data. Different approaches to perform the Early/Late detection on deserialized data and edge samples are compared: the use of majority voting degrades the CDR bandwidth, increasing the impact of the clock jitter on the CDR jitter; on the other hand, counting the single Early/Late occurrences does not degrade the bandwidth but increases the noise related to the finite phases of the PI. The proposed analytical formulas are validated against event-driven behavioral simulations of the CDR system including free-running oscillators as well as phase-locked loop (PLL) for clock generation.

Optimization of geometric parameters and analysis of exergy efficiency of heat recovery units glass furnaces

The paper presents the results of optimization of the geometric parameters of the heat exchange surface of water and air-heating heat exchangers of glass-making furnaces and an analysis of their exergy efficiency. Ensuring the efficient operation of heat recovery units in various thermal circuits is an urgent problem of heat power engineering. The aim of the work is to establish the optimal areas of the geometric parameters of the heat exchange surface of heat recovery units of glass-melting furnaces and to analyze their exergy efficiency. The paper presents the results of solving the tasks necessary to achieve the goal: - using statistical methods for planning the experiment, determine the levels of variation of the parameters of the geometric surface of heat transfer for the heat recovery units under study and calculate the values of the criteria for evaluating the efficiency at the points of the central orthogonal compositional plan; - to obtain the regression equations for the investigated heat exchangers, to determine the optimal areas of change in the geometric parameters of the heat exchange surface and the corresponding exergy efficiency criteria. To determine the optimal areas of geometric parameters of the heat exchange surface, a complex methodology is used based on the methods of exergy analysis and statistical methods of the theory of experiment planning. It has been established that when designing heat recovery schemes for heating water in heat supply systems and for heating blast air, heat recovery units with the following values of the areas of variation of the geometric parameters of the heat exchange surface can be used: - the values of the area of variation of the distance between the panels for heat recovery units with a staggered and corridor arrangement of pipes in a bundle s1 = 58.0-62.0 mm. - the values of the areas of change in the diameter of pipes for a hot water heat exchanger with a corridor arrangement of pipes d = 41.0-43.0 mm and for an air heating heat exchanger with a staggered and corridor arrangement of pipes d = 29.0-31.0 mm. - the use of the values of the ranges of change of other parameters is carried out taking into account additional technological factors. It has been established that the exergy efficiency of hot water heat recovery units is in all cases higher than the exergy efficiency of air heating units. For hot water heat exchangers, the values of exergy criteria are lower than for air heating ones: k – 2.0 times, ε – by 7.5%, m0 – 1.9 times. The expediency of using the investigated heat recovery units in heat recovery circuits of glass melting furnaces has been established, taking into account the results obtained and in the presence of certain technological factors. The results obtained and further developments in the field of optimization of the operating parameters of heat recovery units for glass-melting furnaces will provide an increase in the efficiency of heat recovery equipment for power plants.

A 0.13-μm CMOS resonator-based frequency-doubling mechanism for clock recovery in a full-rate 40 Gb/s optical receiver

A clock recovery circuit for a full-rate 40 Gb/s optical receiver is presented. The proposed circuit consists of a frequency doubling block, a mixer-based phase detector, and a 40 GHz voltage-controlled oscillator. The frequency doubling block, consisting of a tuned amplifier and a frequency doubler, adopts the LC-resonator loads, rather than the conventional resistive loads, which realizes operation at 40 GHz clock frequency. The circuit is fabricated in 0.13-μm CMOS technology. Measurement results indicate that the proposed circuit is able to recover a 40 GHz clock. The recovered clock frequency is at least 1.4 times higher than other competing circuits.

Solar-powered ejector-based adsorption desalination system integrated with a humidification-dehumidification system

The paper presents an integrated solar-driven desalination plant. It consists of an adsorption desalination (AD), a humidification-dehumidification (HDH) desalination, and two ejectors. The HDH unit reuses the silica gel AD cycle's waste energy to enhance the proposed integrated system's freshwater production rate. Two ejectors are also installed to improve freshwater productivity further. Two configurations are studied: with and without condenser/evaporator heat recovery (HR) circuit. In this regard, mathematical energy and cost models are built to examine the performance of solar-powered hybrid desalination systems installed in Assiut, Egypt, at different operating parameters. The model is validated against the available results in the literature. The solar irradiation, ambient temperature, adsorption cycle time, and HDH air mass flow rate on the cycle performance are studied. The highest freshwater is produced when the ratio between the mass flow rate of feed saline water and the air is about 1.4. When HR is applied, the specific daily water production (SDWP) reaches 83.1 m3/ton in June with a gained output ratio (GOR) of 2.7. The cost analysis shows that the specific cost of freshwater produced from the proposed desalination plant using HR loop is about $1.49/m3 when Solar Energy runs the proposed system. This particular water cost could decline to $0.54/m3 when waste heat is used.

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

Research of functionality of using a storage tank for regulating heating load of a gas piston mini-CHPP

The use of a storage tank to regulate the loads of the mini-CHP plant improves the technical and economic indicators of its operation. However, the results of studies of the use of a storage tank in heating systems, in contrast to hot water supply systems, are poorly represented. The purpose of the study is to determine the conditions and indicators under which the use of a storage tank to regulate the heating load of a mini-CHPP is economically viable. The study of the heat grid is based on solving the standard heat balance and heat transfer equations. Modeling of heat transfer in the heat recovery circuit of a cogeneration unit is carried out by approximating the passport specification of the equipment in the range of operating loads from 50 to 100 %. Modeling the standing time of the outside air temperatures is carried out in accordance with the method of B. Shifrinson and V.Ya. Khasilev. The conditions of the numerical study are quite typical for the heating network of Donetsk. For the first time, to satisfy the conditions of a numerical study, the dependence of the available and used thermal capacity of the storage tank on the outside air temperature has been established for different values of the design volume of the tank. The quantitative characteristics of the influence of the design volume of the storage tank on electricity generation during peak, half-peak and minimum power system loads are investigated. The reliability of the results obtained is determined by the correct use of proven methods for calculating the operation parameters of water heating system and heat devices. The study shows that the use of a storage tank to regulate the heating load of a mini-CHPP is technically and economically feasible. With the design volume of the storage tank in the range of 65–126 m3 per 1 MW of the connected heating load, the simple payback period of the mini-CHPP varies insignificantly and can be considered acceptable. The presence of a storage tank allows realizing the maneuverable capabilities of cogeneration units, while maintaining a high share of energy generation in combined mode. The district heating coefficient, equal to one, allows achieving high efficiency of fuel utilization for generation of both electrical and thermal energy. The research results can be used in municipal heat supply systems when introducing gas piston cogeneration units.

A 0.32–2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition

This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency acquisition processes are being done to achieve an unrestricted frequency acquisition range and a fast frequency acquisition time. The CDR is implemented in a 180 nm CMOS process, consumes 62 mW of power including I/O buffers at 2.7 Gb/s with a 1.8 V supply. The CDR takes 15.2 μs of a maximum locking time when the data rate locked at 2.7 Gb/s is switched to 320 Mb/s. The CDR circuit has shown 59 ps and 75.4 ps peak-to-peak jitter in recovered clock and data, respectively, with 2.7 Gb/s input data.

An Energy-Autonomous Power-and-Data Telemetry Circuit With Digital-Assisted-PLL-Based BPSK Demodulator for Implantable Flexible Electronics Applications

Wireless power transmission and data telemetry technology has been widely adopted in healthcare applications based on flexible electronics. It is challenging to achieve high data rate (up to Mbps), low bit-error-rate (BER< 0.1%) data telemetry, as well as simultaneous high energy-efficiency power transmission, with small-volume flexible devices. In this paper, an energy-autonomous power-and-data telemetry circuit with digital-assisted-phase lock loop (PLL)-based binary-phase-shift-keying (BPSK) demodulator for implantable flexible electronics applications has been proposed. Only a single pair of coils has been employed to transmit both power and data based on a BPSK modulated Class-E amplifier. The energy recovery circuit enables a battery-less energy-autonomous implantable device. The proposed digital-assisted control circuitry resets the PLL to maintain the lock state and demodulate the BPSK data. As a result, the maximum data rate is no longer limited by the PLL’s bandwidth, which can be improved significantly. The chip has been implemented with standard 180nm CMOS process, occupying an area of 0.96 mm 2 . The post-layout simulation shows up to 2.26 Mbps data rate can be achieved with a low BER less than 8.6x10 −5 with the coupling factor ranging from 0.13 to 0.17. Thanks to the digital-assisted-PLL-based demodulator, the power consumption of the receiver is only $817.4 ~\mu \text{W}$ and the demodulator Figure-of-Merit (FoM) is 362 pJ/bit with 13.56 MHz carrier frequency. The energy-autonomous circuit based on a single and small-volume pair of coils demonstrates its potential capability to be applied to various kinds of implantable biomedical applications.

Optimal control of high-power density hybrid electric vehicle charger

This research utilizes a hybrid technology through resonant line-level control phase-shifted full-bridge (HR-LLC-PSFB) dc–dc converter. In this research, a line level control (LLC) auxiliary circuit is used to achieve zero-current soft-switching turned-off operation of a controlled switch. The zero-voltage soft-switching turned-on operation is achieved by using the transformers’ magnetic branch energy and the energy reflected by the output filter inductor. The effective turn’s ratio of the isolating transformers is used to reduce the inverter circuit’s voltage stresses. The effect of voltage overshoots and freewheeling circulating current in rectifying branches is improved by implementing an energy recovery circuit with an output filter. A closed loop coordination proportional integral derivative (PID) controller is proposed to generate the pulse width modulation (PWM) control signal to transmit smooth power by controlling output voltage and current values. The droop constant current charging (CCC) and reduced constant current charging (RCCC) technique is proposed for the charging process. Simulations performed in MATLAB and results substantiate the proposed work superiority in comparison to other topologies.

A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller

To improve the jitter tolerance (JTOL) of a clock and data recovery (CDR) circuit, a background loop gain controller (BLGC) is presented. This CDR circuit is realized in a 40nm CMOS process. Its active area is 0.0324mm2 and the power consumption is 12.67mW from a 1 V supply. For 1-Gb/s and 3-Gb/s PRBS of $2^{15}$ -1 and the bit error rate $ , the measured root-mean-square jitter of the retimed data are 12.3ps and 7.74ps, respectively. By using the proposed BLGC, the minimum high-frequency JTOL at 3-Gb/s is improved to 0.68 UIpp.

A Design of a 15-GHz, Voltage-Controlled Ring Oscillator in 130-nm CMOS Technology: Optimizing Central Frequency and Power Dissipation

The voltage-controlled oscillator (VCO) is a critical block in the electronic and communication systems. It may be applied in frequency synthesis, clock signal generation, and a clock recovery circuit. In this article, the authors present the design and performance analysis of a 15-GHz, voltage-controlled ring oscillator using the 130-nm CMOS technology that operates in a 1.8-voltage power supply for high-speed applications. The designed scheme is a fivestage ring oscillator, which includes one inverter replaced by the NAND gate to shut down the ring oscillator during inactive mode. For improving the efficiency of the ring oscillator in the transceiver, different techniques such as transistor sizing are employed. In comparison to other publications, the authors' ring oscillator design is optimized with reference to the central frequency and power dissipation.