Reconfigurable Receiver Research Articles

A 0.5–15 GHz reconfigurable IR-UWB receiver in 28 nm CMOS

A 0.5–15 GHz ultra-wideband (UWB) RF reconfigurable receiver in UMC 28 nm CMOS used for IR-UWB (impulse radio UWB) radar system is proposed in this paper. This receiver employs a 0.5–8 GHz path and an 8–15 GHz path to achieve the wide frequency band, and we proposed an RF channel select voltage-to-time converter (VTC) circuit. Two different low noise amplifiers (LNAs) are adopted in the two paths to obtain the high performance of noise figure (NF) and gain. The common drain stage and resistance negative feedback technology as well as the source degeneration inductive technology are introduced to achieve a high flat gain and fine input matching. The R-2R variable load network of a programable gain amplifier (PGA) gives it a nearly 24 dB dynamic range and approximately linear gain control. A 500MS/s time domain analog to digital converter (TD-ADC) with an equivalent sampling rate of 16GS/s is shared for the two paths which can realize the direct RF sampling. The input RF signal path selection is implemented by configuring the Band_sel signal. The receiver has reconfigurability of the RF front end and better power consumption and area. In the frequency of 0.5–8 GHz, the S11 is below −7.9 dB and the NF is smaller than 6 dB. In the frequency of 8–15 GHz, the S11 is below −8dB and the NF is smaller than 11 dB. The receiver dissipates 242.72mW with an area of 1.01 mm2

Reconfigurable Receiver With Adaptive Output Voltage for Wireless Power Transfer

Reconfigurable Receiver With Adaptive Output Voltage for Wireless Power Transfer

A Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 22-nm CMOS

This paper presents a low noise, and high linearity reconfigurable receiver (RX) analog baseband (ABB) with tunable bandwidth (BW) and gain for multi-standard applications. The designed ABB consists of a programmable gain amplifier (PGA) and a second-order active RC low-pass filter (LPF) with cutoff frequency range from 0.7 MHz–10 MHz, whereas the gain could be tuned between 0 dB and 49 dB. The proposed ABB is implemented in 22 nm CMOS process. The post-simulation results show that the current consumption is 3.36 mA from 1 V supply and the area occupies 571×328 μm 2. The ABB achieves 42.8 dBm in-band third-order harmonic intercept point (IIP3). The spurious-free dynamic range (SFDR) and in-band total harmonic distortion (THD) is 83.2 dBc and is -83.1 dB, respectively. The input referred in-band integrated noise (IRN) is 144.8 μVrms . A digital DCOC is used to calibrate the output DC level.

A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS

In this article, a 0.7–2.5-GHz tri-mode reconfigurable receiver (RX) for global navigation satellite system (GNSS)/narrow band-Internet of Things (NB-IoT)/Bluetooth low energy (BLE) applications is realized targeting one chip capability of integrating both wide area network (WAN) and local area network (LAN) protocols as well as positioning characteristics in 28-nm CMOS process with a compact core area of 1.7 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . By applying the proposed variable gain wideband active balun-low noise amplifier (LNA), the RX achieves minimum noise figure (NF) of 2.8 dB with the power consumption of 43 mW. The harmonic rejection (HR) method suppresses the signal interference caused by on-chip coupling. 68-dB 3rd HR ratio (HR3) is achieved with only one-stage HR circuit. The mismatch between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula> channel and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> channel may limit the image rejection of the complex bandpass filter (CBPF). Detailed mathematical analysis of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> calibration circuit is provided. Owing to the virtual short characteristic of the amplifier, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> calibration scheme achieves a high-precision phase calibration. About 60-dB image rejection ratio (IMRR) is obtained after calibration.

A reconfigurable wireless superheterodyne receiver for multi-standard communication systems

ABSTRACT The rapid growth of the communication frequency band leads to the diversity of receiving frequency bands of smart devices. This paper proposes a reconfigurable wireless superheterodyne receiver for multi-standard communication systems. The receiver is designed through architecture design, chip selection, layout drawing, and physical measurement. The designed receiver consists of receiving module, local oscillator module, and control module. Unlike previous receivers, the proposed receiver selects the frequency channel, local oscillator frequency, and link gain through the control module in the current scene. The control module consists of a single-chip microcomputer and computer. The receiver can work in application scenarios including 2.4–2.5 GHz, 3.3–3.6 GHz, and 4.8–6.0 GHz. This paper discusses the design process of the proposed reconfigurable receiver in detail. Compared with the traditional receiver, the proposed receiver can change its working mode by software and has the characteristics of flexible reconfiguration. In addition, it has the advantages of a large link gain range and good demodulation performance. Moreover, the receiver is low in design cost and easy to manufacture. Therefore, it can be widely used in receiving modules of WLAN and 5G communication systems.

Blind parameter estimation of turbo convolutional codes: Noisy and non-synchronized scenario

Blind estimation of forward error correction code parameters at the receiver plays a significant role in non-cooperative communication, adaptive modulation and coding systems, and reconfigurable receiver systems. Turbo convolutional codes, a parallel concatenation of multiple convolutional codes, are used in digital communication and storage systems to achieve low bit error rate. The present paper proposes innovative algorithms for the blind estimation of code parameters and reconstruction of turbo convolutional encoder over noisy scenario. The turbo convolutional code is designed using two component codes along with an interleaver. Recursive systematic convolutional codes are used as component codes. Any imperfection in synchronization of received data for the proposed code parameter estimation algorithm is compensated through a bit position adjustment parameter. The performance of the proposed algorithms in terms of parameter estimation accuracy is investigated for different modulation order, code rate, and constraint length values. It is observed that the performance improves with decrease in modulation order and constraint length values.

Dual-Band Wireless Power Transfer With Reactance Steering Network and Reconfigurable Receivers

Wireless power transfer (WPT) via near-field magnetic coupling is an enabling technology for many applications. A few WPT standards are under development with frequencies ranging from kilohertz (kHz) to megahertz (MHz). Operation in kHz offers a higher power rating and that in MHz offers a smaller size. This paper presents a dual-band WPT architecture with novel transmitter and receiver topologies that can achieve high performance at both 100 kHz and 13.56 MHz with low component count and decoupled power delivery at different frequencies. On the transmitter side, we introduce an enhanced push–pull Class-E topology together with a reactance steering network (RSN), which can seamlessly compensate the load impedance variation for MHz wireless power transmitters. On the receiver side, we present a reconfigurable dual-band rectifier that can achieve a power density of 300 W/in $^3$ with low component count and low total harmonic distortion. A complete dual-band WPT system comprising an RSN-based dual-band transmitter and multiple reconfigurable receivers has been built and tested. The WPT system can simultaneously deliver a total of 30 W of power to multiple receivers (15 W maximum each) with 82.5% efficiency at 100 kHz and 74.8% efficiency at 13.56 MHz with 2.8 cm of coil distance and up to 5 cm of coil misalignment.

Determination of LO frequency for reception of maximum number of GNSS signals in presence of interference

A method for the frequency determination of a local oscillator (LO) is presented to facilitate reception of the maximum number of satellite signals via the use of a multi-global navigation satellite system (GNSS) receiver under interference. The authors have herein suggested a model for estimating the number of GNSS satellites with changing LO frequency. This estimation model was derived based on GNSS and interference spectra, used to determine the LO-frequency value to avoid interference and facilitate reception of maximum GNSS signals. The proposed method was verified by means of an experiment involving the use of software-defined radio receiver and actual GNSS signals. The authors expect the proposed method to be the basis of anti-interference processes in reconfigurable GNSS receivers.

Reconfigurable RF receiver using compact distributed switch matrix for array coils

Magnetic resonance (MR) signals captured by RF array coils should be delivered to analogue-to-digital converter (ADC) channels through an independent receiver (Rx) circuitry for precise MRI process. Since different types of RF coils should be utilised by a fixed port configuration on a patient table with a limited number of ADC channels, a highly flexible Rx front-end design is necessary. In this Letter, a compact distributed switch matrix structure for multi-channel RF coil Rx is proposed for supporting different types of array coils with small circuit size and sufficient reconfigurability. The proposed structure is configured by a multiple number of unit matrix cells consisting of a single double pole double throw and two single pole double throw RF switches to control the pathways of received MR signals. The proposed structure was implemented and verified at 9.4-Tesla (9.4 T) MR frequency (400 MHz) by comparing different RF path losses.

A 0.7–7 GHz wideband reconfigurable receiver RF front-end in CMOS

A 0.7–7 GHz wideband RF receiver front-end SoC is designed using the CMOS process. The front-end is composed of two main blocks: a single-ended wideband low noise amplifier (LNA) and an in-phase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers. Based on a self-biased resistive negative feedback topology, the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth. The passive down-conversion mixer includes two parts: passive switches and IF amplifiers. The measurement results show that the front-end works well at different LO frequencies, and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency. The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB, a minimum noise figure (NF) of 3.2 dB, with an IF bandwidth of greater than 500 MHz. The chip area is 1.67 × 1.08 mm2.

Design of a reconfigurable front‐end for a multistandard receiver for the frequency range of 800 MHz to 2.5 GHz

SummaryIn this paper, a reconfigurable receiver front‐end for the frequency range of 800 MHz to 2.5 GHz is presented. The radio frequency front‐end is realized in wideband form with reconfigurable baseband filter. The proposed front‐end targets the GSM, WLAN, WCDMA, and GPS standards residing in the aimed frequency range. The necessary specifications for each individual standard have been revisited and recalculated. The interaction of the different standards and their interoperability has been thoroughly investigated and extra specifications derived for the multistandard receiver. The multistandard receiver has been designed, layouted, and simulated in RFCMOS 0.18‐μm process.

An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS

An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a low-band (LB) RF path (0.1–1.5 GHz) and a high-band (HB) RF path (1–5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with $LC$ resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver’s resilience to out-of-band interferences. A novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20–76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate −5-dBm interference with 16-dB noise figure (NF) and achieve 95–105-dB maximum conversion gain and 1.7–8-dB NF over 0.1–5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68-dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The system-level measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

ABSTRACTA composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply.

Reconfigurable OFDM based transceiver for Wireless Communication

Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier modulation technique which is very much popular in new wireless networks of IEEE standard. It has improved the quality of long- distance communication by eliminating Inter Symbol Interference (ISI) and improving Signal-to-Noise Ratio (SNR) And Multipath Fading. Reconfigurable OFDM based transceiver in information security gives high benefits to the wireless communication and used for multipurpose requirements. Reconfigurable transmitters with all the digital modulation techniques are flexible to all the end users without reconfigurable receiver with single modulation technique. Digital 8 bit data which is input to the system that is converted to the high digital signals at the end of receiver side. Receiver output is given to the microcontroller and examining the input data in connected mobile, hence communications between two end users are fully secured.

Computationally efficient method for estimation of angle of arrival with non-uniform reconfigurable receiver arrays.

The main focus of this paper is the design and formulation of a computationally efficient approach to the estimation of the angle of arrival with non-uniform reconfigurable receiver arrays. Subsequent to demodulation and matched filtering, the main signal processing task is a double-integration operation. The simplicity of this algorithm enables the implementation of the estimation procedure with simple operational amplifier (op-amp) circuits for real-time realization. This technique does not require uniform and structured array configurations, and is most effective for the estimation of angle of arrival with dynamically reconfigurable receiver arrays.

Reconfigurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation

A software-defined radio receiver that is suitable for intra-band carrier aggregation is demonstrated. The RF front-end frequency selectivity is enhanced by the combination of the passive mixer and a proposed reconfigurable transimpedance amplifier. High order bandpass filtering function with frequency notches can be achieved at the front-end. Current domain complex signal processing is explored to select and separate multiple channels concurrently. The receiver contains a variety of functional building blocks that can be connected in different ways to form various architectures. The fine-grained programmability of component parameters and reconfigurability of receiver schemes enable optimum performance under varying signal and blocker scenarios. A proof-of-concept CMOS chip fabricated in a 65 nm CMOS technology is presented that supports up to three-channel aggregation. The receiver operates at any frequency between 0.5 to 3 GHz. The frequency separation between the concurrent RF channels can be tuned anywhere between 0 to +100 MHz. The concurrent receiver scheme can also be explored to reject large near-band blockers for high dynamic range.

Dual-Carrier Aggregation Receiver With Reconfigurable Front-End RF Signal Conditioning

A reconfigurable receiver that can support dual-carrier aggregation is demonstrated. Switched Capacitor (SC) technique is explored at the receiver front-end for direct RF signal conditioning. By changing the connections of the switches and capacitors, various filtering profiles, including bandpass and notch functions, can be synthesized. On the other hand, complex-domain signal processing enables RF selectivity with controllable offset frequency relative to the LO frequency. Therefore, multiple RF channels can be selected simultaneously by multiple complex-domain signal processors and a shared single front-end. The scheme also enables a 4th-order RF bandpass transfer function by combining two 2nd-order bandpass transfer functions with slightly different center frequencies. In this work, a combination of a reconfigurable front-end passive SC network and two concurrent complex-domain signal processors enables the receiver to handle different signal scenarios. A proof-of-concept CMOS chip fabricated in a 65 nm CMOS technology is presented that supports single-channel and dual-carrier aggregation receiving modes. The receiver covers the frequency range from 0.1 to 1 GHz. The frequency distance between two concurrent RF channels can be tuned anywhere between 0 to +100 MHz. The near-band blocker resilience is improved by 15 dB when the front-end is configured as a notch filter.

SiGe BiCMOS high‐gain and wideband differential intermediate frequency amplifier for W‐band passive imaging single‐chip receivers

This thesis presents solutions and studies related to the design of reconfigurable and wideband receiver circuits for system-on-chip (SoC) radiometer front-ends within the millimetre-wave (mm-wave) range. Whereas many of today’s mm-wave front-ends are bulky and costly due to having discrete RF components, single-chip receiver modules could potentially result in a wider use for emerging applications such as wireless communication, short range radar and passive imaging security sensors if realised with adequate performances and at a lower cost. Three main topics are considered in this thesis, monolithic integration of low-loss RF-MEMS (Dicke) switch networks and switched LNAs in MMIC/RFIC foundry processes, designs of SiGe wideband (IF) amplifier and broadband power detectors up to W-band (75-110 GHz).Low-loss and high isolation GaAs and SiGe RF-MEMS switch networks were designed and characterised for the 30-110 GHz range. A GaAs MEMS Dicke switch network has a measured minimum loss of 1 dB and maximum isolation of 19 dB at 70-96 GHz, respectively, making it a potential candidate in Dicke switched radiometer receivers. Furthermore, single-chip 30 GHz and W-band MEMS Dicke switched LNA designs have been realised for the first time in SiGe BiCMOS and GaAs mHEMT processes, respectively.For a targeted 94 GHz passive imaging application two different receiver topologies have been investigated based on direct-detection and direct-conversion (heterodyne) architectures. An optimised detector design fabricated in a 0.13 μm SiGe process achieves a more wideband input matching than earlier silicon W-band detectors and is competitive with reported III-V W-band detectors in terms of a higher responsivity and similar NEP.A SiGe 2-37 GHz high-gain differential (IF) amplifier design achieves a more wideband matching and an order of magnitude higher linearity than a recent single-ended SiGe LNA. The SiGe IF amplifier was integrated on-chip with a power detector in a 5-35 GHz IF section. Their broadband properties compared with other IF amplifier/detector RFICs, make them suitable for W-band down-conversion receivers with a larger pre-detection bandwidth and improved sensitivity. The experimental results successfully demonstrate the feasibility of the SiGe 5-35 GHz IF section for high performance SoC W-band radiometers using a more wideband heterodyne receiver architecture.

A Multi-Channel Random Demodulation Reconfigurable Receiver

In this letter, we propose a new approach to recon- figurable receivers using random acquisition techniques. Random projections have been widely used within the context of com- pressive sensing for sub-Nyquist signal acquisition. In the system we propose, we design the random sensing signals so as to filter undesired components in the signal and result in measurements equivalent to those obtained had the signal been filtered prior to acquisition. Because the random signals are digitally generated, the system is reconfigurable; the signal's components to be filtered can be changed by changing the digitally generated random sig- nals. The system digitizes the measurements at a rate proportional to the desired bandwidth only, not the total signal bandwidth. Index Terms—Reconfigurable receivers, random signal acquisition.

Mitigation of Total Dose Performance Degradation in an 8–18 GHz SiGe Reconfigurable Receiver

An 8-18 GHz receiver implemented in silicon-germanium (SiGe) BiCMOS technology is presented. The receiver is designed to enable built-in test (BIT) and consists of a low noise amplifier (LNA), an image-reject mixer, on-chip, automatic gain control (AGC), ring oscillator (RO) sources (used to provide test signals of a predefined amplitude), and digital-to-analog converters (DACs), used for DC bias control of the blocks. The voltage and current biases of both the LNA and the mixer circuit blocks are used as tuning knobs for radio frequency (RF) performance metrics to mitigate the negative effects of total ionizing dose (TID) radiation damage present in extreme environments such as space. Samples of the receiver die were exposed to 10 keV X-rays at 1, 3, and 6 Mrad( SiO2) doses. The BIT system was able to mitigate for TID damage in most cases, with improvements in the key RF metrics of gain, output third-order intercept point (OIP3), and noise figure (NF). The receiver was fabricated in an 0.18 μm SiGe BiCMOS process technology with a peak fT of 150 GHz and nominally consumes 241-243 mA from a 4 V supply.