Reconfigurable Hardware Devices Research Articles

A Survey On Image Registration Techniques Using FFT

Image Registration is the process of straightening two or more images of the same scene with testimonial to a particular image. The images are captured from various sensors at different times and at multiple viewpoints. Thus, to get a better picture of any change of a scene/object over a considerable period of time image registration is important. Image registration finds application in medical sciences, remote sensing and in computer vision. This paper presents a detailed review of several approaches which are classified accordingly along with their contributions and drawbacks. The main steps of an image registration procedure are also discussed. Different performance measures are presented that determine the registration quality and accuracy. The scope for the future research are presented as well. Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to experiment with algorithms. Reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. At present, however, users must program FPGAs at a very low level and have a detailed knowledge of the architecture of the device being used. To try to reconcile the dual requirements of high performance and ease of development, this paper reports on the design and realization of a High-Level framework for the implementation of 1-D and 2-D FFTs for real-time applications. Results show that the parallel implementation of 2-D FFT achieves virtually linear speed-up and real-time performance for large matrix sizes. Finally, an FPGA-based parametrizable environment based on the developed parallel 2-D FFT architecture is presented as a solution for frequency domain image filtering application

Using FPGA-Based AMC Carrier Boards for FMC to Implement Intelligent Data Acquisition Applications in MTCA Systems Using OpenCL

The Micro Telecommunications Computing Architecture (MTCA) standard is widely used in developing advanced data acquisition and processing solutions in the big physics community. The number of applications implemented using commercial Advanced Mezzanine Cards (AMC) using AMD-Xilinx and Intel® Field Programmable Gate Array (FPGA) systems on chips is growing due to the flexibility and scalability of these reconfigurable hardware devices and their suitability to implement intelligent applications using artificial intelligence and machine learning techniques. The paper presents the specific design methodologies for hardware acceleration proposed by both FPGA manufacturers. Comparative results are obtained from two different software/hardware setups using two different AMCs, one based on Intel® FPGA Arria 10 and another based on Xilinx ZynqMP. The paper illustrates the process of how to modify the board support package, required by the hardware acceleration methodology, to implement the JESD204B and Low-Voltage Differential Signaling (LVDS) interfaces with the FPGA Mezzanine Card (FMC) modules containing the ADCs, to prepare the AMC cards to implement such kind of applications. The data acquisition and processing implementation inside these reference designs, with both languages OpenCL and High-Level Synthesis (HLS), is described. An important feature, needed for many applications in the big physics field, is the interface with the Experimental Physics and Industrial Control System (EPICS) software framework using the ITER Nominal Device Support framework, which is briefly described.

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

Current edge computing systems are deployed in highly complex application scenarios with dynamically changing requirements. In order to provide the expected performance and energy efficiency values in these situations, the use of heterogeneous hardware/software platforms at the edge has become widespread. However, these computing platforms still suffer from the lack of unified software-driven programming models to efficiently deploy multi-purpose hardware-accelerated solutions. In parallel, edge computing systems also face another huge challenge: operating under multiple conditions that were not taken into account during any of the design stages. Moreover, these conditions may change over time, forcing self-adaptation mechanisms to become a must. This paper presents an integrated architecture to exploit hardware-accelerated data-parallel models and transparent hardware/software multithreading. In particular, the proposed architecture leverages the ARTICo <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> framework and ReconOS to allow developers to select the most suitable programming model to deploy their edge computing applications onto run-time reconfigurable hardware devices. An evolvable hardware system is used as an additional architectural component during validation, providing support for continuous lifelong learning in smart edge computing scenarios. In particular, the proposed setup exhibits online learning capabilities that include learning by imitation from software-based reference algorithms. Experimental results show the benefits of the proposed approach, exposing different run-time tradeoffs (e.g., computing performance versus functional correctness of the evolved solutions), and highlighting the benefits of using scalable data-parallel models to perform circuit evolution under dynamically changing application scenarios.

Intrinsic Evolution of Analog Circuits Using Field Programmable Gate Arrays.

Evolvable hardware is a field of study exploring the application of evolutionary algorithms to hardware systems during design, operation, or both. The work presented here focuses on the use of field programmable gate arrays (FPGAs), a type of dynamically reconfigurable hardware device typically used for electronic prototyping in conjunction with a newly created open-source platform for performing intrinsic analog evolvable hardware experiments. This work targets the reproduction of seminal field experiments that generated complex analog dynamics of unclocked FPGAs evolved through genetic manipulation of their binary circuit representation: the bitstream. Further, it demonstrates the intrinsic evolution of two nontrivial analog circuits with intriguing properties, amplitude maximization and pulse oscillation, as well as the robustness of evolved circuits to temperature variation and across-chip circuit translation.

An Extensive Study of Flexible Design Methods for the Number Theoretic Transform

Efficient lattice-based cryptosystems operate with polynomial rings with the Number Theoretic Transform (NTT) to reduce the computational complexity of polynomial multiplication. NTT has therefore become a major arithmetic component (thus computational bottleneck) in various cryptographic constructions like hash functions, key-encapsulation mechanisms, digital signatures, and homomorphic encryption. Although there exist several hardware designs in prior work for NTT, they all are isolated design instances fixed for specific NTT parameters or parallelization level. This article provides an extensive study of flexible design methods for NTT implementation. To that end, we evaluate three cases: (1) parametric hardware design, (2) high-level synthesis (HLS) design approach, and (3) design for software implementation compiled on soft-core processors, where all are targeted on reconfigurable hardware devices. We evaluate the designs that implement multiple NTT parameters and/or processing elements, demonstrate the design details for each case, and provide a fair comparison with each other and prior work. On a Xilinx Virtex-7 FPGA, compared to HLS and processor-based methods, the results show that the parametric hardware design is on average <inline-formula><tex-math notation="LaTeX">$4.4\times$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$73.9\times$</tex-math></inline-formula> smaller and <inline-formula><tex-math notation="LaTeX">$22.5\times$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$19.3\times$</tex-math></inline-formula> faster, respectively. Surprisingly, HLS tools can yield less efficient solutions than processor-based approaches in some cases.

Constructing Bloom filters by reconfigurable means for solving information security tasks

Recently, the string matching task became a performance bottleneck in network intrusion detection, anti-virus, anti-worms and other signature-based information security systems. Unlike the firewall, NIDS examines not only packet headers, but also the packet bodies, that is, performs the deep packet inspection (DPI). The multi-pattern string matching task is a specific type of string matching functionality performed in DPI systems to search an input stream for a set of patterns rather than a single pattern. Due to rising traffic rates, increasing number and sophistication of attacks and the collapse of Moore's law for sequential processing, traditional software solutions can no longer meet the high requirements of today’s security challenges. Therefore, hardware approaches are proposed to accelerate pattern matching. Combining the flexibility of software and the near-ASIC performance, reconfigurable hardware devices based on Field Programmable Gate Arrays (FPGA) have become increasingly popular for this purpose. There are three main approaches to fulfill the computation-intensive multi-pattern string matching task using FPGA. The techniques (and underlying technologies) of these approaches are: content addressable memory (based on digital comparators), Bloom filter (based on hash-functions) and Aho-Corasick Algorithm (based on finite automata). This article is devoted to the investigation of the second approach - Bloom filter. The features (advantages and disadvantages) of this approach in terms of resource costs, speed/throughput parameters, as well as scaling parameters are explored. The basic scheme and its modifications are considered. The performance characteristics, problems and challenges of implementing this approach on reconfigurable accelerators as well as ways to overcome them are analyzed. The obtained results allow improving the technical parameters when designing pattern matching modules, which are speed-critical components of the signature-based information protection systems hardware. The knowledge obtained in this study allows developers to create more effective reconfigurable means for information security.

Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware

There is an increasing concern about transient errors in deep submicron processor architectures. Software-only error detection approaches that exploit program invariants for silent error detection incur large execution overheads and are unreliable as state can be corrupted after invariant checkpoints. In this article, we explore the use of configurable hardware structures for the continuous evaluation of high-level program invariants at the assembly level. We evaluate the resource requirements and performance of the proposed predicate-evaluation hardware structures when integrated with a 32-bit MIPS soft core on a contemporary reconfigurable hardware device. The results, for a small set of kernel codes, reveal that these hardware structures require a very small number of hardware resources with negligible impact on the processor core that they are integrated in. Moreover, the amount of resources is fairly insensitive to the complexity of the invariants, thus making the proposed structures an attractive alternative to software-only predicate checking.

LayeredTrees: Most Specific Prefix-Based Pipelined Design for On-Chip IP Address Lookups

Multibit trie-based pipelines for IP lookups have been demonstrated to be able to achieve the throughput of over 100 Gbps. However, it is hard to store the entire multibit trie into the on-chip memory of reconfigurable hardware devices. Thus, their performance is limited by the speed of off-chip memory. In this paper, we propose a new pipeline design called LayeredTrees that overcomes the shortcomings of the multibit trie-based pipelines. LayeredTrees pipelines the multi-layered multiway balanced prefix trees based on the concept of most specific prefixes. LayeredTrees is optimized to fit the entire routing table into the on-chip memory of reconfigurable hardware devices. No prefix duplication is needed and each ${\mbi {W}}$ -bit prefix is encoded in a (${\mbi {W}} + {\bf 1}$ )-bit format to save memory. Assume the minimal packet size is 40 bytes. Our experimental results on Virtex-6 XC6VSX315T FPGA chip show that the throughputs of 33.6 and 120.8 Gbps can be achieved by the proposed single search engine and multiple search engines running in parallel, respectively. Furthermore, the impact of update operations on the search performance is minimal. With the same FPGA device, an IPv6 routing table of 290,503 distinct entries can also be supported.

English

This paper presents the virtual environment implementation for project simulation and conception of supervision and control systems for mobile robots, which are capable of operating and adapting in different environments and conditions. The purpose of this virtual system is to facilitate the development of embedded architecture systems, emphasizing the implementation of tools that allow the simulation of the kinematic conditions, dynamic and control, with real time monitoring of all important system points. To accomplish this, open control architecture is proposed, integrating the two main techniques of robotic control implementation in the hardware level: systems microprocessors and reconfigurable hardware devices. The utilization of a hierarchic and open architecture, distributing the diverse actions of control in increasing levels of complexity, the use of resources of reconfigurable computation are made in a virtual simulator for mobile robots.

Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware

Cryptanalysis, i.e., the study of methods for breaking cryptographic algorithms, can greatly benefit from hardware acceleration as a key aspect enabling high-performance attacks. This work investigates the new opportunities inherently provided by a particular class of hardware technologies, i.e., reconfigurable hardware devices, addressing the cryptanalysis of the SHA-1 hash function as a case study. We show how hardware reconfiguration enables some unexplored approaches such as algorithm and architecture exploration, as well as on-the-fly system specialization relying on hardware programmability. We also identify some new cryptanalysis methods, including two novel techniques for SHA-1 cryptanalysis called interbit constraints and constraint relaxation. Relying on the proposed approaches, we designed an FPGA-based platform targeting 71- and 75-round versions of SHA-1. Under the same cost budget, the estimated times for a collision achieved by the platform are at least one order of magnitude lower than other solutions based on high-end supercomputing facilities, reaching the highest performance/cost ratio for SHA-1 collision search and providing a striking confirmation of the impact of hardware reconfigurability.

A Reconfigurable Hardware Platform for Secure and Efficient Malware Collection in Next-Generation High-Speed Networks

With the growing diversity of malware, researchers must be able to quickly collect many representative samples for study. This can be done, e.g., by using honeypots. As an alternative to software-based honeypots, we propose a singlechip honeypot appliance that is entirely hardware-based and thus significantly more resilient against compromising attacks. Additionally, it can easily keep up with network speeds of 10+ Gb/s and emulate thousands of vulnerable hosts. As base technology, we employ reconfigurable hardware devices whose functionality is not fixed by the manufacturing process. Furthermore, a special technology available in modern reconfigurable devices allows to alter part of the functionality even during operation and will be used to create a hardware virtualization layer. Beyond the technical aspects, we present improvements to the platform, aiming to simplify management and updates. To this end, we introduce the domain-specific language VEDL, which can be used to describe the honeypot behavior in a high-level manner by security experts not proficient in hardware design.

A review on several methods for fast generation of digital Fresnel holograms

Computer generated holography (CGH) is technology for generating holograms of synthetic, three dimensional (3D) objects which may not exist in the physical world. The process, however, requires heavy amount of computation as the resolution of a hologram is significantly higher than that of a typical optical image. This paper reviews four modern techniques for fast generation of digital Fresnel holograms which are important in the development of holographic video systems. The methods that will be described include the virtual window, sub-line, wavefront recording plane (WRP), and the interpolative WRP schemes. These works share the common objective to generate digital Fresnel hologram at a speed that is close to the video frame rate, and with complexity which is realizable with affordable computing and reconfigurable hardware devices. The author will present the principles and realization of these works, as well as some potential area of research in digital holography.

Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.

A Survey on the Application of FPGAs for Network Infrastructure Security

Given the rapid evolution of attack methods and toolkits, software-based solutions to secure the network infrastructure have become overburdened. The performance gap between the execution speed of security software and the amount of data to be processed is ever widening. A common solution to close this performance gap is through hardware implementation of security functions. Possessing the flexibility of software and high parallelism of hardware, reconfigurable hardware devices, such as Field Programmable Gate Arrays (FPGAs), have become increasingly popular for this purpose. FPGAs support the performance demands of security operations as well as enable architectural and algorithm innovations in the future. This paper presents a survey of the state-of-art in FPGA-based implementations that have been used in the network infrastructure security area, categorizing currently existing diverse implementations. Combining brief descriptions with intensive case-studies, we hope this survey will inspire more active research in this area.

MOBILE ROBOT NAVIGATION CONTROL DESIGN USING VIRTUAL SIMULATOR WITH RAPID PROTOTYPING

This paper presents the virtual environment implementation for simulation and design conception of supervision and control systems for mobile robots, that are capable to operate and adapt in different environments and conditions. The purpose of this virtual system is to facilitate the development of embedded architecture systems, emphasizing the implementation of tools that allow the simulation of the kinematic conditions, dynamic and control, with monitoring in real time of all important system points. For this, an open control architecture is proposed, integrating the two main techniques of robotic control implementation in the hardware level: systems microprocessors and reconfigurable hardware devices. The implemented simulator system is composed of a trajectory generating module, a kinematic and dynamic simulator module, and an analysis module of results and errors. All the kinematic and dynamic results obtained during the simulation can be evaluated and visualized in graphs and table formats in the results analysis module, allowing the improvement of the system, minimizing the errors with the necessary adjustments and optimization. For controller implementation in the embedded system, it uses the rapid prototyping which is the technology that allows in set, with the virtual simulation environment, the development of a controller project for mobile robots. The validation and tests had been accomplished with nonholonomic mobile robot models with differential transmission.

Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems

Operating systems for reconfigurable devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a reconfigurable hardware device (FPGA). In this work, we consider real-time systems subject to dynamic workloads and whose tasks can be computationally intensive. We introduce a novel resource allocation scheme and an online admission control test that achieve high performance and flexibility; in addition, runtime reconfiguration is used to maximize the number of admitted real-time tasks. Moreover, in detail, we first discuss a 1D system architecture and its prototype for a Xilinx Virtex-4 FPGA; then, we concentrate on the online admission control problem. Online task allocation and migration between the CPU and the reconfigurable device are discussed and sufficient feasibility tests are derived for both the commonly used slotted and 1D area models. Finally, the effectiveness of our admission control and relocation strategy is shown through a series of synthetic simulations.

Model-based engineering for change-tolerant systems

Developing and evolving today’s systems are often stymied by the sheer size and complexity of the capabilities being developed and integrated. At one end of the spectrum, we have sophisticated agent-based software with hundreds of thousands of collaborating nodes. These require modeling abstractions relevant to their complex workflow tasks as well as predictable transforms and mappings for the requisite elaborations and refinements that must be accomplished in composing these systems. At the other end of the spectrum, we have ever-increasing capabilities of reconfigurable hardware devices such as field-programmable gate arrays to support the emerging adaptability and flexibility needs of these systems. From a model-based engineering perspective, these challenges are very similar; both must move their abstraction and reuse levels up to meet growing productivity and quality objectives. Model-based engineering and software system variants such as the model-driven architecture (MDA) are increasingly being applied to systems development as the engineering community recognizes the benefits of managing complexity, separating key concerns, and automating transformations from high-level abstract requirements down through the implementation. However, there are challenges when it comes to establishing the correct boundaries for change-tolerant parts of the system. Capabilities engineering (CE) is a promising approach for defining long-lived components of a system to ensure some sense of change tolerance. For innovative initiatives such as the National Aeronautics and Space Administration (NASA)’s autonomous nanotechology swarms (ANTS), the development and subsequent evolution of such systems are of considerable importance as their missions involve complex, collaborative behaviors across distributed, reconfigurable satellites. In this paper, we investigate the intersection of these two technologies as they support the development of complex, change-tolerant systems. We present an effective approach for bounding computationally independent models so that, as they transition to the architecture, capabilities-based groupings of components are relevant to the change-tolerant properties that must convey in the design solution space. The model-based engineering approach is validated via a fully functional prototype and verified by generating nontrivial multiagent systems and reusing components in subsequent systems. We build off of this research completed on the collaborative agent architecture, discuss the CE approach for the transition to architecture, and then examine how this will be applied in the reconfigurable computing community with the new National Science Foundation Center for High-Performance Reconfigurable Computing. Based on this work and extrapolating from similar efforts, the model-based approach shows promise to reduce the complexities of software evolution and increase productivity—particularly as the model libraries are populated with canonical components.

Analysis and Detection Of Errors In Implementation Of SHA-512 Algorithms On FPGAs

The Secure Hash Algorithm SHA-512 is a dedicated cryptographic hash function widely considered for use in data integrity assurance and data origin authentication security services. Reconfigurable hardware devices such as Field Programmable Gate Arrays (FPGAs) offer a flexible and easily upgradeable platform for implementation of cryptographic hash functions. Owing to the iterative structure of SHA-512, even a single transient error at any stage of the hash value computation will result in large number of errors in the final hash value. Hence, detection of errors becomes a key design issue. In this paper, we present a detailed analysis of the propagation of errors to the output in the hardware implementation of SHA-512. Included in this analysis are single, transient as well as permanent faults that may appear at any stage of the hash value computation. We then propose an error detection scheme based on parity codes and hardware redundancy. We report the performance metrics such as area, memory, and throughput for the implementation of SHA-512 with error detection capability on an FPGA of ALTERA. We achieved 100% fault coverage in the case of single faults with an area overhead of 21% and with a reduced throughput of 11.6% with the error detection circuit.

A NOVEL APPROACH FOR IMPLEMENTING RC4 STREAM CIPHER ALGORITHM

The implementation of cryptographic algorithms on reconfigurable hardware devices based on Field Programmable Gate Arrays (FPGA) devices is highly attractive. They can run faster than software implementations while preserving the physical security of hardware solutions. Meanwhile, they maintain the flexibility obtained by using those software solutions [1]. In this work, a proposed hardware implementation of RC4 algorithm on field programmable gate arrays (FPGAs) is introduced. The design was described using the hardware description language VHDL (Very high speed integrated circuit hardware description language). The design was implemented on devices from XILINX and we achieved speeds of up to 280 Mbits/s.

Hardware Acceleration for Finite-Element Electromagnetics: Efficient Sparse Matrix Floating-Point Computations With FPGAs

Custom hardware acceleration of electromagnetics computation leverages favorable industry trends, which indicate reconfigurable hardware devices such as field-programmable gate arrays (FPGAs) may soon outperform general-purpose CPUs. We present a new striping method for efficient sparse matrix-vector multiplication implemented in a deeply pipelined FPGA design. The effectiveness of the new method is illustrated for a representative set of finite-element matrices computed on our highly scalable and fully pipelined FPGA-based implementation