Optoelectronic Integrated Circuit Receiver Research Articles

Low‐power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal–oxide semiconductor technology

The authors present a low-power 850 nm Si optoelectronic integrated circuit (OEIC) receiver fabricated in standard 65 nm complementary metal–oxide semiconductor (CMOS) technology. They analyse power consumption of previously reported CMOS OEIC receivers and determine the authors receiver architecture for low-power operation. Their OEIC receiver consists of a CMOS-compatible avalanche photodetector and electronic circuits that include an inverter-based transimpedance amplifier, a tunable equaliser and a post amplifier. With the fabricated OEIC receiver, they successfully demonstrate 8 Gb/s operation with a bit-error rate <10−12 at incident optical power of −4.5 dBm. Their OEIC receiver consumes 5 mW with 1.2 V supply voltage. To the best of their knowledge, their OEIC receiver achieves the lowest energy efficiency among 850 nm CMOS OEIC receivers.

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

An integrated 125-Gb/s optoelectronic receiver with a silicon avalanche photodetectorin standard SiGe BiCMOS technology

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

10-Gb/s 850-nm CMOS OEIC Receiver With a Silicon Avalanche Photodetector

We present a 10-Gb/s optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.13-μm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. The OEIC receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD), a transimpedance amplifier (TIA), an offset cancellation network, a variable equalizer (EQ), a limiting amplifier (LA), and an output buffer. The CMOS-APD provides high responsivity as well as large photodetection bandwidth. The TIA is composed of two-stage differential amplifiers with high feedback resistance of 4 kΩ. The EQ compensates high-frequency loss by controlling the boosting gain with a capacitor array. The LA consists of five-stage gain cells with active feedback and negative capacitance to achieve broadband performance. With the OEIC receiver, we successfully demonstrate transmission of 10-Gb/s optical data at 850 nm with a bit error rate of 10-12 at the incident optical power of -4 dBm. The OEIC receiver has the core chip area of about 0.26 mm2 and consumes about 66.8 mW.

InAlAs/InAs/InGaAs pseudomorphic high electron mobility transistors exhibiting ultra‐fast optical response

AbstractHigh electron mobility transistors with a pseudomorphically strained InAs channel (InAs‐PHEMTs) have superior electron‐transport properties and high electron density, which are due to a large conduction‐band discontinuity. In this work, we demonstrate that InAs‐PHEMTs have an additional property: they exhibit an ultra‐fast optical response with a time‐constant of 3.5 × 10–11 s. By irradiating the optical signal onto the InAs‐PHEMTs, hole‐electron pairs are created in the channel layer. Holes accumulated in the source region of the channel layer recombine immediately with 2DEG due to an Auger recombination mechanism. Holes generated in the region outside the gate also recombine immediately with the 2DEG due to the Auger recombination mechanism before they drift or diffuse toward the gate region. This is why the optical response time of an InAs‐PHEMT is extremely small and it is restricted by the time for holes to transit across the gate region. A circuit incorporating an InAs‐PHEMT as a transistor and an InAlAs/InAs/InGaAs MSM photodiode that has the same structure as an InAs‐PHEMT as an optical detector has the potential to be applied as an ultra‐fast receiver optoelectronic integrated circuit. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Design and Analysis of a 20 Gbps Metal-Insulator-Field Effect Transistor Photoreceiver for the OptoElectronic Integrated Circuit Receiver Applications

High-speed photoreceivers are important components for future high-bit rate communication systems. The use of a monolithical integration of photodetector and amplifier avoids loss making interconnections and enables high-speed performance, small size and cost-saving high frequency packaging. Particularly with respect to a commercial use, the degree of reproducibility and reliability has to be very high. The elimination of process uncertainties is indispensable. Hence, in our photoreceiver development, a photoreceiver based on optically gated metal-insulator-field effect transistor (MISFET) has been proposed to perform both the functions as photodetector and preamplifier. For future long-haul communication systems operate at bitrates of 40 Gbit/s and for broad-band mobile access systems using 38-GHz or 60-GHz carrier frequencies, ultrafast photoreceivers have to be provided. Therefore, an integration concept for InP-based optoelectronic monolithic integrated circuits for the 1.55-μm wavelength regime is studied, which allows independent optimization of the constituting devices. The device can be considered as a nano device as all the device parameters are in nanometer range. The design and characterization of a novel high sensitivity photo MISFET based OEIC receiver for using in 1.55 μm applications has been carried out based on 3D numerical modeling and device simulation. The bit error rate (BER) and sensitivity of the photoreceiver have also been computed. The proposed OEIC receiver has a transimpedance gain of 71.35 dB and sensitivity at 20 Gb/s for a BER of 10 -9 has been found to be -66 dBm. This seems to be a promising technology which will greatly simplify the design of optoelectronic integrated circuits including OEIC repeaters.

80-Gb/s InP-based waveguide-integrated photoreceiver

A waveguide-integrated photoreceiver, comprising a waveguide-integrated photodiode and a distributed amplifier, is presented. Its optical to electrical conversion capability for nonreturn to zero modulated data rates up to 80 Gb/s is demonstrated. The receiver optoelectronic integrated circuit was packaged into a pig-tailed module with a 1 mm connector output.

2.5 Gbit/s silicon receiver OEIC with large diameter photodiode

A silicon receiver optoelectronic integrated circuit (OEIC) in 0.6 µm BiCMOS technology is presented. The OEIC achieves with a 300 µm-diameter pin photodiode a sensitivity of −20.1 dBm at a data rate of 2.5 Gbit/s and at a pseudorandom bit sequence of 231−1 with a bit error rate of 10−9.

Design and fabrication of 60-Gb/s InP-based monolithic photoreceiver OEICs and modules

An InP-based photoreceiver comprising a waveguide-integrated photodiode and a traveling-wave amplifier is presented, which allows dc-coupled interfacing to subsequent electronics without a bias-T. Getting rid of the bias-T provides cost savings of the receiver operation and improves the available bandwidth, gain, and gain flatness. The redesigned receiver optoelectronic integrated circuit was fully packaged into a pigtailed module with a coaxial 1.85-mm connector. Its optoelectronic conversion capability for nonreturn-to-zero modulated data rates up to 66 Gb/s is shown.

43 Gbit/s, 200 km unrepeatered transmission experiment using high-sensitivity digital OEIC receiver module

The first transmission results using a monolithic digital optoelectronic integrated circuit (OEIC), which consists of a uni-travelling-carrier photodiode and an InP high electron mobility transistor decision circuit, are presented. High receiver sensitivity of −30.2 dBm was obtained at the bit rate of 43 Gbit/s with 150 km dispersion-shifted fibre transmission. It is confirmed that the transmission distance can be extended to over 200 km by employing forward error correction code.

Gas source molecular beam epitaxy of InP-based heterostructures for OEIC applications

Abstract We report in this paper on high quality InGaAs/InAlAs/InP heterostructure and its application to optoelectronic integrated circuit (OEIC) structures grown by gas source molecular beam epitaxy. Electron mobilities of the modulation doped heterostructure are as high as 1.1×10 4 cm 2 / V s at room temperature and 6.4×10 4 cm 2 / V s at liquid nitrogen temperature. An OEIC structure consisting of high electron mobility transistors (HEMT) and a metal semiconductor metal photo-detector (MSM-PD) was then achieved within a single growth run. An etch stop layer was inserted between the MSM and HEMT structure in order to ease the device process by employing the excellent etch selectivity between InP and InAlAs. The MSM photo-detector, with an active area of 80×80 μm 2 , has the responsivity of 0.62 A/W. The DC transconductance of an InGaAs/InAlAs HEMT with 1 μm gate length is 305 mS/mm with threshold voltage of −1.4 V. High frequency measurements show that the −3 dB bandwidth of the OEIC receiver is 1.0 GHz indicating that it can operate at a transmitting rate of 1.3 Gb/s.

GSMBE growth of InP-based MSM/HEMT OEIC structures

An optoelectronic integrated circuit (OEIC) structure consisting of high electron mobility transistors (HEMT) and a metal semiconductor metal photo detector (MSM-PD) was achieved by gas source molecular beam epitaxy with one growth run. The whole structure consists of an InGaAs/InAlAs MSM PD and InGaAs/InAlAs HEMT preamplifier circuits. An etch stop layer, InP, was inserted between the MSM and HEMT structure, which makes the device process much easier because of the good etch selectivity between InP and InAlAs. The MSM photo-detector, with an active area of 80×80 μm 2, has the responsivity of 0.62 A/W. The DC transconductance of an InGaAs/InAlAs HEMT with 1 m gate length is 305 mS/mm with threshold voltage of –1.4 V. High frequency measurements show that the -3 dB bandwidth of the OEIC receiver is 1.0 GHz indicating that it can operate at a transmitting rate of 1.3 Gb/s.

Ultrafast monolithic receiver OEIC composed of multimode waveguide p-i-n photodiode and HEMT distributed amplifier

A multimode waveguide p-i-n photodiode (WGPD) and a distributed baseband amplifier consisting of high-electron mobility transistors (HEMTs) were monolithically integrated on InP substrate using a stacked layer structure for both components. The multimode WGPD has a 3-dB bandwidth of 49 GHz. The distributed baseband amplifier has a 3-dB bandwidth of 47 GHz, though its 0.5-/spl mu/m gate-length HEMTs have modest cutoff frequencies f/sub T//f/sub max/ of 47/100 GHz. The receiver optoelectronic integrated circuit has a bandwidth of 46.5 GHz. It was packaged into a fiber-pig-tailed module, and the WGPD in the module has a high responsivity of 0.62 A/W for 1.55-/spl mu/m wavelength. The module achieves a sensitivity of -22.7 dBm at 40 Gb/s and exhibits a clear eye-opening at 50 Gb/s.

Ultrawide-band/high-frequency photodetectors

The two main trends in the progress of ultrawide-band/high-frequency photodetectors (PD's), improving the bandwidth-efficiency product and obtaining a high saturation current, are reviewed. With respect to achieving large bandwidth-efficiency, the limiting factors and potentials of edge-coupled (waveguide, waveguide-fed, traveling-wave, periodic-traveling-wave), resonant-cavity, and refracting-facet photodiodes, as well as the avalanche photodiode are discussed. Regarding high-saturation current, the author estimated how much the space-charge effect limits the saturation current and two ways to reduce the space-charge effect are outlined. One way is to distribute the photocarriers along the edge-coupled PD's and the other is to increase the carrier velocity using a uni-traveling carrier structure. The waveguide-photodiode-based technologies that we have developed are also presented; namely the design and fabrication of a 100-GHz waveguide photodiode (WGPD), uni-traveling carrier WGPD, 60-GHz packaging, and a 20-GHz large-core WGPD for planar lightwave circuit integration. A 50-Gb/s receiver opto-electronic integrated circuit technology based on the WGPD is also presented.

A proposed OEIC receiver using MESFET photodetector

An optical receiver configuration based on the concept of using a single optically gated metal-semiconductor-fieid-effect transistor (MESFET) to perform the function of a photodetector and preamplifier has been introduced. The proposed optoelectronic integrated circuit (OEIC) receiver has been analyzed theoretically. A simplified noise model of the receiver has also been developed. Results have been presented for an OEIC receiver based on InGaAs MESFET supposed to be fabricated with matured InGaAs-InP MMIC technology. Theoretical results based on a simplistic noise model reveal that the proposed OEIC receiver has superior performance characteristics over the existing optical receivers.

46.5-GHz-bandwidth monolithic receiver OEIC consisting of a waveguide p-i-n photodiode and a HEMT distributed amplifier

A large bandwidth monolithically integrated photoreceiver for 1.5-/spl mu/m wavelength operation was fabricated using a stacked structure of waveguide p-i-n photodiode layers and InAlAs-InGaAs high-electron mobility transistor (HEMT) layers grown using a single-step metal-organic vapor-phase epitaxy. The monolithic receiver optoelectronic integrated circuit (OEIC) consists of a waveguide p-i-n photodiode with a high responsivity of 0.5 A/W and a HEMT distributed amplifier. It has a bandwidth of 46.5 GHz, which is the largest yet reported for a long-wavelength receiver OEIC, and exhibits a clear eye opening at 40 Gb/s. This excellent performance is very attractive for use in high-speed optical transmission systems and millimeter-wave fiber-radio systems.

OEIC technologies for high-speed optical interconnection system

As the level of integration and the power of computation increase, methods of interconnecting computational elements attract more attention and the total system performance is bottlenecked by the problems associated with electrical interconnections. Optical interconnections have advantages of practically unlimited bandwidth and absence of crosstalk. To utilize such merits of optical interconnections, a large number of low-cost high-performance optoelectronic integrated circuits (OEICs) are needed. This paper focuses on monolithically integrated receiver OEICs that consist of InP/InGaAs p-i-n photodiodes and fully ion-implanted InP junction field-effect transistors (JFETs). In the formation of shallow InP p-n junctions we use a co-implantation technique in which we implant a group V element together with Be, a dopant, and take advantage of damage and stoichiometry effects. We fabricate a p-i-n/JFET amplifier receiver front-end circuit and a receiver 2×2 crosspoint switch circuit using this technique. We also develop bandwidth enhancement designs using inductive peaking and cascoding. Finally, we demonstrate a single-channel, free-space optical interconnection system with a bandwidth of 1.5 GHz and an interconnection length of 50 cm.

Designing optoelectronic integrated circuit (OEIC) receivers for high sensitivity and maximally flat frequency response

This paper examines previously overlooked, but a highly effective, optimization approach to designing transimpedance OEIC receivers based on heterojunction bipolar and field-effect transistors (HBT's & HFET's) with high sensitivity and maximally flat frequency response. It is shown that the 3-dB bandwidth of amplifiers involving single-transistor common-emitter (CE) and common-source (CS) input stages, and the corresponding cascoded input stages can be universally expressed as f/sub 3-dB//spl cong/1/2/spl pi//spl radic/(/spl tau/'(c/sub /spl mu//+c/sub L/)R/sub f/), where /spl tau/' is the effective transit time of the transistor including the effect of the photodetectors capacitance, c/sub /spl mu// is the feedback capacitance of the transistor, c/sub L/ is the capacitance in parallel to the collector or drain effective load conductance (g~/sub L/), and R/sub f/ is the feedback resistance of the amplifier that ensures a much greater than unity loop-gain. The gain-bandwidth product can also be universally expressed as R/sub f//spl times/f/sub 3-dB//spl cong/g/sub m///spl radic/2/spl pi/g~/sub L/c/sub in/, where gm is the transconductance of the transistor and c/sub in/ is the total capacitance appearing at the input of the respective amplifier. For the single-transistor CE and CS input stages the dependence of the optimum values of R/sub f/ on g~/sub L/ can be expressed as R/sub f/=2/spl tau/'(c/sub /spl mu//+c/sub L/)/(g~L/spl tau/'+c/sub /spl mu//)/sup 2/, whereas for the corresponding cascoded input stages the same expression also applies but with c/sub /spl mu//=0 in the denominator. Since designing high sensitivity OEIC receivers require high values of R/sub f/ and correspondingly low values of g~/sub L/, thus it follows that amplifying transistors must be operated at the lowest possible current but without degradation of their high frequency performance. A low-value of the base or gate bias current also ensures a low level of shot noise thus further enhancing the sensitivity. Because of a low g/sub m/ to drain current ratio in HFET's, receivers involving only the cascoded input stage, and not the single-transistor CS input stage, are capable of providing both high sensitivity and high bandwidth. In contrast, receivers based on HBT's involving either the simple CE input stage or the cascoded input stage are capable of providing both high sensitivity and high bandwidth. Design examples, using HBT's and HFET's with intrinsic unity current gain frequency f/sub /spl tau//=160 GHz and very low-capacitance msm photodetectors, indicate that high-speed receivers can be realized with bandwidth f/sub 3-dB//spl cong/20 GHz, and sensitivity as high as -28.7 dBm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fabrication of pin/hemt receiver oeics for Gb/s lightwave systems on three‐inch diameter inp substrate

AbstractReceiver optoelectronic integrated circuits (OEICs) have been successfully designed on a three‐inch diameter InP substrate. Epitaxial layers grown by OMVPE on three‐inch diameter InP substrates showed good uniformity of electrical and optical properties. By using the epitaxial layers, transimpedance‐type receiver OEICs were fabricated. the receiver OEICs over a three‐inch diameter InP substrate showed an average bandwidth of 2.78 GHz with a standard deviation of 280 MHz. the receiver also exhibited a transimpedance of 61.1 dB and a sensitivity of ‐24.9 dBm for 2.4 Gb/s input signals. These results indicate that the receiver OEICs designed on a three‐inch diameter InP substrate are ready for practical use in Gb/s lightwave systems.

Long-Wavelength Receiver Optoelectronic Integrated Circuit on 3-Inch-Diameter GaAs Substrate Grown by InP-on-GaAs Heteroepitaxy

A monolithic long-wavelength receiver optoelectronic integrated circuit (OEIC), which integrates an InGaAs PIN-photodiode (PD) and a GaAs field-effect transistor (FET), has been successfully fabricated on a 3-inch-diameter GaAs substrate using InP-on-GaAs heteroepitaxy, by metalorganic chemical vapor deposition (MOCVD) and conventional GaAs-IC process technology. The epitaxial quality of the PD layer has been improved by use of a low-temperature-grown buffer layer, thermal cyclic annealing and an InGaAs/InP strained-layer superlattice. The integrated PD has low dark current of 10 nA at -5 V bias voltage, and exhibited stable operation at 175°C. The fabricated receiver OEIC has 1.4 GHz bandwidth and sensitivity of -28.1 dBm at the transmission rate of 622 Mb/s with bit error rate of 10-9, which is applicable to practical subscriber optical communication systems.