Real-time computer systems must meet specific deadlines in generating their outputs. As a result, all components of the real-time system must have predictable performance so that hardware resources can be effectively scheduled, ensuring that all deadlines are met. Cache memories, by their nature, have unpredictable access times which result in execution times that may vary significantly for multiple runs of the same program. Varying program-execution times complicate scheduling activities, which may result in missed deadlines. For this reason, cache memories are generally not used in hard real-time systems, and the substantial performance advantages they offer are therefore not realized. This paper describes research whose goal is to make cache memory predictable as seen by the processor, so it can be used in hard real-time systems. This predictability is a result of improving the cache's “worst-case” effective memory-access time, which allows the processor to operate more effficiently thus increasing its ability to meet hard real-time deadlines. By reducing the upper limit execution time (by lowering the worst-case effective memory-access time) performance will increase in a predictable manner without any risk of missing real-time deadlines.
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