Real Chip Research Articles

Analysis, design, and implementation of a simple switched‐coupled‐inductor boost DC‐AC inverter

AbstractThis paper presents a simple switched‐coupled‐inductor inverter (SCII), as well as completes the relevant analysis, design, and implementation, for efforts aimed at achieving boost DC‐AC inversion and strengthening closed‐loop regulation. In structure, the power‐part circuit consists of switched‐coupled‐inductor booster and half‐bridge DC‐link inverter, connected in cascade between supply and output to work for the AC output range as (n: turn ratio, : ratio cycle). As adopting , , , the output can be lifted to (i.e., DC 24 V to AC 100 Vrms, 60 Hz). In control, the control‐part circuit consists of phase generator and sinusoidal pulse‐width‐modulation (SPWM) block and generates driver signals of switches according to the feedback signal of for the needs of timing sequence (to different topologies) and output regulation/robustness (to various desired output/loading variation). The related chip circuit is designed via pre‐/post‐layout Cadence procedure and then practically is implemented on a real chip (D35‐106B‐E0027, TSMC 0.35 μm, 1500 × 1500 μm2, 3.3 V, 2.146 mW, 100 kHz max., 18S/B) via the assistance of TSMC and Chip Implementation Center (CIC). In theory, some relevant analysis and design will be discussed, such as modeling, conversion ratio, power efficiency, parameter selection, system stability, and control design. In implementation, several simulation/experiment cases via testing on the SCII's prototype circuit are illustrated to examine the efficacy of the proposed scheme.

Universal strategy study of applying passive metasurfaces to an intra-DC wireless-optical interconnection

Free-space optical (FSO) communication can reduce the routing complexity of data center networks (DCNs), not only ensuring high-capacity optical switching, but also owning similar flexibility to the wireless connectivity. Presently, mainstream wireless-optical switching units (WOSUs) have adopted serial beam control for unicasting. As a two-dimensional planar structure composed of meta-atoms with special electromagnetic properties arranged in a certain way, a passive metasurface (PMF) has strong parallel beam regulating capability. In this paper, we propose a wireless-optical intra-DC interconnection scheme based on PMFs. Through a real PMF chip, by adjusting the polarization of an incident beam, the power distribution between normal and abnormal reflected beams can be controlled. When both reflected beams are assigned with power, we obtain a pair of beams reflected in parallel, thus simultaneously communicating with two racks. In fact, we can perform 1-to-N (N≥2) multicast by using cascaded PMFs, and 1-to-N means that each source rack can communicate with N destination racks, i.e., a wide communication coverage range. However, the cascaded PMFs may result in huge chip costs and high accumulated power loss. In this paper, we only demonstrate the 1-to-2 communication ability of our PMFs, so the communication coverage may be still limited. Hence, by introducing electrostatic drive to control the PMF rotation, each source rack can achieve a wider communication coverage range than before. As a result, all racks within the coverage range have the ability to establish communication links with the source rack. To this end, we also design a neural network to mimic the PMF rotation, further improving the communication capability between racks. We then propose a DCN-topology reconfiguration algorithm supporting the coexistence of unicasting and multicasting, in order to make real-time decisions on the matching between FSO ports with minimized latency. Finally, we established a proof-of-concept prototype system to demonstrate the parallel beam control of our PMF. The test results show that the angle error is less than 0.1°, satisfying the accuracy requirements of WOSUs, and our PMF always has a good polarization response with the insertion loss of less than 2 dB under various azimuth angles or rotation planes.

Establishing the robustness of chip trade networks by dynamically considering topology and risk cascading propagation

Risk cascading propagation research mostly focuses on complex theoretical networks. Recently, the vulnerability of international chip supply has increased notably, and it is strategically important to explore how shortage risk affects the emergence dynamics of the real chip trade systems. This study abstracts the global chip trade relationship data for 2009–2021 into multiple asymmetrically weighted networks. Using macro-network and micro-node indicators, we explore the topological traits of international chip trade networks and their evolutionary laws. Accordingly, we propose risk cascading propagation models driven by node failure and edge restraint and further innovate to open up the research paradigm of focused-edge networks. Furthermore, a community infection-driven risk cascading propagation mechanism that incorporates community risk absorption capacity is introduced, considering both the propagation attenuation effects and the trade dependency degree. A multi-dimensional dynamic perspective reveals the hidden systemic risks in international chip trade. The main results are as follows: first, international chip trade networks are highly connected and cohesive, consistent with small-world characteristics. Second, the proportion of economies that collapse because of supply shortage risk shocks increases with the impact coefficient α/β\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha /\\beta$$\\end{document}. The dominant power in chip crisis propagation has shifted from Europe and America to Asia, and mainland China’s risk penetration capacity has enhanced significantly. Third, focused-edge networks conform to a multi-hub radiation pattern. Before the COVID-19 pandemic, the degree of control and spillover effects of chip supply shortages in hub economies on the international trade was increasing progressively. Fourth, an increase in absorption capacity λ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\lambda$$\\end{document} or attenuation factor γ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\gamma$$\\end{document} consistently leads to a decline in avalanche scale, with λ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\lambda$$\\end{document} exhibiting critical thresholds. These findings will help policymakers pursue efficient management strategies for chip trade, thereby improving supply stability and security.

Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips

The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130◦C and T = 25◦C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant.Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130◦C) compared to lower operating temperatures (T = 25◦C).

Efficient multipole representation for matter-wave optics

Technical optics with matter waves requires a universal description of three-dimensional traps, lenses, and complex matter-wave fields. In analogy to the two-dimensional Zernike expansion in beam optics, we present a three-dimensional multipole expansion for Bose-condensed matter waves and optical devices. We characterize real magnetic chip traps, optical dipole traps, and the complex matter-wave field in terms of spherical harmonics and radial Stringari polynomials. We illustrate this procedure for typical harmonic model potentials as well as real magnetic and optical dipole traps. Eventually, we use the multipole expansion to characterize the aberrations of a ballistically interacting expanding Bose–Einstein condensate in (3 + 1) dimensions. In particular, we find deviations from the quadratic phase ansatz in the popular scaling approximation. The scheme is data efficient by representing millions of complex amplitudes of a field on a Cartesian grid in terms of a low order multipole expansion without precision loss. This universal multipole description of aberrations can be used to optimize matter-wave optics setups, for example, in matter-wave interferometers.

An optimal selective maintenance policy for multi-state series production systems by considering environment impact

Series production systems are prevalent in the manufacturing industry. The productivity of these systems is influenced by various factors, including system conditions, on-site environment, maintenance planning, and others. Efforts to develop an effective maintenance plan that considers the on-site environment are crucial for maximizing net revenue over the system’s lifetime, which has practical significance. Against this backdrop, a selective maintenance model is constructed for a multi-state series production system over a finite time horizon. This model describes the operation and maintenance processes at any decision period and analyzes the impact of the on-site environment on system productivity. Subsequently, an optimal maintenance strategy is formulated with the goal of maximizing net revenue throughout the system’s lifetime. To efficiently solve this optimal strategy, a hybrid solution approach is developed by integrating a deterministic method with a heuristic method. Finally, a numerical example involving a real chip mounter system is presented to verify the developed maintenance strategy. This is followed by a comparative experiment to validate the performance of the hybrid solution approach. Additionally, sensitivity analysis is conducted to test the strategy’s robustness. The results from the numerical example, comparative experiment, and sensitivity analysis demonstrate that the developed strategy is effective and robust, and the hybrid approach is efficient.

The Impact of Information Presentation on Consumer Perceptions of Cricket-Containing Chocolate Chip Cookies

As a source of protein and other nutrients for a growing population, edible insect production offers environmental and sustainability advantages over traditional meat production. Although around 2 billion people consume insects worldwide, Western consumers are still reluctant to practice entomophagy, hindered largely by neophobia and negative emotions. In addition to sensory quality and safety, an informational component may be crucial to consumers’ decision making involving insect consumption. In this study, three different information types, namely text, image, and a tangible product, were used to convey information about chocolate chip cookies (CCCs) containing cricket flour. The nature of the information was related to the ingredient usage level (5%), the type of insect (cricket), nutritional values, sustainability benefits, packaging, celebrity endorsement, and/or visual appearance of an actual product. Consumers’ willingness to consume (WTC), acceptance, and purchase intent (PI) were measured in response to each informed condition. Once informed of the insect ingredient, all scores significantly (α = 0.05) dropped. The lowest WTC (1.97 ± 1.06, Text), acceptance (3.55 ± 2.23, Image), and PI (1.85 ± 1.05, Text) scores were found after identifying cricket as the insect ingredient. Compared to other informed conditions, the presentation of a real chocolate chip cookie containing insects achieved the highest scores on all affective scores (WTC: 3.4 ± 1.04, acceptance: 6.17 ± 1.89, PI: 3.07 ± 1.09). The greatest improvement in scores was observed after information about nutrition and sustainability benefits (based on ANOVA), which was more impactful for males than females (based on a t-test). Celebrity endorsement did not have a significant effect. The presentation of the actual CCC containing cricket flour (for visual observation only) significantly increased WTC, acceptance, and PI compared to presenting text and images alone. Acceptance, WTC, and certain information cues were significant predictors of PI for CCCs containing cricket flour.

The Interaction of Dietary Patterns and Genetic Variants on the Risk of Cardiovascular Diseases in Chinese Patients with Type 2 Diabetes.

Diabetes is an important risk factor for cardiovascular disease (CVD), which in turn is the most common and serious complication of diabetes. This study analyzes dietary patterns and single nucleotide polymorphisms (SNPs) in 543 diabetes patients with new-onset cardiovascular events and 461 diabetic patients without. SNPs are determined and analyzed using real time PCR and gene chip method. Factor analysis and logistic regression are used to determine dietary patterns and evaluate the level of associations and interaction effects, respectively. The legumes and edible fungi pattern and vegetable pattern show a significant negative correlation with complication risk. ADIPOQ rs37563 and legumes and edible fungi pattern have a significant interactive effect on disease, and patients with a high score of C polymorphism genotype (GC+CC) have a lower risk of disease. 5-10-Methylenetetrahydrofolate reductase (MTHFR) rs1801131 and vegetable pattern have a borderline interaction effect on disease, and those patients with TT genotype have a lower risk of disease. These findings provide new insights into the role of the interactive protection of dietary patterns and SNPs. And participants with specific alleles show a lower risk of cardiovascular complications.

From Brain Models to Robotic Embodied Cognition: How Does Biological Plausibility Inform Neuromorphic Systems?

We examine the challenging "marriage" between computational efficiency and biological plausibility-A crucial node in the domain of spiking neural networks at the intersection of neuroscience, artificial intelligence, and robotics. Through a transdisciplinary review, we retrace the historical and most recent constraining influences that these parallel fields have exerted on descriptive analysis of the brain, construction of predictive brain models, and ultimately, the embodiment of neural networks in an enacted robotic agent. We study models of Spiking Neural Networks (SNN) as the central means enabling autonomous and intelligent behaviors in biological systems. We then provide a critical comparison of the available hardware and software to emulate SNNs for investigating biological entities and their application on artificial systems. Neuromorphics is identified as a promising tool to embody SNNs in real physical systems and different neuromorphic chips are compared. The concepts required for describing SNNs are dissected and contextualized in the new no man's land between cognitive neuroscience and artificial intelligence. Although there are recent reviews on the application of neuromorphic computing in various modules of the guidance, navigation, and control of robotic systems, the focus of this paper is more on closing the cognition loop in SNN-embodied robotics. We argue that biologically viable spiking neuronal models used for electroencephalogram signals are excellent candidates for furthering our knowledge of the explainability of SNNs. We complete our survey by reviewing different robotic modules that can benefit from neuromorphic hardware, e.g., perception (with a focus on vision), localization, and cognition. We conclude that the tradeoff between symbolic computational power and biological plausibility of hardware can be best addressed by neuromorphics, whose presence in neurorobotics provides an accountable empirical testbench for investigating synthetic and natural embodied cognition. We argue this is where both theoretical and empirical future work should converge in multidisciplinary efforts involving neuroscience, artificial intelligence, and robotics.

Hot-Trim: Thermal and Reliability Management for Commercial Multicore Processors Considering Workload Dependent Hot Spots

This work proposes a new dynamic thermal and reliability management framework via task mapping and migration to improve thermal performance and reliability of commercial multi-core processors considering workload-dependent thermal hot spot stress. The new method is motivated by the observation that different workloads activate different spatial power and thermal hot spots within each core of processors. Existing run-time thermal management, which is based on on-chip location-fixed thermal sensor information, can lead to suboptimal management solutions as the temperatures provided by those sensors may not be the true hot spots. The new method, called Hot-Trim, utilizes a machine learning-based approach to characterize the power density hot spots across each core, then a new task mapping/migration scheme is developed based on the hot spot stresses. Compared to existing works, the new approach is the first to optimize VLSI reliabilities by exploring workload-dependent power hot spots. The advantages of the proposed method over the Linux baseline task mapping and the temperature-based mapping method are demonstrated and validated on real commercial chips. Experiments on a real Intel Core i7 quad-core processor executing PARSEC-3.0 and SPLASH-2 benchmarks show that, compared to the existing Linux scheduler, core and hot spot temperature can be lowered by 1.15 1.31∘C. In addition, Hot-Trim can improve the chip’s EM, NBTI and HCI related reliability by 30.2%, 7.0% and 31.1% respectively compared to Linux baseline without any performance degradation. Furthermore, it improves EM and HCI related reliability by 29.6% and 19.6% respectively, and at the same time even further reduces the temperature by half a degree compared to the conventional temperature-based mapping technique.

A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops

While the spin-transfer torque (STT) magnetic tunnel junction (MTJ) is a promising technique for enabling nonvolatile flip-flops (NVFFs) to perform power gating to reduce leakage power without any data losses, the large store energy (the energy to make a store operation) of MTJs needs to be addressed. The nonvolatile cool mega array series is an edge-oriented coarse-grained reconfigurable accelerator that implements an improved MTJ-based NVFF with a verify-and-retryable store method that should ideally reduce the store energy under the presence of the switching time variation originating from the stochastic nature of the MTJs. However, the energy reduction effect of the method has not been formulated or evaluated thoroughly enough to make the best use of the method in actual applications. In this study, we propose an analytical model to estimate the store energy in typical operational conditions under the assumption of switching time variations following the normal distributions based on the measurements of a real chip fabricated with a 40-nm perpendicular MTJ/CMOS hybrid process. In contrast to the tedious measurement on each different condition, the proposed model allows for an instantaneous determination of the best storing method for minimizing the store energy, with an energy reduction of up to 69% compared with a conventional one-time attempt storing method. This model is expected to be used for system-level energy simulations and, ultimately, for design explorations in pursuit of energy-optimized memory.

A chopper amplifier with a pseudo MOS resistor-based tunable bandwidth for EEG applications

PurposeThe purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.Design/methodology/approachThis paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.FindingsThe total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.Research limitations/implicationsAll kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.Practical implicationsThe proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.Originality/valueThe high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

Fenglin-I: An Open-Source Time-Sensitive Networking Chip Enabling Agile Customization

Time-Sensitive Networking (TSN) technology is experiencing diverse application requirements and forming a complicated standard system. It is extremely difficult to design a one-fits-all chip for all TSN applications. Therefore, application-driven TSN chip customization is inevitable. Generally, chip customization starts from a “clean-slate”. For complicated ASIC chips, that results in significant development overhead. Inspired by RISC-V chips, an open-source template will significantly reduce the customization complexity. Along this road, we propose an open-source TSN chip named Fenglin-I. Fenglin-I includes a high-level abstraction to build a relationship between application requirements and chip implementation, source code of a real chip named FastTSN to provide reference code for chip implementation, and software tools to facilitate chip verification. Based on Fenglin-I, we further propose a TSN chip customization method that provides step-by-step guidance about customizing TSN chips agilely. To verify the effectiveness of Fenglin-I and the proposed customization method, we use FPGA arrays to prototype and verify FastTSN. The results show that FastTSN achieves microsecond-level transmission jitter for unicast and multicast time-critical traffic. Additionally, we demonstrate two domain-specific TSN chip customization cases in which the customized chips reuse at least 84 <inline-formula><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> of FastTSN code while meeting their requirements.

머신 러닝 모델을 활용한 웨이퍼 불량 탐지 및 테스트 항목 효율화

Wafer testing is one of the key components of the semiconductor manufacturing process and aims to balance maximum production with the highest quality. However, there is a problem that it is difficult to preemptively respond to the changing environment due to the ultra-fine semiconductor process, the quality risk caused by the production of various products, and the lack of professional engineers. Therefore, in this work, we present a framework for determining the optimal set of wafer test items representing high defect wafer detection rates using machine learning models. The proposed framework applies an effective sampling methodology to solve category imbalances, mostly composed of good chips, and uses ensemble classification models and important feature selection methods to achieve high classification performance in a short time without direct wafer evaluation. We demonstrate the proposed methodology has a meaningful effectiveness on time reduction through classification accuracy and test item reduction using real DRAM chip datasets.

Self-adaptive cooling of chips with unevenly distributed high heat fluxes

• A self-adaptive chip cooling method for high heat fluxes is proposed. • Unevenly distributed high heat fluxes of up to 460 W/cm 2 are effectively removed. • The maximum surface temperature drop amounts to 22.6 K with reduced flow rates. • Coolant flow adapts to local heat fluxes and movable hotspots are cooled effectively. The heat load scenario of a real chip is unsteady and spatially variable and gives rise to regions of concentrated high power. Conventional liquid cooling techniques are always inadequate to tailor the flow distribution to the changing thermal environment and cool the resulting high-heat-flux regions effectively. In this work, the self-adaptive cooling for unevenly distributed high heat fluxes is proposed. It contains a matrix of microfluidic units with integrated thermal-sensitive hydrogel valves. The units are independently controlled and deliver the coolant to where it is needed. A numerical model is developed to investigate the flow and temperature distribution of the cooling unit. By introducing the self-adaptive mechanism, the near-wall flow is enhanced remarkably. Nonuniform heat fluxes of up to 460 W/cm 2 are effectively dissipated by means of the developed self-adaptive cooling method. The maximum surface temperature drop amounts to 22.6 K, meanwhile the total flow rate can be reduced by nearly an order of magnitude. The microfluidic unit array adapts to local heat fluxes by reconfiguring its internal flow-channel structure automatically and thus movable hotspots are elaborately cooled. The self-adaptive cooling scheme offers both effective and smart thermal management for modern electronic devices.

Experimental study on the quantum search algorithm over structured datasets using IBMQ experience

In this work, a quantum search algorithm over structured datasets is proposed. Subsequently, the algorithm is executed on a real chip quantum computer developed by IBM Quantum experience (IBMQ). QISKit, the software platform developed by IBM, is used for the implementation of this algorithm. Quantum interference, quantum superposition, and π phase shift of the quantum state are applied in the proposed search algorithm. It performs a π phase shift on the initial state and conducts a state elimination and amplitude amplification process to reach the 'search key' or 'solution key' from the given structured dataset. The proposed quantum algorithm is executed using the QISKit SDK local backend ‘local_qasm_simulator’, real chip 'ibmq_16_melbourne', 'ibmq_belem' and 'ibmqx4′ IBMQ. The results suggest that the real chipibmq_16_melbourne is more quantum error- or noise-prone than ibmq_belem and ibmqx4. The correctness, validation, and application using the proposed algorithm are demonstrated. The algorithm is very promising in terms of low quantum cost and fewer gate requirements. This implies that the proposed quantum search algorithm may be a compelling and pertinent choice in the Noisy Intermediate-Scale Quantum (NISQ) technology era.

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

During development of power Integrated Circuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{4}$ </tex-math></inline-formula> -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions - the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time - and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.

Design and analysis of coupled-inductor Cockcroft–Walton-switched-capacitor boost DC–AC inverter

ABSTRACT The objective of this study is to present a novel simple structure of coupled-inductor Cockcroft–Walton-switched-capacitor (CICWSC) inverter for DC–AC conversion/closed-loop regulation. In structure, the power part is contained by three units: coupled–inductor booster, Cockcroft–Walton-switched-capacitor doubler, and half-bridge DC-link, working together for providing the DC–AC gain range as (n: turn ratio, : ratio cycle). In control, for the time sequence (to different topologies) and output regulation/robustness (to various desired output/loading variation), the control part is made of phase generator and sinusoidal pulse-width-modulation (SPWM) block, and its chip internal circuit is designed through pre/post-layout procedure via CADENCE. By the assistance of Chip Design and Implementation Center (CIC) and TSMC, this control part is practically fabricated on a real chip (D35-104B-E0013, TSMC 0.35μm, 2P4M, 3.3V, 3.889mW). In analysis and design, the quantitative mathematical modeling of CICWSC is carefully derived, and the relevant system analysis/ design is also presented (e.g. steady-state response, conversion ratio, power efficiency, parameter selection, stability, and control design). In implementation, it contains several cases of simulation and experiment (via testing on prototype circuit) so as to examine the validity of the analysis/design and check the efficacy of the proposed structure.

On-chip photonic diffractive optical neural network based on a spatial domain electromagnetic propagation model.

An integrated physical diffractive optical neural network (DONN) is proposed based on a standard silicon-on-insulator (SOI) substrate. This DONN has compact structure and can realize the function of machine learning with whole-passive fully-optical manners. The DONN structure is designed by the spatial domain electromagnetic propagation model, and the approximate process of the neuron value mapping is optimized well to guarantee the consistence between the pre-trained neuron value and the SOI integration implementation. This model can better ensure the manufacturability and the scale of the on-chip neural network, which can be used to guide the design and manufacturing of the real chip. The performance of our DONN is numerically demonstrated on the prototypical machine learning task of prediction of coronary heart disease from the UCI Heart Disease Dataset, and accuracy comparable to the state-of-the-art is achieved.

A machine learning method for hardware Trojan detection on real chips

Due to the global supply chain of integrated circuits (IC) from design to application, Hardware Trojan (HT) may be stealthily inserted into ICs. The effect of HT detection methods are related to the signal-to-noise ratio (SNR) and the Trojan-to-circuit ratio (TCR). Various HT detection methods are designed to target at simulated circuits; however, the effect on real chips is not involved. In the light of detection of HT on real chips with low SNR and low TCR, a machine learning method is proposed and experimented in this paper. It is difficult to directly distinguish the insignificant effect of HT on a modern complex chip. The proposed method extracts statistic features to explore the much rich expression of HT signals and adjusts the distance of different features to separate Trojan circuits from the security ones far apart. The proposed methods are tested on real chips with 10−5 TCR and demonstrated the effect compared to other state-of-the-art methods.