Readout Integrated Circuit Research Articles

A CMOS Hall Sensors Array With Integrated Readout Circuit Resilient to Local Magnetic Interference From Current-Carrying Traces

This paper proposes a CMOS Hall sensors array with readout circuitry to counteract the magnetic interference from nearby conductors carrying high currents. The 3×3 Hall sensors array with current-spinning collects the spatial magnetic field information in a time-interleaved manner while the readout circuitry, formed by a capacitively-coupled instrumentation amplifier (CCIA) with T-capacitor feedback network, amplifies the transduced signals for subsequent processing. The calibration mechanism analyzes the magnetic field distribution on the array and separates the magnetic field component due to the environment and local perturbation from adjacent traces, enabling accurate detection of the environmental magnetic field. Prototyped in a 0.35-μm CMOS process, the Hall sensors array and readout circuit occupy an area of 2.2 × 2.2 mm2 and consume 3.5 mA of current under a 3.3-V supply. The hall sensors achieve an average sensitivity of 100 V/(A·T). The input-referred noise of the entire circuit is 0.128 μT/√Hz. With the interference cancellation scheme, the error in the magnetic field readings caused by a conductor 5 mm from the center of the chip carrying 3 A of current reduced from 120 to 5 μT, corresponding to a 24× improvement. Overall, the average error of the captured magnetic field after calibration reaches 0.9%.

A Baseline-Tracking Single-Channel I/Q Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring

An impedance plethysmogram (IPG) IC with wide-range fine baseline tracking capability is proposed to provide continuous blood pressure (BP) and cardiovascular monitoring just by wearing a neckband wearable device. For the baseline tracking, a mixed-mode baseline cancellation (MM-BC) scheme is proposed to achieve wide dynamic range (DR) and high SNR performance, where an artifact-detecting continuous-time (CT)- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $</tex-math> </inline-formula> ADC is included together for high-resolution conversion. For cost-effective IPG design, a phase synchronizer concept is introduced to provide I/Q detection capability with single readout channel, supporting both configurations of two-electrode and four-electrode. A proposed readout integrated circuit (ROIC) prototype for the proposed IPG was fabricated, where an electrocardiogram (ECG) readout path is integrated together. The proposed IPG schemes were experimentally verified to achieve good performances of 145.2-dB DR and 103.5-dB SNR. For system-level feasibility, a neckband device prototype was also manufactured, and its cardiovascular monitoring functionality was functionally verified. Based on its IPG and ECG measurements, continuous BP measurement based on the pulse arrival time (PAT) was experimentally verified with a reference BP device.

High-Linearity and High-Speed ROIC of Ultra-Large Array Infrared Detectors Based on Adaptive Compensation and Enhancement.

In order to solve the problem of limited linearity and frame rate in the large array infrared (IR) readout integrated circuit (ROIC), a high-linearity and high-speed readout method based on adaptive offset compensation and alternating current (AC) enhancement is proposed in this paper. The efficient correlated double sampling (CDS) method in pixels is used to optimize the noise characteristics of the ROIC and output CDS voltage to the column bus. An AC enhancement method is proposed to quickly establish the column bus signal, and an adaptive offset compensation method is used at the column bus terminal to eliminate the nonlinearity caused by the pixel source follower (SF). Based on the 55 nm process, the proposed method is comprehensively verified in an 8192 × 8192 IR ROIC. The results show that, compared with the traditional readout circuit, the output swing is increased from 2 V to 3.3 V, and the full well capacity is increased from 4.3 Me- to 6 Me-. The row time of the ROIC is reduced from 20 µs to 2 µs, and the linearity is improved from 96.9% to 99.98%. The overall power consumption of the chip is 1.6 W, and the single-column power consumption of the readout optimization circuit is 33 μW in the accelerated readout mode and 16.5 μW in the nonlinear correction mode.

Large-Scale Terahertz Sensor Array Module With Antenna-Coupled Microbolometers on Glass Substrate With Sigma–Delta ADC Readout ASIC

We describe the design, fabrication and demonstration of a terahertz sensor array module, designed to operate over 250-350GHz. The antenna coupled microbolometer was fabricated on a glass substrate with an integrated array of pixel switches and row multiplexing circuitry implemented with LTPS (Low Temperature PolySilicon) thin film transistors. While other microbolometer arrays have been reported for the upper Terahertz bands, we focus on lower frequencies where adequate semiconductor sources are available potentially enabling important medical and security applications. The devices were fabricated in a Gen 3.5 flat panel manufacturing facility implementing what we call Large Area MEMS Platform (LAMP) surface micromachining process, providing a path to low-cost manufacturing. Individual pixels were defined on a 0.7mm pitch across an array of 128x128 pixels in this first demonstration. Since flat panel fabrication capabilities use large, single-shot reticle masks and large glass substrates, physically larger arrays can be manufactured without mask stitching. An ROIC (readout integrated circuit) was demonstrated to support the THz sensor panel with 648 input channels, each providing an independent sigma delta ADC with excellent uniformity and 12 effective number of bits. An early demonstration of the sensor array is described, imaging a metallic knife hidden in a cardboard envelope.

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit has been implemented for a bridge sensor. The read-out integrated circuit has a capacitively-coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an output data-rate of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The ΔΣ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoI) filter. Implemented in a 0.13 μm CMOS process, the read-out circuit achieves an input impedance of 22 MΩ at a data-rate of 800 SPS, a sensor offset compensation range of ± 350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of 1.72 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at a gain of 128. It draws an average current of 106.3 μA from a 3 V supply and 1.3 μA from a 1.5 V supply.

Design, Annealing, and Electric Field Effects on Proton and Gamma Irradiated MWIR HgCdTe Focal Plane Arrays

This work presents the performance degradation under irradiation of multi pixel-designs n/p mid-wavelength infrared HgCdTe focal plane arrays (FPA). Gamma and proton irradiations are conducted to single out the effects of total ionizing dose (TID) from the damage induced by displacement damage dose (DDD). The radiation-induced degradation is analysed through the current levels evolution and the random telegraph signal (RTS) phenomenon. TID damages the silicon read-out integrated circuit (ROIC), causing low current level and RTS pixels. The influence of photodiode size and electric field on TID-induced defects is investigated. The results suggest that leakage currents in the ROIC, induced by TID, are involved. DDD impacts the HgCdTe photodetection layer: the number of pixels with high dark current and RTS is increased in the FPA. The amount of DDD-induced degradation scales with the photodiode size and the applied bias. This suggests that the defects responsible for the evolution of the dark current and RTS are located in the HgCdTe depletion region. Annealing mechanisms of these effects indicate different types of DDD-induced defects.

An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition.

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 , and an input-referred noise of 7.7 ± 0.4 in the AP band and 11.9 ± 1.1 in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter.

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

Noise Model of Large-Format Readout Integrated Circuit for Infrared Focal Plane Array

With the upscaling of the pixel format and the downscaling of the pixel pitch of infrared focal plane arrays (FPAs), the demand for ultra-low-noise design is increasing drastically. Existing methods of noise modelling lack transistor-level analysis and are unable to provide directly effective guidance for circuit design because of extremely complicated mathematical expressions. In this work, a comprehensive noise model of large-format readout integrated circuit (ROIC) is presented, for the first time elucidating the noise mechanism with a full research framework, including transistor-, circuit-, block-, and chip-level analysis. By utilizing a novel approximation method, simplified analytical formulas with high accuracy are obtained for flicker noise and other noise. These simplified formulas clear up the confusions of how the various functional circuit blocks influence noise performance. Moreover, based on the presented noise model, the impacts of crucial parameters on FPA noise are analyzed in detail, and strategies regarding the trade-off between the signal-to-noise ratio (SNR) and other aspects of performance are proposed for low-noise design. Taking an astronomical application with a very long integration time as an example, the calculated results show that an ultralow noise of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}{\,e^{-}}$ </tex-math></inline-formula> can be achieved by leveraging the above approaches.

A Chemoresistive Gas Sensor Readout Integrated Circuit With Sensor Offset Cancellation Technique

A Chemoresistive Gas Sensor Readout Integrated Circuit With Sensor Offset Cancellation Technique

Low-Noise, Low-Power Readout IC for Two-Electrode ECG Recording Using Common-Mode Charge Pump for Robust 20-VPP Common-Mode Interference

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-VPP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm2. The proposed CMCP achieves a CMI robustness of 20 VPP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply.

A Wireless Soil pH and Conductance Monitoring Chip Powered by Soil Microbial and Photovoltaic Energy Cells.

This paper presents an energy-autonomous wireless soil pH and electrical conductance measurement IC powered by soil microbial and photovoltaic energy. The chip integrates highly efficient dual-input, dual-output power management units, sensor readout circuits, a wireless receiver, and a transmitter. The design scavenges ambient energy with a maximal power point tracking mechanism while achieving a peak efficiency of 81.3% and the efficiency is more than 50% over the 0.05-14 mW load range. The sensor readout IC achieves a sensitivity of -8.8 kHz/pH and 6 kHz·m/S, a noise floor of 0.92 x 10-3 pH value, and 1.4 mS/m conductance. To avoid interference, a 433 MHz transceiver incorporates chirp modulation and on-off keying (OOK) modulation for data uplink and downlink communication. The receiver sensitivity is -80 dBm, and the output transmission power is -4 dBm. The uplink data rate is 100 kb/s using burst chirp modulation and gated Class E PA, while the downlink data rate is 10 kb/s with a self-frequency tracking mixer-first receiver.

Sound Activity Monitor Circuit for Low Power Consumption of Always-On Microphone Applications

A novel sound activity monitor (SAM) circuit for low power consumption of always-on microphone applications is presented. To reduce average power consumption, the ultra-low-power SAM is essential and operates a readout integrated circuit (ROIC) in low power mode with silent input or in normal power mode with voice input. A novel SAM with an architecture that does not include an envelope detector is proposed to achieve low power consumption. A new architecture is also proposed to improve MEMS sensitivity by connecting the SAM input to the source follower (SF) output instead of connecting the SAM input to the MEMS port already connected to the SF. In addition, in order to prevent inefficient frequent operation mode conversion, a feature of delaying the transition to the low-power mode after the sound is silenced is implemented. The proposed architecture is designed and verified based on the standard 0.18 µm CMOS process. The SAM, which consists of two-stage amplifiers (OA, AMP2), comparators, and a logic circuit, consumes a 1 µA current. The analog path consisting of SF, OA, and AMP2 in low power mode has a maximum amplification gain of 63 dB and a noise of 72 nVrms/√Hz at 1 kHz.

Integrated Millimeter-Wave and Terahertz Analyzers for Biomedical Applications

This invited paper reviews the progress of silicon-based integrated analyzers for biomedical applications over the last two decades. Focus is set on various integrated circuit realizations in the millimeter-wave range from 30 GHz and at the terahertz frequencies of above 300 GHz. This article discusses high-frequency architectures and concrete implementations of both narrowband as well as broadband integrated readout circuits, including their use in miniaturized sensor solutions. A variety of circuits ranging from low-power sensing oscillators to highly integrated broadband vector network analyzers (VNAs), and example realizations of millimeter-wave cardiovascular sensors and implants to THz microfluidic labs-on-chip and exhaled human breath analyzers are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of such biomedical sensors toward reliable and specific systems.

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems.

This paper presents an energy-efficient, duty-cycled, and spinning excitation bridge-to-digital converter (BDC) designed for implantable pressure sensing systems. The circuit provides the measure of the pulmonary artery pressure that is particularly relevant for the monitoring of heart failure and pulmonary hypertension patients. The BDC is made of a piezoresistive pressure sensor and a readout integrated circuit (IC) that comprises an instrumentation amplifier (IA) followed by an analog-to-digital converter (ADC). The proposed design spins both the bridge excitation and the ADC's sampling input voltages simultaneously and exploits duty cycling to reduce the static power consumption of the bridge sensor and IA while cancelling the IA's offset and 1/f noise at the same time. The readout IC has been designed and fabricated in a standard 180-nm CMOS process and achieves 8.4 effective number of bits (ENOB) at 1 kHz sampling rate while drawing 0.53 μA current from a 1.2 V supply. The BDC, built with the readout IC and a differential pressure sensor having 5 k Ω bridge resistances, achieves 0.44 mmHg resolution in a 270 mmHg pressure range at 1 ms conversion time. The current consumption of the bridge sensor by employing duty cycling is reduced by 99.8% thus becoming 0.39 μA from a 1.2 V supply. The total conversion energy of the pressure sensing system is 1.1 nJ, and achieves a figure-of-merit (FoM) of 3.3 pJ/conversion, which both represent the state of the art.

MEMS Cavity-Based pH Image Biosensor for Wound Dressings to Monitor Hard-to-Cure Wounds

The biochemical processes in the body, including wound healing, are influenced by pH. When skin is damaged, in the inflammation phase, the pH of the skin is under pH 6.0, and in the granulation and spontaneous reepithelization phase, the pH of the skin oscillates between 6 and 8. If there is a frequent change in the wound dressing, it will make the damage to the skin hard to cure, especially for chronic wounds. In this article, we design and implement a highly sensitive micro-electro-mechanical-system (MEMS) cavity-based pH image biosensor of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100\times100$ </tex-math></inline-formula> array with an integrated readout circuit in a CMOS bulk technology. Based on the proposed pH fringing electrical field model, we predict and optimize the performance of the proposed sensor pattern with cavity structure for operation frequency and various pH ions. The proposed pH biosensor with MEMS cavity structure exhibits a high sensitivity of 201 mV/pH, low drift voltage over time of 2.08 mV, a fast response time of 5 s, high precise repetition of 98.9%, and a pH image of 20 frame rate/s. Since the sensor is a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100\times100$ </tex-math></inline-formula> array, it displays a detailed change in the pH image of wound exudate to identify the inflammation stage under pH 6 or spontaneous reepithelization above pH 6 to indicate the need to change the dressing, reducing the clinician’s wasted resources on frequency change of wound dressings.

A 640×512 ROIC with optimized BDI input stage and low power output buffer for CQDs-based infrared image sensor

A 640 × 512 readout integrated circuit (ROIC) for colloidal quantum dots (CQDs) infrared image sensor is presented in this paper. An optimized buffered direct injection (BDI) pixel circuit and a low power rail-to-rail output buffer are proposed to achieve higher array-level consistency of output voltage. The ROIC can process photocurrent of CQDs detector from 100 fA to 100 pA with a conversion gain (CG) of 2.13μV/e−, full well capacity (FWC) of 4.6 × 105e− and readout noise of 100e−. With 1.8 V power supply for both digital and analog modules, the output signal swing exceeds 1 V and performs linearity over 99.95% under different PVT conditions. The ROIC is designed and simulated with SMIC 0.18 μm mixed-signal 1-poly 6-metal (1P6M) process and the die size is 11.13 mm × 8.78 mm.

A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications

SummaryPower consumption and image resolution are the major concerned while designing modern readout integrated circuits (ROICs) of Cadmium‐Telluride (CdTe)/Cadmium‐Zinc‐Telluride (CdZnTe) sensors for nuclear magnetic resonance imaging (MRI) and positron emission tomography (PET) applications. The key ROIC element, namely, preamplifier, must be monolithically integrated to the sensor chip and should guarantee low noise, low power, and high linearity along with assuring higher conversion gain and less chip area. A power immune, linear charge sensitive preamplifier (CSP) with a custom leakage current compensation feedback for (CdTe)/CdZnTe sensors is designed. A maximum power consumption of 120 μW, stable against process voltage and temperature (PVT) variations, is achieved. The compensation module cancels out current noise generated at the output of the circuit, lowering the power spectral density of about 84.26% than that of similar architectures, thus improving the signal‐to‐noise ratio (SNR) at the CSP output by a factor of 6.31. In turns, it injects about 100 pA of input direct‐current (DC) current and compensates the sensor leakage current therefore. Two input dynamics of (0.25–10) and (10.01–20)fC are achieved, providing two conversion factors of 23.06 and 19.00 mV/fC with 2.4% and 0.58% nonlinearity errors, respectively, using 1 pF sensor capacitance. Noise performance of the circuit is improved with 47.5 e‐rms and 62.46e−rms of equivalent noise charge (ENC) depending upon the input dynamic. The design is validated by Monte Carlo simulations and PVT analysis implemented in 65 nm complementary metal‐oxide semiconductor (CMOS) process, assuring a chip area of only 0.000246 mm2.

Design of Prototype Readout Integrated Circuit for Time-of- Arrival and Time-over-Threshold Measurement for Hybrid Pixel X-ray Detectors in 28 nm CMOS

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