Reactive Ion Etching Tool Research Articles

Atomic layer etching of indium tin oxide

This work presents the atomic layer etching (ALE) process for sputtered indium tin oxide (ITO) thin films using thermal surface modification with BCl3 and modified surface removal by low ion energy Ar plasma. In this approach, an elevated temperature is required for high synergy ALE due to the low volatility of indium chlorides, and 150°C is proved to be suitable. An etch per cycle (EPC) of 1.1 Å and ALE synergy of 82% was achieved. Both surface modification and modified surface removal steps exhibited self-limited EPC. The ALE process was developed in a conventional reactive ion etching tool and retains the thin film absolute uniformity on the wafer. ITO was photolithographically patterned on whole wafers using photoresist as an etch mask for the ALE, and clear smoothing of the unmasked areas is observed, which is a characteristic of an ideal ALE process. This confirms that the developed ALE process can be utilized to pattern ITO using conventional photolithography. The demonstrated ITO ALE can be used to fabricate, for example, thin channel or recessed channel transistors, with self-smoothened channels for reduced surface scattering.

Large area nanoscale patterning of functional materials using organosilicate ink based nanotransfer printing

This paper presents a versatile nanotransfer printing method for achieving large-area sub-micron patterns of functional materials. Organosilicate ink formulations combined with effective release layers have been shown to facilitate patterning of materials through the commonly used patterning approaches—lift off, physical etching and chemical etching. In this paper, we demonstrate that organosilicate ink formulations function as an effective resist owing to its superior physico-chemical stability whereas the release layers ensure clean removal of the resist post patterning. We successfully demonstrate patterning of sub-micron structures (800 nm feature sizes) of chromium metal through the lift off approach, silicon through reactive ion etching technique and silicon dioxide through wet chemical etching technique illustrating the versatility of the reported method. This patterning methodology represents a significant advancement in enabling nanostructure fabrication within resource-constrained laboratories. The approach requires nothing more than a master mold containing the desired structures, a spin coater, a low-temperature hotplate, and a desktop reactive ion etch tool.

Numerical and experimental exploration towards a 26% efficiency rear-junction n-type silicon solar cell with front local-area and rear full-area polysilicon passivated contacts

In this work, structure designs and the corresponding energy loss analysis are conducted to achieve the high-efficiency n-type rear-junction solar cells with polysilicon passivated contact. We focus on the front-side structure design of solar cells, considering that the primary efficiency loss of the conventional n-type polysilicon passivated contact cells with boron-diffusion emitter is from the front side. A well-designed rear-junction solar cell with front localized n-type and rear full-area p-type polysilicon passivated contacts is expected to overcome these problems. However, the efficiency of rear-junction solar cells is sensitive to the front-side electrode contact resistivity. To accurately assess the practically achievable efficiency that the current technology can reach, we develop a simple modified TLM with wet-chemical etching to measure the contact resistivity of the n-type polysilicon contact. This method does not require relatively expensive photolithography and reactive ion etching tools and is easy to be used. When the contact resistivity of the front-side localized n-type polysilicon contact reaches 0.002 Ω·cm2 with a saturation current density of ~10 fA/cm2 in the front-side un-diffused area, the efficiency of the rear-junction n-type solar cell is expected to be ~26%, showing its potential for application in mass-production of high-efficiency crystalline silicon solar cells.

Demonstration of genuine surface inversion for the p/n-In0.3Ga0.7Sb-Al2O3 MOS system with in situ H2 plasma cleaning

The results of an investigation into the impact of in situ H2 plasma exposure on the electrical properties of the p/n-In0.3 Ga0.7 Sb-Al2O3 interface are presented. Samples were processed using a clustered inductively coupled plasma reactive ion etching and atomic layer deposition tool. Metal oxide semiconductor capacitors were fabricated subsequent to H2 plasma processing and Al2O3 deposition, and the corresponding capacitance-voltage and conductance-voltage measurements were analyzed quantitatively via the simulation of an equivalent circuit model. Interface state (Dit) and border trap (Nbt) densities were extracted for samples subjected to the optimal process, with a minimum Dit of 1.73×1012 eV−1 cm−2 located at ∼110 meV below the conduction band edge and peak Nbt approximately aligned with the valence and conduction band edges of 3×1019 cm−3 and 6.5×1019 cm−3, respectively. Analysis of the inversion response in terms of the extraction of the activation energy of minority carriers in inversion (p-type) and the observation of characteristics that pertain to minority carriers being supplied from an external inversion region (n-type) unequivocally demonstrate that the Fermi level is unpinned and that genuine surface inversion is observed for both doping polarities.

Modified inductively coupled plasma reactive ion etch process for high aspect ratio etching of fused silica, borosilicate and aluminosilicate glass substrates

We report on the etching of glass substrates of various compositions in a modified inductively coupled plasma – reactive ion etch (ICP-RIE) tool using SF6 as the plasma source gas and NF3 and H2O gases introduced downstream near the surface of the wafer through a diffuser gas inlet. Using this modified system, we have been able to achieve etch rates as high as 1.06 μm/min, 1.04 μm/min, and 0.45 μm/min with surface smoothness of ∼2 Å, ∼67 Å, ∼4 Å for fused silica, borosilicate glass, and aluminosilicate glass respectively after 5 min etches. We examine the role of ion flux and fluorine radicals and molecules on the etch rate and the etch smoothness. We analyze the results obtained on 41 etches through multivariate statistical analysis and use the Pearson coefficient and P-value to determine the importance of these parameters for each of the glass substrate compositions. Overall for all three glass compositions, etch rate is critically influenced by ion flux. Fluorine based radicals and molecular fragments influence both the etch rate and surface smoothness of fused silica whereas they primarily influence the surface smoothness for borosilicate glass. The large fraction of impurity atoms of Ca and Al in aluminosilicate glass form non-volatile fluorides in the etched areas and therefore the etch rate and surface smoothness of aluminosilicate glass is primarily influenced ion flux and very little by the fluorine chemistry. We also examine the role of the layout of the metal mask layer on how it influences the charging of glass substrates during etching and therefore the etch rate.

MEMS Industry-Worth Etching to Fabricate Tapered Structures in SiO2

This paper presents the results for developing SiO2 plasma etching with tapered sidewalls for microelectromechanical systems (MEMS). The experiment was designed in an industrial inductively-coupled plasma reactive ion etching tool, wherein a two-step etching process was developed for opening vias in the SiO2 with a sidewall angle of 68°–70°. The first step modified the photoresist profile from a vertical to a tapered profile using Ar/O2/CF4 plasma with a high wafer platen power. The second step of SiO2 etching was performed in C4F8/H2-based plasma with added inert gases and used a dual mechanism of photoresist pattern transfer and etch by-product redeposition on the sidewalls. The introduction of the photoresist profile tapering as the first step of the etching process not only facilitated fabrication of tapered sidewalls, but also helped to avoid etch-stop in structures with a critical dimension (CD) down to 1.5 $\mu \text{m}$ and minimize the etch CD shrink. [2017-0089]

Nanopore patterning using Al2O3 hard masks on SOI substrates

Aluminum oxide Al2O3, deposited using amorphous atomic layer deposition (ALD), is a very promising material to be utilized as a hard mask for nano-patterning. We used an aluminum oxide hard mask on a silicon-on-insulator (SOI) substrate to implement a sub-100 nm nanopore process. The transfer of nanoscale patterns via dry etching of the Al2O3 thin film was investigated by comparing etch profiles, etch rates, and selectivity of Al2O3 over PMMA resist, using different gas chemistries such as Cl2, Ar, Ar/BCl3 mixtures, and BCl3 plasma. A selectivity of 1:4 was observed using an inductively coupled plasma reactive ion etching (ICP-RIE) tool with BCl3 plasma, and the sub-100 nm nanopore patterns were anisotropically transferred to the alumina layer from a 250 nm PMMA layer. The dense and inert Al2O3 hard mask showed exceptional etch selectivity to Si and SiO2, which allowed the subsequent transfer of the nanopore patterns into the 340 nm-thick Si device layer and made it possible to attempt etching the 1 μm-thick buried oxide (BOX) layer. Using chlorine chemistry, nanopores patterned in the Si device layer showed excellent anisotropy while preserving the original pattern dimensions. The process demonstrated is ideally suited for patterning high aspect ratio nanofluidic structures.

Wafer-to-wafer process fault detection using data stream mining techniques

In this paper, we develop a wafer-to-wafer fault detection system using data stream mining techniques for a semiconductor etch tool. The system consists of two data stream mining modules: a trace segmentation module and a multivariate trace comparison module. Each time a wafer exits the processing chamber, the trace segmentation module extracts the traces of monitored tool parameters from raw sensor data streams. We propose a novel trace segmentation algorithm called multisensor-based trace segmentation. The algorithm finds the individual start and end times of monitored tool parameters in a wafer-to-wafer fashion. For analyzing faulty tool operations, the multivariate trace comparison module performs a new principal component analysis (PCA) called a trace structure-based PCA. For each tool parameter, the structural similarity distance between a template and the extracted trace is measured using a dynamic time warping algorithm. Then, the measurements are used to build the PCA model. This approach is contrasted with the traditional PCA procedure in which the trace means are used as the building blocks for the PCA model. Experiments using the data collected from a worksite reactive ion etch tool showed that the performance of the proposed system is very encouraging.

Fabrication And Characterization Of Tunable, Low Stress Al2O3 Nanopores For The Electronic Detection Of Biomolecules

Understanding the biophysics governing single molecule transport through solid state nanopores is of fundamental importance in working towards the goal of genome sequencing using nanopore based sensors. Here, we present a simple process for the fabrication and characterization of novel, low stress, low noise aluminum oxide nanopores for biomolecule detection. Aluminum oxide has numerous attractive properties including high mechanical hardness, low surface charge, chemical inertness to strong acids and excellent dielectric properties from DC to GHz frequencies.Device fabrication involved the use of Atomic Layer Deposition and Deep Reactive Ion Etching tools to form low stress, mechanically robust aluminum oxide membranes. High temperature process steps were avoided to allow for possible process integration with metal nano-electrodes and optical probes. The nanometer sized pores themselves were formed through Field Emission Gun Transmission Electron Microscope (FEG-TEM) based sputtering. We demonstrate the precise size tunability of these structures in the nanometer regime and examine the physics governing pore contraction in aluminum oxide. Diffraction patterns reveal polycrystallinity localized to the pore region post sputtering suggesting localized heating and possible thermal annealing under the electron beam. Film composition and thickness were characterized. In addition, we examine the surface charge properties of these structures as a function of buffer pH and molarity. The single molecule sensing ability of this novel structure was tested using dsDNA. Electrical characterization revealed a significant reduction in membrane capacitance and reduced high frequency dielectric noise relative to existing silicon nitride and silicon dioxide topologies. These improvements can greatly enhance device performance by improving sensitivity and signal-to-noise ratio. In summary, our work provides a novel yet simple approach to fabricate tunable, low stress chemically functionalizable nanopores for the detection of biomolecules.

Fabrication and testing of through-silicon vias used in three-dimensional integration

The formation of through-silicon vias (TSVs) provides a vertical interconnect scheme that can be used in three-dimensional stacking technologies. A sloped via sidewall is essential for conformal coverage of via lining materials deposited in subsequent steps that provide insulation (SiO2), barrier (TaN), and metal seed (Cu) layers. In this article, via sidewall angles in the range of 83°–90° are investigated resulting in variable degrees of conformal lining of the insulation, barrier, and seed layers. Via insulation is deposited by plasma enhanced chemical vapor deposition, while barrier and seed layers are deposited by sputtering. A modified Bosch process, using a deep reactive ion etch tool, allows formation of differing via profiles in silicon substrates. Cross-sectional views of via profiles showing the coverage of lining materials (SiO2, TaN, and Cu) are examined with a scanning electron microscope. For a constant via sidewall angle, variable aspect ratios allow us to determine the specific via profile that can be conformally lined and filled by Cu electroplating without the presence of voids. The aspect ratios of the vias under study are in the range of 2–4. Electrical performance of the fabricated TSVs is reported and is consistent with expected performance.

MWIR HgCdTe Photodiodes based on high-density plasma-induced type conversion

A novel fabrication process for planar n-on-p junction HgCdTe infrared photodiodes has previously been demonstrated based on H2/CH4 plasma-induced type conversion in a parallel-plate reactive ion etching (RIE) tool. In this work, it is demonstrated that high-performance photodiodes can also be fabricated based on H2/CH4/Ar plasma-induced type conversion in an inductively coupled plasma (ICP) RIE plasma tool. This tool has significantly greater control over the plasma condition, and the plasma condition for the type conversion process is significantly different to that associated with the junction formation process that has previously been demonstrated based on the parallel-plate RIE reactor. Photodiodes have been fabricated based on different ICPRIE plasma process conditions, and characterized by current–voltage and noise measurements. The performance characteristics of these photodiodes are comparable to those reported for diodes, based on established fabrication processes based on ion implantation or ion beam milling. The effects of the ICPRIE process parameters used for junction formation on the respective photodiode performance characteristics are investigated in terms of the plasma-induced type conversion mechanisms.

Pattern transfer using poly(styrene-block-methyl methacrylate) copolymer films and reactive ion etching

Self-assembly block copolymers have drawn a lot of attention for its great potential on critical dimension (CD) control and line-edge roughness (LER) reduction, which become more and more crucial as the CD of transistors is only tens of nanometers nowadays. In this study, lamellar-forming poly(styrene-b-methyl methacrylate) copolymer which fabricates line patterns was chosen for its ability to provide higher aspect ratio and vertical sidewall profile in template stage, thus more suitable for the following etching process to substrate. A dry plasma etching process using pure oxygen and pure argon plasma as example chemical etching gas and physical etching gas, respectively, was studied. Etching selectivity and lateral etch rate, which are responsible for the final template height and CD loss, had been characterized on a capacitive reactive ion etching tool. The templates formed by the proposed process had high aspect ratios, excellent pattern fidelity, and low LER values. The PS lateral etch rate was small enough to provide a wide process window for retaining the CD of the pattern during the template forming process. Subsequent silicon etching using the PS template made by dry etching process yielded a steep and smooth sidewall profile.

Effect of process parameters on via formation in Si using deep reactive ion etching

The effect of process parameters on blind via formation for vertical interconnects using an STS deep reactive ion etch tool is reported. A modified Bosch process is used to create vias (20 and 25μm in diameter) with varying depths and sidewall angles on 125mm diameter silicon wafers using a photoresist mask. The effect of changing the flow rates of SF6 and C4F8 gases, the automatic pressure control angle, and coil and platen powers on via profile and sidewall morphology is studied. The effect of chamber cleaning and conditioning on controlling the diameter growth at the top surface of the via is also reported. The various via profiles are examined using an environmental scanning electron microscope and by observing via cross sections. Each parameter plays a critical role in obtaining a specified via profile. A sloped via sidewall is required for our application of fabricating vertical interconnects. After etching, vias are insulated by depositing 2μm of silicon dioxide by plasma enhanced chemical vapor deposition at 250°C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the via. The sloped via sidewall is required due to the weak step coverage obtained by sputter deposition.

High aspect ratio Bosch etching of sub-0.25μm trenches for hyperintegration applications

The ability to predict and optimize the effects of the process parameters during silicon dry etching is vital for the fabrication of emerging hyperintegration technologies, as well as many microelectromechanical systems and integrated circuit devices. This article outlines the establishment of reactive ion etching protocols for fabrication of high aspect ratio trenches with minimum scalloping and undercut, employing the Bosch process. High aspect ratio submicron trench array patterns were transferred into silicon substrates using a Unaxis Versalock deep reactive ion etch tool equipped with a time multiplexed plasma etch/passivation cycle scheme which uses an inductively coupled plasma etcher. Through careful optimization of Bosch etch process conditions, successful etching of high aspect ratio (20:1) 170nm trench features was achieved.

Effect of High-Density Plasma Process Parameters on Carrier Transport Properties in p-to-n Type Converted Hg0.7Cd0.3Te Layer

Exposure of p-type HgCdTe material to Ar/H 2 -based plasma is known to result in p-to-n conductivity-type conversion. While this phenomenon is generally undesirable when aiming to perform physical etching for device delineation and electrical isolation, it can be used in a novel process for formation of n-on-p junctions. The properties of this n-type converted material are dependent on the condition of the plasma to which it is exposed. This paper investigates the effect of varying the plasma process parameters in an inductively coupled plasma reactive ion etching (ICPRIE) tool on the carrier transport properties of the p-to-n type converted material. Quantitative mobility spectrum analysis of variable-field Hall and resistivity data has been used to extract the carrier transport properties. In the parameter space investigated, the n-type converted layer carrier transport properties and depth have been found to be most sensitive to the plasma process pressure and temperature. The levels of both RIE and ICP power have also been found to have a significant influence.

Sub-0.25 micron silicon via etching for 3D interconnects

Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar integrated circuits (ICs). Etching high aspect ratio submicron vias for inter-wafer connection is one of the key processing metrics for the wafer-level 3D technology platform. The ability to optimize the effects of the process parameters during via etching is vital for the fabrication of emerging hyperintegration technologies. This paper outlines the establishment of reactive ion etching protocols for fabrication of high aspect ratio silicon vias with minimum bowing employing the Bosch process. High aspect ratio submicron via patterns were transferred into silicon substrates using a Unaxis Versalock deep reactive ion etch (DRIE) tool. Through careful optimization of Bosch etch process conditions, successful etching of high aspect ratio (13:1) 200 nm via features was achieved.

A Gap Reduction and Manufacturing Technique for Thick Oxide Mask Layers With Multiple-Size Sub-<tex>$mu$</tex>m Openings

This paper introduces a technique for the fabrication of thick oxide hard masks on top of a substrate with adjustable opening sizes in the sub-mum regime, while the only lithography step involved has mum-scale resolution. This thick oxide mask layer with sub-mum openings is suitable for etching deep narrow trenches in silicon using deep reactive ion etching (DRIE) tools. Openings of less than 100 nm are realized in a 1.5-mum-thick oxide layer, while the original lithographically defined feature sizes are larger than 1 mum in width. This method, combined with modified high aspect ratio DRIE recipes, shows a great potential for single-mask batch-fabrication of high frequency low-impedance single crystalline resonators on silicon-on-insulator (SOI) substrates. Dry-etched trenches with aspect ratios as high as 60:1 are fabricated in silicon using the gap reduction technique to realize 200 nm opening sizes in an oxide mask layer. Various resonator structures with sub-mum capacitive gaps are also fabricated on a SOI substrate using a single-mask process. Measurement results from high-frequency and high-quality factor (Q) all single crystal silicon resonators are presented

Control of sidewall slope in silicon vias using SF6∕O2 plasma etching in a conventional reactive ion etching tool

The etching of anisotropic blind vias in silicon with diameters of 5–10μm and an aspect ratio ∼2–4 with controlled sidewall inclination is reported. The motivation for this work is the creation of a vertical, or three dimensional interconnect. Via formation by reactive ion etch (RIE) processing is the focus of this project. Arrays of vias have been etched in 125 mm diam silicon (100) wafers using a photoresist mask. A parallel plate RIE system with a SF6∕O2 gas mixture is used. The effects of O2∕(SF6+O2) gas flow ratio, electrode bias, and chamber pressure on etch rate and feature profile have been studied. Visualization of the via profiles using scanning electron microscopy is used to identify the key parameters that control the sidewall slope. This slope is important for the subsequent deposition of via lining materials before filling with Cu. Our results indicate that the O2∕(SF6+O2) ratio is a key parameter in determining the sidewall slope, however the electrode bias and chamber pressure are critical in determining the physical and chemical process balance that determine the anisotropy of the etch process.

Microfabrication and application of high-aspect-ratio silicon tips

We report a new process combining reactive ion etching (RIE) and deep RIE (DRIE) tools for microfabrication of high-aspect-ratio (HAR) silicon tips with heights >40μm and aspect ratios of 7. We integrate atomic force microscope (AFM) cantilevers with HAR tips and compare AFM scans using an HAR tip and a commercial tip. Our results demonstrate the advantage of HAR tips for metrology applications.

Batch reactive ion etching of gallium nitride using photoresist as a mask

Though advances had being made in the growth technology of gallium nitride (GaN), the device wafer sizes remain at a maximum of 2″. The consequence of this is that in a production environment single wafer processing severely impacts on throughput and therefore the profitability. Dry etching is an essential part of gallium nitride device (C.R.Eddy, Jr., Etch Process of III–V Nitrides, RES 4S1, G10.5 (1999) [1]) processing because of the high bond strength and lack of simple wet etch process. This paper discusses the methods developed to enable the Reactive Ion Etching (RIE) of batches of GaN. Photoresist was used to define mask patterns on 2″ GaN wafers. Various batch sizes were processed in an Oxford Instruments Plasma Technology Plasmalab133 RIE tool. Etch rates in excess of 50 nm/min were achieved for batches of six and fifteen two inch GaN wafers. Uniformities of etch across these batches are +/–3% and +/–5%, respectively. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)