Rapid Thermal Processing Chamber Research Articles

Rapid and Efficient Oxidation Process of SiC by <i>In Situ</i> Multiple RTP Steps

Rapid Thermal Processing (RTP) has been evaluated as an alternative to conventional furnace technique for oxidation of 4H- and 3C-SiC. We show that the growth of the SiO2 films in a RTP chamber is orders of magnitude faster than in a conventional furnace. As well as being fast, this process leads to oxide films with quality comparable or even better than the one grown in classical furnaces. Studying different gas for oxidizing and annealing ambient, we demonstrate that SiO2/SiC interface is significantly improved when using N2O instead of O2 or even N2-O2 dilution.

Optimization of rapid thermal processing for uniform temperature distribution on wafer surface

An optimization of rapid thermal processing (RTP) was conducted to obtain uniform temperature distribution on a wafer surface by using linear programming and radiative heat transfer modeling. The results show that two heating lamp zones are needed to maintain uniform wafer temperature and the optimal lamp positions are unique for a given geometry and not affected by wafer temperatures. The radii of heating lamps, which were obtained by optimization, are 45 mm and 108 mm. The emissivity and temperature of the chamber wall do not significantly affect the optimal condition. With obtained optimum geometry of the RTP chamber and lamp positions, the wafer surface temperatures were calculated. The uniformity allowance of the wafer surface is less than ±1°C when the mean temperature of the wafer surface is 1000°C.

Modeling and temperature control of rapid thermal processing

In the past few years, rapid thermal processing (RTP) has gained acceptance as mainstream technology for semiconductor manufacturing. This single wafer approach allows for faster wafer processing and better control of process parameters on the wafer. However, as feature sizes become smaller, and wafer uniformity demands become more stringent, there is an increased demand from rapid thermal (RT) equipment manufacturers to improve control, uniformity and repeatability of processes on wafers. In RT processes, the main control problem is that of temperature regulation, which is complicated due to the high non-linearity of the heating process, process parameters that often change significantly during and between the processing of each wafer, and difficulties in measuring temperature and edge effects. This paper summarizes work carried out in cooperation with Steag CVD Systems, in which algorithms for steady state and dynamic temperature uniformity were developed. The steady-state algorithm involves the reverse engineering of the required power distribution, given a history of past distributions and the resulting temperature profile. The algorithm for dynamic temperature uniformity involves the development of a first-principles model of the RTP chamber and wafer, its calibration using experimental data, and the use of the model to develop a controller.

A novel approach for co-firing optimization in RTP for the fabrication of large area mc-Si solar cell

High-efficiency solar cells require printed metal contacts with adapted emitters to ensure high fill factors. Multi-crystalline silicon (mc-Si) substrates require adapting the temperature ramps of rapid thermal processing (RTP) to avoid minority carrier lifetime degradation from activated defect centers. Sufficient temperature difference is required between front and back surfaces during co-firing to prevent junction leakage on the front and proper aluminum back surface field (Al-BSF) on the back surface. Actual temperature profile for co-firing in RTP after screen printing is a key issue for high-quality metal–semiconductor contact for high efficiency solar cell. A novel approach for optimization of co-firing temperature profile in RTP is investigated by measuring the actual temperature of front and back surfaces of the solar cell. Rapid cooling in the spike firing profile is made possible by controlling the gas flow rate in the RTP chamber during co-firing. For the best front and back metal contact and enhancement of minority carrier lifetime, the actual temperature of the silver (Ag)-printed surface is 605 °C and that of Al-printed surface is 743 °C. Mc-Si solar cell with fill factor (FF) 0.79 and conversion efficiency 15.02% is fabricated using the optimized co-firing temperature of RTP in a conventional solar cell production line.

Design-tool for Rapid Thermal Processors for Optimal Trajectory Tracking

It has become an irreversible trend in recent years that the semiconductor wafer fabrication requires shorter processing time, greater flexibility and lower capital cost. Rapid thermal processing (RTP) has demonstrated its potential to meet such requirements while becoming a key process for manufacturing advanced semiconductor devices. Ever decreasing feature sizes require extremely tightly controlled processing conditions, especially the temperature trajectory to be precisely followed across the wafer. This paper presents a systematic methodology for RTP chamber design, based on the 3-dimensional physics-based model of a generic RTP chamber. After experimentally validated, the physics-based model is reduced to a lower-order model without sacrificing its fidelity for computational efficiency. With a reduced-order model, optimization studies are performed to determine how small the deviation of the wafer temperature from the pre-specified trajectory can be made in a given design. The results of the optimization studies indicate the goodness of the given RTP design, unravel clues for design improvements, and may provide guidelines for control implementation.

Ellipsometric study of the polysilicon/thin oxide/single-crystalline silicon structure and its change upon annealing

Polysilicon/thin oxide/single-crystalline silicon structures used as emitters of bipolar transistors were measured using spectroscopic ellipsometry. The thin SiOx layer was deposited on the substrate in a rapid thermal processing chamber, then polysilicon was deposited, implanted with As, and annealed. During annealing the SiOx layer dissolves to islands retarding the diffusion of As, which results in a shallow p-n junction. The process—and as a consequence, the device performance—depends sensitively on the thickness of the oxide layer. We developed optical models to measure the thickness of the SiOx layer at each process step, i.e., after SiOx deposition, after polysilicon deposition, and after annealing. The structure, the surface quality, and the homogeneity of the polysilicon layers were obtained from the same optical model. The thickness of the initially 0.76–0.86 nm SiOx layer decreased to the detection limit of about 0.2 nm during annealing, together with a significant crystallization of the deposited amorphous Si resulting in a perfectly smooth surface with a native oxide layer. The uncertainty of the measurement of the SiOx layer after annealing was typically 0.2 nm even below the polysilicon layer of about 150 nm. Our results show that ellipsometry is a proper tool for the measurement of the thickness of the buried SiOx boundary layer, which can be applied as an in line or in situ measurement as well.

Oxidation and roughening of silicon during annealing in a rapid thermal processing chamber

Silicon wafers were annealed at 1100 °C in nitrogen flowing ambient, using a conventional rapid thermal processing system operating at atmospheric pressure. Subsequently, silicon oxidation and the resulting surface morphology following chemical etching of the oxide film were studied. According to atomic force microscopy analysis, a significant amount of roughening occurs on the silicon surface after the high temperature anneal in nitrogen. However, by adding 10% oxygen to the nitrogen ambient, the average surface roughness was reduced by a factor of ∼3. Ellipsometry measurements were performed to study silicon oxidation following annealing. It was shown that the ellipsometric characteristics of the surface after removal of the oxide layers can be correlated to generation of surface roughness. A close agreement between the experimental results and theoretical calculations was obtained with respect to the oxidation induced surface roughening.

Modelling, Simulation and Design Optimization of Rapid Thermal Processing System

This paper describes modelling and simulation of rapid thermal processor. Further, these modelling and simulation experiments have been used to design and optimize the rapid thermal processing chamber dimension. Using these design guidelines, a Rapid Thermal Processor (RTP), reaching 1200°C with a ramp rate 200°C/second has been fabricated. Likewise, RTP chamber for any specifications can be designed. The results of these experiments are illustrated.

Ultrathin SiOxNy by rapid thermal heating of silicon in N2 at T=760–1050 °C

In this letter, we report on the reaction between Si and N2 in the temperature range of 760–1050 °C, in a rapid thermal processing chamber. Gas phase impurities such as H2O, O2, and H2, which can outgas from the cold walls of the chamber, mediate the Si/N2 reaction, resulting in the formation of SiOxNy. The oxynitridation can be explained by equilibrium chemical thermodynamics, in contrast to the case of oxynitridation using N2O or NO, where the nitrogen is incorporated under nonequilibrium conditions. Using nuclear reaction analysis, we have measured nitrogen contents as high as 2.5×1015 N/cm2 (the equivalent of more than 3 monolayers) in these new dielectrics. They can be reoxidized to form ultrathin (2 to 3 nm) dielectrics.

Photon effect on radiative properties of silicon during rapid thermal processing

Emissivity is a critical parameter in the rapid thermal processing (RTP) of semiconductors for temperature control and thermal modeling. It is often considered as a material property that depends on the sample temperature and surface finishing. For a silicon wafer placed in a radiation environment such as a RTP chamber, however, the ambient photons emitted from lamps create electron-hole pairs in the wafer. These electrons and holes participate in the thermal emission from the wafer and change its radiative properties. This work studies this photon effect on the radiative properties of silicon and demonstrates, through modeling and experiment, that radiative properties of a silicon wafer may depend on the temperature of the lamps due to free-carrier excitation. Such an photon effect imposes a limit on the accuracy of temperature measurement by the infrared pyrometry method in a RTP environment. It is also an important factor to consider in the measurement of the temperature dependence of silicon’s optical properties and in the thermal modeling of the RTP.

On Operating Point Sensitivity of Thermal Processes

First-principles based nonlinear dynamic model of a rapid thermal processing chamber is used to consider a control/structure interaction problem. The proposed approach ranks a particular chamber design according to steady-state wafer uniformity analysis for constant inputsas well as achievable transient uniformity during ramping using a baseline integral action controller. A computational toolset is developed to determine operating points, reduced-order small signal equivalent models, step- or ramp-tracking feedback controllers and a baseline dynamic response for a given chamber design. The approach is illustrated on a model.

Effects of Reflective Surfaces on Silicon Emissivity and Temperature Measurements

AbstractThe effects of front-side reflective surfaces on the emissivity and temperature measurement of silicon wafers in a Rapid Thermal Processing chamber with backside heating are examined through optics modeling. Two schemes are contrasted. In (1), the pyrometry detector looks at the back-side of the wafer; in (2), it looks at the front-side of the wafer. In both cases, the temperature errors occur when the reflector's reflectivity deviates from unity. However, the error dependence on the reflector reflectivity exhibits interesting differences in these two schemes. Under the working conditions proposed in this paper, a non-ideal reflector introduces a bigger temperature error in the “backside-detector” scheme than in the “front-detector” scheme. Practical implications of these results are also discussed.

Concurrent Design of an RTP Chamber and Advanced control system

AbstractA concurrent-engineering approach is applied to the development of an axisymmetric rapidthermal- processing (RTP) reactor and its associated temperature controller. Using a detailed finite-element thermal model as a surrogate for actual hardware, we have developed and tested a multiinput multi-output (MIMO) controller. Closed-loop simulations are performed by linking the control algorithm with the finite-element code. Simulations show that good temperature uniformity is maintained on the wafer during both steady and transient conditions. A numerical study shows the effect of ramp rate, feedback gain, sensor placement, and wafer-emissivity patterns on system performance.

Concurrent Design of an RTP Chamber and Advanced Control System

ABSTRACTA concurrent-engineering approach is applied to the development of an axisymmetric rapidthermal-processing (RTP) reactor and its associated temperature controller. Using a detailed finiteelement thermal model as a surrogate for actual hardware, we have developed and tested a multi-input multi-output (MIMO) controller. Closed-loop simulations are performed by linking the control algorithm with the finite-element code. Simulations show that good temperature uniformity is maintained on the wafer during both steady and transient conditions. A numerical study shows the effect of ramp rate, feedback gain, sensor placement, and wafer-emissivity patterns on system performance.

Low-order modeling and dynamic characterization of rapid thermal processing

A low-order model of rapid thermal processing (RTP) of semiconductor wafers is derived. The first-principles nonlinear model describes the static and dynamic thermal behavior of a wafer with approximate spatial temperature uniformity undergoing rapid heating and cooling in a multilamp RTP chamber. The model is verified experimentally for a range of operating temperatures from 400° C to 900° C and pressures of 1 Torr and 1 atmosphere in an inert N2 environment. Theoretical predictions suggest model validity over a still wider range of operating conditions. One advantage of the low-order model over previous high-order and statistical models is that the proposed model contains a small number of fundamental parameters and functions that, if necessary, are easily identifiable. Furthermore, because of reduced computational complexity, the low-order model can be used in real-time predictive applications including signal processing and process control design.

Transient effects in rapid thermal processing

Using a realistic model of a rapid thermal processing chamber including Navier-Stokes calculations of the gas losses, the stresses and yield strengths of silicon wafers were determined for several linear ramp rates. It was found that the stress to yield strength ratio is a sensitive function of the ramp rate and the radiant uniformity. Radiation patterns that produce good steady-state thermal nonuniformity overheat the wafer edges during heating transients, leading to high stress levels.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Observation of silicon wafer emissivity in rapid thermal processing chambers for pyrometric temperature monitoring

The emissivity of silicon wafers in a rapid thermal processing chamber has been measured as a function of the wafer temperature. Wafers with different surface roughness and layers have been studied. For transparent wafers, both sides of the wafer affect the emissivity. This emissivity is not only affected by surface roughness, but also by the layers deposited on the wafer. It has also been observed that while the emissivity increases rapidly as the temperature increases from its room value to 600 °C, the emissivity decreases with a slope of −8.89×10−5 °C−1 for temperatures larger than 600 °C.

An inexpensive, flexible temperature controller for rapid thermal processing chambers

New research has shown significant advantages in fast, high temperature processing of semiconductors. Thus there is now a demand for more stringent temperature control. This paper outlines a design for such a controller that is inexpensive to build and yet gives excellent performance over a wide range of application.