Rapid Thermal Processing Process Research Articles

Rapid Thermal Processing and Improved Photocatalysis of Bi2O3-BaTiO3 Heterojunction

Bi2O3-BaTiO3 heterojunction with high photocatalysis efficiency was directly synthesized by rapid thermal processing (RTP). Bi2O3 and BaTiO3 were mixed in ratio and treated by RTP and conventional thermal processing (CTP), respectively. RTP samples have obvious Bi2O3 diffraction peaks, while CTP samples show pure BaTiO3 tetragonal perovskite. More small particles and layered existed in RTP samples. Photodegradation of MB solutions shows that RTP can promote photocatalytic efficiency. Its main lies in the following points: RTP can remove grain boundary defects by strengthening the bond grains; RTP can limit the solution region of the two substances to a certain range to get the best built-in electric field width; and RTP can strengthen the tetragonal BaTiO3 phase to hasten ion movement. Therefore, RTP can achieve much higher photocatalytic efficiency by improving the build heterojunction. This work provides a direct and efficient route to get improvement and high performance of heterojunction.

Shallow junction formation via lateral boron autodoping during rapid thermal process

Autodoping is a well-known phenomenon of unwanted dopant transfer in silicon epitaxy process. In this work, we discovered boron lateral autodoping in normal rapid thermal process (RTP) and used it to controllably form shallow junctions for device fabrication. The redeposition of boron from the gas phase to the solid surface was identified to be the limiting step of the boron incorporation into the undoped silicon area in the RTP process. At a given RTP temperature, boron autodoping could be increased by elevating the concentration of the boron source or enhancing the evaporation coefficient. Extending the annealing time can substantially improve the uniformity of the boron concentration in the gas phase, thus reducing the pattern dependence of the autodoping results. In addition, the autodoping process also avoids the traps and defects induced by ion implantation. Therefore, the described mechanism holds great promise for shallow junction formation in selectively patterned area with low cost.

Formation of a gate dielectric of nanometer thickness by rapid thermal treatment

Investigations of the thickness and optical characteristics of thin SiO2 films obtained by one-, two-, or three-stage rapid thermal processing (RTP) at atmospheric pressure, pulses of 6, 12, and 20 s duration have been carried out. To obtain thin SiO2 films by the RTP method, N-type:Ph 4.5 Оhm/□ (100) silicon wafers were used as initial samples. The samples were preliminarily oxidized at 1000 °C of the obtained wet oxygen (SiO2 d = 100 nm), then the silicon oxide was completely removed in a solution of hydrofluoric acid, after which the wafers were subjected to chemical cleaning using the Radio Corporation of America (RCA) technology. Oxidation in a stationary oxygen atmosphere was carried out in one or two stages by heating the plates with a light pulse of different power up to maximum temperatures of 1035 – 1250 °C, as well as a three-stage process, where the final stage was annealing in a nitrogen atmosphere or in a forming gas (N2 97% + H2 3%). The characteristics of SiO2-Si barrier structures nitrided in N2, obtained by the RTP process by light fluxes with pulses of a second duration, were studied to improve the electrophysical parameters of gate oxides by the RTP method. It is of interest for integrated circuits (ICS) with a high density of the active regions of devices.

Cooling rate dependence of Ni-catalyzed transformation of amorphous carbon into graphene in rapid thermal processing: An experimental and reactive molecular dynamics study

Amorphous carbon with Ni as catalyst can be transformed into graphene on the dielectric substrate directly without the subsequent transfer process during rapid thermal processing (RTP). However, the effect of cooling rate on this transformation process is still not fully understood yet, leading to the controversy of underlying mechanism. Here, by the combined reactive molecular dynamics simulation with experimental approach, we investigated the evolution of RTP graphene structure and diffusion behavior of C atoms with cooling rates. Results demonstrated that for each case, there were no C atoms precipitated from C-Ni intermixing layer during the cooling process, which was different from the behavior observed in the Ni-catalyzed CVD growth process of graphene. This confirmed that the a-C-to-graphene transformation mechanism during the RTP process was dominated by the C diffusion and Ni-induced crystallization rather than the traditional dissolution/precipitation mechanism for graphene growth. Most importantly, it was also found that tailoring the cooling rate could achieve the regular arrangement of distorted structure in as-grown RTP graphene and thus promote the high-quality synthesis of graphene, which was confirmed by the experimental result.

FORMATION OF PLATINUM SILICIDE LAYERS DURING THE RAPID THERMAL PROCESSING OF THE SYSTEM PLATINUM-SILICON: STRUCTURAL-PHASE CHANGES

The paper presents the performed investigations of the structural-phase changes of the platinum-silicon system during rapid thermal processing (RTP) in the nitrogen medium within the temperature range from 200°C to 550°C with a step of 50 K and the time duration of 7 s. High effectiveness of the RTP process was demonstrated for formation of the thermally stable platinum silicides in the nanodimensional film (40 nm Pt)/(Si 111) substrate system. Within the temperature range of 200°C ≤ T ≤ 300°C during 7 s of the RTP process on the border of the → metallic film with the substrate there grows the Pt2Si layer at the expense of the Pt atoms diffusion into silicon through the layer of the growing silicide. It is peculiar for the temperature T = 300°C to use completely the film of Pt for 7 s in the process of the silicide formation of the single-phase system of Pt2Si. At 350°C ≤ T < 450°C formation is registered of the double-phase system of Pt2Si PtSi, starting from the interphase boundary of Si/Pt2Si predominantly at the expense of the oncoming diffusion of Si atoms into the layer of Pt2Si. The RTP temperature T = 450°C marks formation of the thermally stable structure of PtSi along the entire thickness of silicide, which is 50-100°C lower and substantially faster, than during the continuous furnace thermal treatment (FTT).

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τeff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τRTP) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τRTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τd) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Physical properties of highly crystalline CIS layer prepared using single phase electrodeposition and low temperature RTP annealing

CuInSe2 nanoparticles (CIS-NP) were synthesized on ITO-coated glass substrate by electrodeposition and rapid thermal processing (RTP). The as-deposited films were annealed under argon atmosphere at 250 °C, 350 °C and 450 °C using RTP during a short annealing time. The latter is practicable to avoid further losing of the Se content in CIS films. In order to analyze the effect of annealing temperature, the structural, morphological, optical and electrical properties were investigated by means of X-ray diffraction, scanning electron microscopy, UV–Visible Spectroscopy and Mott-Schottky plots respectively. XRD results show that elaborated films have a tetragonal chalcopyrite CIS with preferential orientation along the (112) orientation. The phase formation of CIS-NP with good crystallinity was observed at low annealing temperature. Optical absorption studies indicate a direct band gap around 1.02 eV at 250 °C. The optical constants such as refractive index n(λ) and extinction coefficient k(λ) were estimated using an appropriate optical model. To determine the doping type of elaborated semiconductor, its flat band potential and the free carrier concentration we used the Mott-Schottky plots. A new attempt to anneal the electrodeposited CIS films by short annealing duration using RTP process was proved to be a useful method to synthesize polycrystalline CIS films for solar cell application.

Effect of selenization temperature on the crystalline and electrical properties of Cu2SnSe3 thin films obtained from rapid thermal process

In this paper, effect of selenization temperature on the crystalline and electrical properties of Cu2SnSe3 (CTSe) thin films obtained from rapid thermal processing (RTP) has been studied. X-ray diffraction and scanning electron microscope results indicated that the crystallinity of CTSe thin film is improved with the increase of selenization temperature. X-ray diffraction and Raman analysis revealed that the CTSe thin films without secondary phase were obtained at a growth temperature above 600 °C. A decrease of the element Tin (Sn) in the RTP process is observed as substrate temperature is increased from 550 to 700 °C. The band gap the CTSe thin films is between 0.87 and 0.91 eV distinguished by the selenization temperature. The CTSe thin films showed p-type conductivity with carrier concentrations of 1017–1021 cm−3. Hole mobility of the CTSe thin films were found to range between 4.48 and 23.6 cm2 V−1 s−1. Electrical properties improved significantly because of the RTP temperature increased.

Controlled activation of ZnTe:Cu contacted CdTe solar cells using rapid thermal processing

Back contacts can significantly limit CdTe solar cell performance, reducing both open circuit voltage (Voc) and fill factor (FF). Copper is an essential component of effective back contacts, but its presence in the CdTe absorber creates detrimental recombination centers. Rapid thermal processing (RTP) is demonstrated as a highly effective approach for reducing back contact barriers in CdTe solar cells contacted with ZnTe:Cu buffer layers, substantially improving both FF (>73%) and Voc (>850mV). Current density and quantum efficiency remain essentially unchanged, but a five-fold increase in minority carrier lifetime is observed which is attributed to passivation of recombination sites in the back contact region. Quantitative analysis of secondary ion mass spectrometry shows that the majority of Cu segregates to the Au metallization layer and that the ZnTe buffer appears to inhibit the Cu diffusion into CdTe. 3D imaging of the back contact region using atom probe tomography shows that optimized devices are characterized by preferential segregation of copper to both the Au|ZnTe and CdTe|ZnTe interfaces, perhaps in the form of CuxTe. With its low thermal budget the RTP process has been successfully applied to multiple device architectures.

Formation of CuInSe2 absorber by rapid thermal processing of electron-beam evaporated stacked elemental layers

Copper indium diselenide (CuInSe2) film was formed using the rapid thermal process (RTP) of electron-beam (E-beam) evaporated Cu–In stacked elemental layers as an absorber layer for chalcopyrite solar cells. The E-beam evaporation method could accurately control the thickness of each elemental layer so that the chemical composition of Cu–In precursor could also be controlled by changing the thickness ratio of the Cu/In metal layer. The device-quality Cu-deficient CuInSe2 film was obtained when the thickness ratio of Cu/In was about 1/2.5. Otherwise, the RTP process time was also certified as one of the most important parameters of RTP when the temperature was over 550 °C. A single-phase CuInSe2 was successfully obtained after rapid thermal process under 580 °C for 3 min. Finally, the growth mechanism of CuInSe2 film during RTP process was also summarized.

Phosphorus gettering of precipitated Cu in single crystalline silicon based on rapid thermal process

In this paper, we have investigated the effect of phosphorus diffusion gettering on the precipitated Cu in silicon via rapid thermal process (RTP). It is found that, for dot-like or star-like precipitates, the RTP-based phosphorus diffusion technique is efficient for gettering out the precipitated Cu. A two-step RTP gettering process is much more effective than a single-step RTP process. Furthermore, the choice of oxygen ambient can enhance the Cu gettering efficiency due to the involvement of considerable self-interstitial silicon atoms. The minority carrier lifetime of the sample subjected to RTP-based phosphorus gettering has also been verified to be significantly enhanced. These results are of interest for the gettering engineering of high-efficiency silicon solar cells.

Pressure Dependent Rapid Thermal Processing of CuInS2 Thin Films Investigated by In-Situ Energy Dispersive X-ray Diffraction

AbstractThe rapid thermal processing (RTP) of Cu-rich Cu/In precursors for the synthesis of CuInS2 thin films is possible within a broad processing window regarding leading parameters like top temperature, heating rate, and Cu excess. The key reaction pathway for the CuInS2 phase formation has already been investigated by in-situ energy dispersive X-ray diffraction (EDXRD) for various precursor stoichiometries, heating rates and top temperatures at sulphur partial pressure conditions which are typical for physical vapour deposition processes. According to the phase diagrams of the binary sulphide phases, the sulfur partial pressure strongly determines the occuring crystalline phases. However, a controlled variation of the maximum sulphur partial in a typical RTP experiment has not been carried out yet. In order to study the influence of this parameter a special RTP reaction chamber was designed suitable for in-situ EDXRD experiments at the EDDI beamline at BESSY, Berlin. In a typical in-situ RTP/EDXRD experiment sulphur and a Cu/In/Mo/glass precursor are placed in an evacuated graphite reactor. The amount of sulphur determines the maximum pressure available at the top temperature of the experiment. As the RTP process proceeds a complete EDXRD spectrum is acquired every 10 seconds and thus the various stages of the reaction path and the crystalline phases can be monitored. The first experiments show already a significant change in the reaction pathway and the secondary Cu-S phases which segregate on top of the CuInS2 thin film during the reaction.

Oxide Grown on Polycrystal Silicon by Rapid Thermal Oxidation in N2O

In this paper, rapid thermal processing (RTP) polyoxides were studied in terms of oxidation temperature and thickness with oxidation polyoxides as comparison. Atomic force microscopy, transmission electron microscopy, and secondary ion mass spectroscopy measurements were employed to correlate the electrical characteristics with the physical structures. Results showed that RTP -grown polyoxides exhibited better characteristics on the leakage current, , trappings and . It was found that it was the proper amount of nitrogen incorporated in the polyoxide improving the interface of the polyoxide/polysilicon, consequently improving the electrical quality. The initial hole-trapping phenomenon during the constant current stress, which was due to the incorporated nitrogen, was also observed in the -grown polyoxides. The two-step RTP process, i.e., first RTP oxidizing the polysilicon in and then RTP oxidizing in , could achieve polyoxide of good characteristics by incorporating the proper amount of nitrogen into the polyoxide.

Electrical characterization of NiSi/Si interfaces formed by a single and a two-step rapid thermal silicidation

This paper investigates the electrical characteristics of NiSi Schottky barrier diodes (SBD). A single-step rapid thermal process (RTP) and a two-step RTP were employed to form the SBDs. The diode structures were designed so as to minimize edge leakage. The two-step silicidation process resulted in a significant reduction of the reverse leakage current density, suggesting an improvement of the interface characteristics. Temperature-dependent current–voltage measurements were used to analyse the interface characteristics. The two-step RTP process reduces the density of non-ideal micro-contacts with low barrier height, which are responsible for the reverse leakage current.

SIMS study on N diffusion in hafnium oxynitride

As the MOS device feature size continues to shrink, novel high- k gate dielectrics should be adopted to reduce the unacceptable high gate leakage current due to direct tunneling. HfO 2 is one of the most promising high- k materials. It was reported that HfN x O y formed by incorporating N into HfO 2 could improve the thermal stability and electrical properties of the gate dielectric films. However, N loss can occur due to subsequent high temperature processes, such as rapid thermal processing (RTP). It is necessary to understand the mechanism of N loss from the academic and application points of view. In this study, SIMS was applied to investigate the N diffusion behavior in sputter-deposited HfN x O y after RTP processing. The results showed that N loss is due to out-diffusion of N to the surface. On the other hand, segregation of N at the interface of HfN x O y /Si was observed. N acts as a good barrier to O diffusion from HfN x O y to Si. The results show that oxygen flooding is unfavorable for characterizing N in HfN x O y /Si since oxygen flooding can enhance the N background.

Optimisation of a combined transient-ion-drift/rapid thermal annealing process for copper detection in silicon

The transient ion drift (TID) technique has been recently proposed for copper trace detection in silicon. Cu atoms may be present either in the vicinity of the Si surface or within the volume. In the latter case they are either gathered at secondary defects or form precipitates believed to be silicides. In order to become detectable by TID Cu atoms must be put into the highly mobile interstitial state. Depending on the initial configuration of the Cu/Si system different physical mechanisms may enable Cu atoms to become ‘TID active’. In this work we study the Cu activation process using rapid thermal processing (RTP) in an attempt to minimise the thermal budget required to achieve a complete activation. Both, surface and volume contaminated samples are investigated. During RTP treatments the activation of surface Cu atoms is found to proceed significantly faster than during standard furnace anneal. We tentatively attribute this behaviour to the UV light exposure associated with the RTP, which may enhance the release of copper atoms from the surface. The dissolution kinetics of the Cu precipitates occurring during RTPs are found to be only limited by Cu diffusion. The RTP/TID process is used to study the low temperature reaction path of supersaturated Cu. If prior to the RTP process, Cu atoms are chemically removed from the surface or near surface region, TID measures only the residual bulk Cu atoms. Our results show that out-diffusion and near-surface precipitation are reducing mostly the copper supersaturation.

Characterization of Si(1 1 1) crystals implanted with Sb + ions and annealed by rapid thermal processing

Monocrystalline Si(1 1 1) targets are implanted (at room temperature) with antimony ions at 120 keV energy to 5×10 14 or 5×10 15 Sb + cm −2 dose. The samples are heat treated by means of rapid thermal processing (RTP) at 1000 °C during 60 s, under nitrogen atmosphere. In this work, we report the measured evolution of the silicon surface damage and the radiation damage recovery in relation to antimony dose and RTP processing. We also study the behavior of antimony dopant into Si(1 1 1) specimens. The investigation is carried out by He + Rutherford backscattering spectrometry (RBS; operating at 1.57 MeV energy in both random and channeling modes), X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It is shown that a good surface damage recovery is obtained for all the annealed samples. However, after RTP, a significant loss of antimony has occurred for the specimens which are implanted with 5×10 15 Sb + cm −2 dose. This suggests an antimony out-diffusion. Finally, a good morphological characterization of the specimens is provided by AFM.

Precise chemical analysis development for Si and GaAs surfaces

Precise chemical analysis (PCA) was developed to allow the study of non-interconnected atoms on crystalline semiconductor surfaces, such as those produced during rapid thermal processing (RTP) of silicon and electron beam lithography on gallium arsenide (GaAs). The PCA method is based on selectively dissolving the different components present on the semiconductor surface using preferential etchant solutions. After etching, the etchant solution, containing the etched component, is analyzed by a photometric technique. In this paper, we present photometric measurements of the amount of “free” (non-interconnected) atoms that remain on semiconductor surfaces following electron beam and RTP processing. In this context, “free” atoms are those presenting in any form other than crystalline GaAs or Si, for instance, those in the form of surface oxides. Using the PCA method, free Ga and As were detected on GaAs surfaces after electron beam lithography. Free silicon, boron and phosphorous atoms were found on silicon surfaces after RTP. The concentration of boron diffused into a silicon wafer during RTP was also carried out by means of slight surface etching. We estimate the accuracy of this PCA method at 2% for Ga and 5% for all other elements.

Model-based control in rapid thermal processing

In single wafer rapid thermal processing (RTP), the process recipe is characterized by high ramp rates and short high temperature holds. In this paper, the development of temperature control algorithms for the RTP process is discussed. A model-based controller based on a physically-based macroscopic model developed from first principles is presented. The model-based controller is compared to an empirically determined controller and is shown to perform favorably towards meeting very stringent specifications.

Advanced salicides for 0.10 μm CMOS: Co salicide processes with low diode leakage and Ti salicide processes with direct formation of low resistivity C54 TiSi2

The scaling of CMOS technologies to 0.10 μm and beyond imposes increasingly demanding constraints to self-aligned silicide (salicide) processes. For high performance devices, it is essential that salicide processes achieve low gate and source-drain sheet resistance as well as low silicide to source-drain diffusion contact resistance, and maintain low junction leakage. This becomes increasingly difficult as junction depths and linewidths are scaled. In this paper we present an overview of the development of advanced Ti and Co salicide processes, with implementations into a high performance 0.10 μm complementary metal-oxide-semiconductor (CMOS) technology. For Co salicide, the main scaling issue is diode leakage on shallow junctions. We show that the use of pre-amorphization implants or a pre-Co deposition sputter etch improves diode leakage distributions, but fails to eliminate high leakage outliers. Co deposition temperature and rapid thermal processing (RTP) variables were found to have a strong effect on diode leakage, with optimization of either one resulting in tight low leakage distributions on shallow junctions. For conventional Ti salicide processes, the main scaling issue is sheet resistance on narrow lines due to incomplete high resistivity C49 TiSi2 to low resistivity C54 TiSi2 transformation. We present X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM) studies that indicate that direct growth of C54 TiSi2 bypassing the C49 phase is achieved at low temperatures on polycrystalline or amorphous Si with the addition of Mo impurities, eliminating the narrow line effect. The mechanism is demonstrated to be nucleation of MoSi2 and an unidentified phase at the Ti/Si interface, followed by epitaxial growth of C54 TiSi2 on these templates. Ti salicide processes with Mo impurities were evaluated, demonstrating an optimized one-step RTP process combining Mo and pre-amorphization implants that maintains low sheet resistance to 0.06 μm gate lengths. Successful implementations into a 0.10 μm flow were achieved both for optimized Co salicide or Ti salicide processes.