As high-throughput omics technologies continue to advance, researchers are facing the challenge of a rapid surge in proteomics, metabolomics, and genomics data. This growth not only necessitates more disk space and network bandwidth, but also complicates data sharing and subsequent analysis. To address this challenge and enhance the analytical efficiency of downstream software, we propose Dear-OMG, a unified, compact, flexible, and high-performance metadata storage solution. Dear-OMG introduces a novel file storage structure and utilizes the Elias-Fano encoding algorithm to compress and store proteomics, genomics, and metabolomics metadata into the unified OMG format. The OMG format not only demonstrates remarkably high compression and decompression speeds, but also enables parallel random access to any data block. Test results reveal that, compared to the commonly used proteomics formats of mzXML and mzML, the OMG format achieves an 80% reduction in storage space, a 90% decrease in conversion time, and approximately a tenfold speed improvement with support for parallel random access. Dear-OMG is freely available at https://github.com/jianweishuai/Dear-OMG .

Abstract We review two magnetic tunnel junction (MTJ) approaches for compact, low-power, CMOSintegrated true random number generation (TRNG). The first employs passive-read, easy-plane superparamagnetic MTJs (sMTJs) that generate thermal-fluctuation-driven bit streams at 0.5-1 Gb/s per device. The second uses MTJs with magnetically stable free layers, operated with stochastic write pulses to achieve switching probabilities of about 0.5 (i.e., write error rates of ≃ 0.5), achieving ≳ 0.1 Gb/s per device; we refer to these as stochastic-write MTJs (SW-MTJs). Randomness from both approaches has been validated using the NIST SP800 test suites. sMTJ approach uses a read-only cell with low power and can be compatible with most advanced CMOS nodes, while SW-MTJs leverage standard CMOS MTJ process flows, enabling co-integration with embedded spin-transfer torque magnetic random access memory (STT-MRAM). Both approaches can achieve deep sub-0.01 µm 2 MTJ footprints and offer orders-of-magnitude better energy efficiency than CPU/GPU-based generators, enabling placement near logic for high-throughput random bit-streams for probabilistic computing, statistical modeling, and cryptography. In terms of performance, sMTJs generally suit applications requiring very high data-rate random bits near logic processors, such as probabilistic computing or large-scale statistical modeling. Whereas SW-MTJs are attractive option for edge-oriented microcontrollers, providing entropy sources for computing or cryptographic enhancement. We highlight the strengths, limitations, and integration challenges of each approach, emphasizing the need to reduce device-to-device variability in sMTJs-particularly by mitigating magnetostriction-induced in-plane anisotropy-and to improve temporal stability in SW-MTJs for robust, large-scale deployment.

Abstract The magnetic random access memory (MRAM) architecture, comprising nonvolatile, fast, and energy-efficient magnetic tunnel junctions (MTJs), presents a promising platform for implementing native in-memory and neuromorphic computing tailored for edge AI applications. Integrating the MTJ-based neural network of neurons and synapses within the MRAM architecture overcomes the conventional von Neumann bottleneck, enabling computation to be performed directly where the data is stored. Here, we present an overview of MTJ technologies proposed for artificial neural networks, specifically focusing on the recent advancements in the compound MTJ concept. The compound MTJ − comprising an array of MTJ cells on a 3-terminal spin-orbit torque device structure − is capable of hosting multiple resistance states and tunable conductance levels, which are well-suited for emulating the flexibility and plasticity of artificial synaptic weights. We highlight developments on compound MTJ designs with demonstrable multistate stability, and enhanced synaptic strength and resolution through the bimodal tuning of tunnel magnetoresistance and discrete states. Next, we discuss a promising strategy to expand the switching voltage window between successive states through planar rotations of constituent MTJs, engendering low write errors and high synaptic tolerance. Finally, we discuss emerging material platforms − field-immune, low-power antiferromagnets and altermagnets − as enablers of high density, multistate compound MTJs scalable and robust in-memory and
neuromorphic computing technologies.

Their excellent performance and compatibility with CMOS technology, while the OXRAM (Oxide-based CMOS Resistive Random Access Memory) technique used in CMOS transistors presents challenges in terms of device unpredictability and scalability, also offers potential advantages such as higher endurance, lower power consumption, and quicker reading and writing operation speeds when compared to traditional Flash memory. The inability of conventional SRAMs to store data after powering off limits their use in battery-operated mobile devices and other applications where non-volatility related to zero leakage currents is required. In the article, a new OXRAM-based Non-Volatile SRAM (NVSRAM) device is presented. It is suggested to compare the performance of SRAM with NVSRAM at the memory and cell levels. Learning is crucial for the brain's ability to adapt to changing conditions. A synaptic connection table in an external memory at a local routing node is used to learn a rule in the address domain for neuromorphic architecture. A number of parameters are compared, including design complexity, leakage current values (SRAM cells are 3.4µA, 7.4nA) and (NVSRAM-based OXRAM are 2.7 µA, 5.9nA) at 180nm and 90nm, and energy saving or power usage values (SRAM cells cell are 5.5 µA, 10.5nA) and (NVSRAM based OXRAM are 4.9 µA, 9.8nA) at 180nm and 90nm. The circuits that are being described can be realized using far-above ground voltage CMOS Cadence tools at 180 nm and 90 nm.

Enhanced reliability of HfO2-based conductive bridge random access memory through MgO insertion

With the development of artificial intelligence and flexible electronics, MXene-based memory devices have gained widespread attention due to their excellent performance. However, the traditional MXene-based memory device often requires high-temperature annealing processes, which hinder their application of memory devices in flexible electronics. Here, we demonstrate the use of a one-step process oxygen plasma (O plasma) irradiation process to induce controlled defects for fabricating MXene-based memory devices directly on a flexible polyimide substrate. The resulting memory device exhibits stable resistive switching behavior with a high switching ratio (∼7.8 × 104), low power consumption (∼49.8 nW), excellent retention performance (30 days), and multi-level storage capability. Additionally, the device maintained high stability after multiple bending tests and shows no significant degradation even after three months of ambient exposure without encapsulation. This work provides a viable strategy for developing flexible, high-performance memory device with high controllability.

Effects of physical vapor deposition methods on the microstructure of CuI and directional transport in resistive random access memories

Design and analysis of multi-layer ZrO2-based resistive random access memory (RRAM) for next-generation non-volatile memory

Memristors are promising electronic devices that can be used to create non-volatile resistive random access memory (RRAM) devices and/or neuromorphic computing systems. The densest packing of RRAM elements, promising for practical applications, is achieved in the crossbar architecture when the memristors are located at the intersections of perpendicular electrode buses. However, in such an architecture, sneak path current (parasitic bypass current) problem arises, affecting the correct functioning of the elements of the crossbar matrix. This problem can be solved by adding a transistor that provides isolated access to each memristor element (1T1R architecture). However, in order to refine the manufacturing technology of such devices from both memristor (optimal layer materials and geometry) and access transistor (types and required characteristics) sides, it is necessary to correctly measure the characteristics of simpler passive (1R) arrays of memristors. This work proposes three measuring circuits for solving this problem with their advantages and disadvantages analyzed. It is shown that a combined approach to measuring various memristive characteristics is preferable. The results of the work will be useful in the study of passive arrays of crossbar memristors, including when developing the technology for creating arrays with the 1T1R architecture.

High-Rate Uncoordinated Concurrent Random Access in Underwater Acoustic Networks

As magnetoresistive random access memory (MRAM) technology becomes increasingly vital for emerging applications, such as artificial intelligence, the development of cost-effective and miniaturized solutions is essential. van der Waals (vdW) magnets, which can be vertically stacked with various functional blocks, offer promising potential to enhance the performance and scalability of memory devices. Nevertheless, the need for perfect alignment between adjacent layers and finite local interactions at the interfaces often complicates device architectures and leads to high power consumption. Addressing these challenges, a new device configuration with partial overlap while maintaining the global effect would be a promising scheme. Here, using Fe3GeTe2/MnBi2Te4 (FGT/MBT) as a paradigm, the global-pinning exchange bias (GPEB) effect is successfully achieved with a horizontal pinning distance approaching 100 µm. Specifically, once stacking a small-area MBT on FGT, the entire FGT is fully biased due to magnetic couplings inherent to vdW magnets, as confirmed by the theoretical model. Interlayer coupling and coverage ratio provide additional degrees of freedom to manipulate the GPEB. Remarkably, this emergent GPEB effect is prevalent across vdW heterostructures composed of various vdW magnets. This work expands design flexibility and offers strategies for constructing new in-memory computing devices, opening exciting possibilities for future spintronic applications.

Abstract: The growing demand for energy-efficient memory in sub-threshold computing environments, especially in IoT and embedded systems, necessitates the development of optimized SRAM architectures. Traditional 6T and 8T SRAM cells suffer from high leakage power, increased latency, and poor scalability. This work presents two novel design methodologies to address these limitations. The first incorporates Transmission Gate (TG) logic to improve read access stability and reduce delay. The second integrates a dynamic power gating scheme to minimize leakage power and enhance overall energy efficiency. The proposed designs are modeled and evaluated using the Tanner EDA tool with 45nm technology files. Simulation results demonstrate over 80% reduction in latency and significant power savings compared to conventional SRAM designs, highlighting the architecture’s suitability for low-power, high-performance applications in modern SoC and IoT systems. Keywords: Static Random Access Memory (SRAM), Transmission Gate Logic, Power Gating, Low-Power VLSI, Sub-Threshold Operation, IoT, Tanner EDA, 90nm Technology

Abstract Phase-Change Random Access Memory (PRAM) is a high-speed, non-volatile memory technology that utilizes the reversible phase transitions of materials such as Ge-Sb-Te (GST) between amorphous and crystalline states. This paper provides an in-depth analysis of PRAM’s fundamental operating principles, including rapid switching, high endurance, and multilevel storage capabilities enabled by precise phase transition control. Advances in materials, such as doping and superlattice-like structures, are highlighted for their roles in enhancing thermal stability, endurance, and energy efficiency. The paper also explores PRAM’s potential in neuromorphic computing, emphasizing its ability to emulate biological synaptic functions, including synaptic weight modulation, spike-timing-dependent plasticity (STDP), and long-term potentiation/depression (LTP/LTD). The integration of PRAM into crossbar arrays and multi-memristive synapses is discussed to develop scalable, energy-efficient neural networks for artificial intelligence applications. Key challenges, including sneak currents, endurance degradation, and power consumption in large-scale arrays, are examined alongside solutions such as selector devices, advanced thermal management, and processing-in-memory architectures. These innovations position PRAM as a critical technology for next-generation memory and neuromorphic systems, enabling energy-efficient and scalable computing architectures for future applications.

Relationship between hydrogen diffusion and negative-SET occurred in resistive random access memory with inert electrode

The implementation of a quantum router capable of performing both quantum signal routing and quantum addressing (a Q 2 -router) represents a key step toward building quantum networks and quantum random access memories. We realize a Q 2 -router that uses fixed-frequency transmon qubits to implement a routing protocol based on two native controlled- i gates. These gates leverage a large Z Z interaction to selectively route information according to a quantum address. We find an estimated average routing fidelity of 95.3 % , with errors arising primarily from decoherence or state preparation and measurement. We present a comprehensive calibration and characterization of both the c- i gates and the overall routing protocol through randomized benchmarking techniques and state tomography.

When the demand for real-time data processing and energy keeps efficiency growing in fields like Advanced Driver-Assistance Systems (ADAS) for electric vehicles, in-memory computing (IMC) is becoming a key technology. The heart of effective IMC is Static Random Access Memory (SRAM). It is widely known for its fast access times and low power requirements. For these reasons, SRAM becomes an ideal choice for FPGA-based systems. This paper delves into optimizing SRAM for IMC by comparing the performance, power efficiency, and stability of three SRAM types: 6T, 8T, and 10 T. Whats more, we introduce the innovative C3SRAM architecture. This technology leverages capacitive coupling to boost computational speed and energy efficiency significantly. Finally, we summarize the CONV-SRAM architecture, tailored for in-memory convolution operations in neural networks. Through these explorations, we provide practical insights into how SRAM can be optimized to meet the demands of high-performance, energy-efficient systems, focusing on applications like autonomous vehicles that require speed and power conservation.

Machine Learning Assisted Random Access in LEO Satellite-Based Internet of Things

The development of high-density, field-free spin–orbit torque (SOT) magnetic random access memory (MRAM) at sub-5 nm technology nodes is crucial for next-generation memory technologies. Here, we propose a novel cylindrical magnetic tunnel junction (C-MTJ) architecture, where a nano-shell free layer coaxially surrounds a central heavy-metal nanorod. Through a synergistic approach combining atomistic spin dynamics, micromagnetic simulations, and analytical modeling, we establish the magnetic ground state phase diagram for this geometry down to a 3 nm radial dimension, identifying the out-of-plane Z-state as a stable and scalable configuration. We demonstrate that a single 50 ps current pulse can trigger deterministic, field-free magnetization reversal in under 500 ps, showcasing the C-MTJ’s potential for ultrafast operation. Furthermore, we employ a deep neural network as a surrogate model to rapidly optimize device performance, revealing a design pathway to reduce the critical switching current by an order of magnitude. This C-MTJ design, with its unique 3D geometry and efficient SOT switching, offers a promising pathway toward ultrafast, high-density MRAM and neuromorphic devices.

Amplicon sequencing enables taxonomic profiling of microbial communities but offers limited insight into their functional potential. Existing tools such as Phylogenetic Investigation of Communities by Reconstruction of Unobserved States (PICRUSt2) infer functions through phylogenetic placement and ancestral state reconstruction; however, these methods are computationally intensive and inefficient for large-scale data sets. To address these challenges, we introduce microbiome graphics processing unit (GPU)-based function inference (MGFunc), an ultra-high-throughput framework for microbiome functional inference leveraging multi-GPU acceleration. MGFunc transforms functional prediction for amplicons into standardized matrix multiplication using a pre-constructed genomic content network. It further integrates split data loading, matrix partition, and dynamic scheduling across multiple GPUs, enabling scalable, batch-wise analysis of millions of samples under limited GPU memory and system random access memory (RAM). Compared to PICRUSt2, MGFunc achieves speedups of up to several hundred thousand times, completing the functional interpretation of one million samples within one minute by four GPUs on a single server. This work provides a highly efficient and low-latency solution for ultra-large microbiome data sets functional inference, paving the way for global-scale microbiome studies. The MGFunc software is freely accessible at https://github.com/qdu-bioinfo/MGFunc.IMPORTANCEUnderstanding what microbes do-their functions-is essential for studying health, disease, agriculture, and the environment. While cost-effective sequencing methods like 16S rRNA gene analysis are widely used, they do not directly reveal microbial functions. Existing tools that predict these functions from 16S data are often too slow for today's large studies involving hundreds of thousands of samples. In this work, we developed microbiome graphics processing unit (GPU)-based function inference (MGFunc), a new method that predicts microbial functions quickly and accurately by using GPUs and a streamlined mathematical approach. MGFunc can analyze over one million samples in under a minute, making it one of the fastest tools available. This enables researchers to study the functional potential of microbial communities on a truly global and population scale.

Relevance. The increase in the number of terminals and the intensity of connections in satellite communication networks with the «star» topology actualizes the problem of choosing an effective mechanism for accessing a common radio channel. The well-known approaches of deterministic and random access have significant limitations. At the same time, there are no clear analytical criteria for choosing between mechanisms depending on the load, which makes it difficult to optimize network performance. Purpose (research): The aim is to compare the effectiveness of two mechanisms for entering satellite terminals into a network with the "star" topology: with specific slot access and with random access. The assessment is aimed at identifying conditions under which one of the mechanisms is superior to the other in key performance indicators. Methods. The solution of the problem is based on a combination of analytical and simulation modeling. To evaluate the effectiveness of random access, a strict combinatorial derivation of the mathematical expectation formula for the number of slots selected by exactly one terminal was carried out. The verification of the analytical model was performed using stochastic modeling in Python. Result. A validated analytical model has been obtained that makes it possible to accurately predict the effectiveness of the random access mechanism. The data obtained is applicable in the design of satellite communication networks to optimize terminal entry time and channel resource allocation. The novelty elements are rigorous analytical inference and verification of the formula for the mathematical expectation of the number of successfully occupied slots with random access, which allows you to accurately predict performance without large-scale modeling. The novelty also includes the establishment of a quantitative criterion for choosing an access mechanism. The proposed model takes into account the real conditions of terminal competition for channel resources and is applicable to the analysis of protocols such as ALOHA and TDMA. Practical significance. The presented solution is proposed to be used in the design and adaptive management of the MAC layer in VSAT satellite networks, IoT systems and telemetry networks. The obtained criteria for selecting an access mechanism can be implemented as dynamic reconfiguration algorithms in software-configurable networks, allowing automatic switching between modes depending on the current load. This will ensure optimal use of bandwidth, minimize delays, and increase overall network stability.