Ramp-up Rate Research Articles

A Study of Energy Conversion Efficiency Versus Plasma Density by Lower Hybrid Current Drive in HT-7 Tokamak

Ramp-up experiments by means of lower hybrid wave on HT-7 superconducting tokamak have been performed and analyzed. A ramp-up rate of over 300 kA/s is obtained and a conversion efficiency of over 10% has been achieved during the ramp-up phase. The study of the dependence of conversion efficiency on plasma density shows that the conversion efficiency is affected by the driven current, which is mainly dominated by the competition of impurity concentration with wave accessibility condition. In addition, the effect of current profile may play an important role in determining the conversion efficiency.

Ultra Shallow Junction Formation with High Process Controllability Using Optimized Rapid Thermal Anneal Process

Implant and rapid thermal annealing (RTA) are investigated for a source/drain (S/D) formation process. Optimization of RTA conditions is the key for ultra shallow junction formation. This paper describes the ultra shallow junction formation using RTA. We investigate the effects of thermal budget such as ramp-up rate and ramp-down rate, oxygen content and cap films during the RTA process for achieving a shallow junction and low sheet resistance. In addition, we investigate the effects of these parameters on process controllability and on the combination of complementary metal-oxide-semiconductor (CMOS) fabrication. Using optimized RTA technology, shallow junctions with low sheet resistance and good process controllability for early 100 nm technology nodes can be achieved, even though problems remain with process controllability for wafers of various structures and with the trance enhanced diffusion (TED) effect of gate side-wall spacers.

Application of inverse problem algorithm for temperature uniformity in rapid thermal processing

This article presents a finite-difference-method formulation to the application of inverse problem algorithms for uniform temperature tracking of several different linear ramp-up rates in rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of silicon wafers are used. The required incident-heat-flux profiles for temperature uniformity across 300-mm-diameter 0.775-mm-thick silicon wafer were intuitively evaluated. Our numerical results indicate that temperature non-uniformity occurring during the ramp increase with the ramp-up rate. Although a linear ramp-up rate of 300 °C/s was used and random errors did reach 3.864 °C, the temperature over the wafer was maintained within 0.665 °C of the wafer center if the incident-heat-flux profiles were dynamically controlled according to the inverse results. These temperature non-uniformities could be acceptable in the advanced rapid thermal processing system.

Two-step-heating sequence in arsenic-free high-temperature surface cleaning method for GaAs–AlGaAs MBE

Reduction of the density of protrusions on a cleaned GaAs surface by arsenic-free high-temperature surface cleaning performed in the preparation chamber of a molecular beam epitaxy system was investigated. The density of protrusions was found to decrease when the temperature ramp-up rate of the substrate was reduced from 10°C/min to 1°C/min. Using a constant ramp-up rate of 1°C/min required approximately 10 h to reach 650°C. Consequently, a new two-step-heating sequence is proposed, in which the ramp-up rate is changed from 10°C/min to 1°C/min at 575°C and the total ramp-up time is reduced to 3 h. The roughness of the surface cleaned using the two-step-heating sequence was studied by atomic force microscopy and was found to be almost identical to that for the constant ramp-up rate of 1°C/min. X-ray photoelectron spectroscopy revealed that the stoichiometry of the cleaned GaAs surface was maintained and no excessive Ga was present on the surface. The electron mobility of two-dimensional electron gas in high-electron-mobility transistor grown on the GaAs substrate cleaned using the two-step-heating method increased at low temperatures by 50% beyond that grown on GaAs substrate that was cleaned using a constant ramp-up rate of 10°C/min.

Thermal uniformity of 12-in silicon wafer in linearly ramped-temperature transient rapid thermal processing

This paper presents a systematic method for estimating the dynamic incident-heat-flux profiles required to achieve thermal uniformity in 12-in silicon wafers during linearly ramped-temperature transient rapid thermal processing using the inverse heat-transfer method. A two-dimensional thermal model and temperature-dependent silicon wafer thermal properties are adopted in this study. The results show that thermal nonuniformities on the wafer surfaces occur during ramped increases in direct proportion to the ramp-up rate. The maximum temperature differences in the present study are 0.835/spl deg/C, 1.174/spl deg/C, and 1.516/spl deg/C, respectively, for linear 100/spl deg/C/s, 200/spl deg/C/s, and 300/spl deg/C/s ramp-up rates. Although a linear ramp-up rate of 300/spl deg/C/s was used and measurement errors did reach 3.864/spl deg/C, the surface temperature was maintained within 1.6/spl deg/C of the center of the wafer surface when the incident-heat-flux profiles were dynamically controlled according to the inverse-method approach. These thermal nonuniformities could be acceptable in rapid thermal processing systems.

ＩＴＥＲ‐ＣＳモデル・コイルとＣＳインサート・コイルの実験結果 ＩＴＥＲ中心ソレノイド（ＣＳ）モデル・コイル計画

The Central Solenoid (CS) Model Coil project was started in 1992 as one of the most important R & D programs in the International Thermal Experimental Reactor (ITER) Engineering Design Activity (EDA). The purpose is to confirm the design criteria and performance of the ITER conductor, to develop and verify manufacturing tooting and processes, and to verify material performance following fabrication processes. The CS model coil was fabricated by using full-size ITER CS conductor and consisted of an inner module of 10 layers and an outer module of 8 layers. The coil, which has an inner diameter of 1.58m, an outer module of 3.6m, and a height of 2.78m, including two 0.5m lead regions. The coil was completed in 1999 and tested at the CS model coil test facility in JAERI in 2000. It achieved successfully 13T at 46kA under the pulsed operation condition of 0.4T/s for a ramp-up rate and 1.2T/s for a ramp-down rate, which is targeted as development. And the CS insert, which was a one-layer solenoid to investigate the performance of the ITER conductor in detail, was constructed and tested by being installed inside the CS model coil. The inset was operated up to 13T with a ramp-up rate of 1.2T/s.

Effect of ramp rates during rapid thermal annealing of ion implanted boron for formation of ultra-shallow junctions

Over the last couple of years, manufacturers of rapid thermal annealing (RTA) equipment have been aggressively developing lamp-based furnaces capable of achieving ramp-up rates of the order of hundreds of degrees per second. One of the driving forces for such a strategy was the experimental demonstration of 30 nm p-type junctions using a ≈400°C/s ramp-up rate during a spike-anneal (zero soak-time at temperature). It was proposed that the ultra-fast ramp-up was suppressing transient enhanced diffusion (TED) of boron caused by implantation damage. Ultra-fast ramp rate capability was thus embraced as an essential requirement for the next generation of RTA equipment. In this paper, we review more recent experimental data examining the effect of the ramp-up rate during spike- and soak-anneals on enhanced diffusion and ultra-shallow junction formation. The advantage of increasing the ramp-up rate (above ≈50°C/s) is found to be appreciable only during spike-anneals of the shallowest implants. Since TED naturally decreases with decreasing implantation depth, it follows that the observed advantage of a fast ramp-up does not arise from a so-called suppression of TED but from a straightforward reduction of the thermal budget. Since the temperature ramp-down is in practice limited to a rate much smaller than the achievable ramp-up rates (≈75°C/s vs. ≈400°C/s, respectively), a point of diminishing return is quickly reached when attempting to decrease dopant diffusion by increasing the ramp-up rate only. The advantage of a fast ramp-up is similarly mitigated by the finite minimum soak-time achievable in practice, as well as by decreased process control at faster ramp-up rates. While it is apparent that spike-anneals can minimize dopant diffusion while maximizing dopant activation we find that some of the advantages offered by fast ramp-up rates can be duplicated via modification of the implantation parameters. A survey of spike-anneal daa from different sources supports this point.

Effects of ramp-up rates on the salicide process

Increases in the sheet resistance of TiSi2 with a decreasing linewidth has been attributed to incomplete transformation from high resistance C49–TiSi2 phase to the desired low resistance C54–TiSi2 phase. In this article, we investigate the effects of increasing the ramp up rate of the first rapid thermal anneal (RTA1) in the salicide process. Electrical testing and micro-Raman spectroscopy were used to investigate the C49-to-C54 phase transformation on poly lines with different linewidths. Samples were annealed with two different ramp-up rates in RTA1. From micro-Raman spectra, it is observed that increased ramp-up rate during RTA1 results in more C54–TiSi2 formed during the second rapid thermal anneal (RTA2). It is also shown that higher ramp-up rates result in lower sheet resistance for deep submicron poly lines.

Raman characterization of germanium nanocrystals in amorphous silicon oxide films synthesized by rapid thermal annealing

Raman characterization of germanium (Ge) nanocrystals embedded in amorphous silicon oxide (a-SiO2) films synthesized by rapid thermal annealing (RTA) has been carried out. The samples were prepared by cosputtering Ge and SiO2 targets using a rf magnetron sputtering machine. Ge nanocrystals can only be obtained from samples sputtered with six pieces of Ge attached to the SiO2 target. For samples annealed at different RTA temperatures, the Raman spectra indicated a transition from amorphous to nanocrystalline Ge when annealed between 600 and 750 °C. The spectra were analyzed in terms of phonon confinement model and the estimated nanocrystal size was between 20 and 66 Å. A minimum annealing time of 160 s at 750 °C was necessary for Ge nanocrystal formation. Strong visible broadband photoluminescence was observed from the nanocrystals and the photoluminescence showed a blueshift with decrease in the nanocrystal size. The effect of compressive stress on nanocrystal growth was examined by varying the rampup and rampdown rates of the RTA process. The compressive stress was shown to affect the growth of the nanocrystals.

Reconstruction of Current Profiles and q Profiles on the HL-1M Tokamak

The algorithm for reconstructing plasma current and safety factor profiles on a tokamak with an iron core transformer is given and applied to the analysis of experimental data. It is shown that a central negative magnetic shear region is realized througth ajusting the ramp-up rate of plasma current in ohmic discharges and through lower hybrid current drive on HL-1M tokamak.

Ultra-Shallow Junctions by Ion Implantation and Rapid Thermal Annealing: Spike-Anneals, Ramp Rate Effects

ABSTRACTOver the last couple of years rapid thermal annealing (RTA) equipment suppliers have been aggressively developing lamp-based furnaces capable of achieving ramp-up rates on the order of hundreds of degrees per second. One of the driving forces for adopting such a strategy was the experimental demonstration of 30nm p-type junctions by employing a ramp-up rate of ≈400°C/s. It was subsequently proposed that the ultra-fast temperature ramp-up was suppressing transient enhanced diffusion (TED) of boron which results from the interaction of the implantation damage with the dopant. The capability to achieve very high temperature ramp-rates was thus embraced as an essential requirement of the next generation of RTA equipment.In this paper, recent experimental data examining the effect of the ramp-up rate during spike-and soak-anneals on enhanced diffusion and shallow junction formation is reviewed. The advantage of increasing the ramp-up rate is found to be largest for the shallowest, 0.5-keV, B implants. At such ultra-low energies (ULE) the advantage arises from a reduction of the total thermal budget. Simulations reveal that a point of diminishing return is quickly reached when increasing the ramp-up rate since the ramp-down rate is in practice limited. At energies where TED dominates, a high ramp-up rate is only effective in minimizing diffusion if the implanted dose is sufficiently small so that the TED can be run out during the ramp-up portion of the anneal; for larger doses, a high ramp-up rate only serves to postpone the TED to the ramp-down duration of the anneal. However, even when TED is minimized at higher implant energies via high ramp-up rates, the advantage is unobservable due to the rather large as-implanted depth. It appears then that while spike anneals allow the activation of ULE-implanted dopants to be maximized while minimizing their diffusion the limitation imposed by the ramp-down rate compromises the advantage of very aggressive ramp-up rates.

Thermal Studies on Stress-Induced Void-Like Defects in Epitaxial-CoSi2 Formation

AbstractWe report experimental findings on the thermal-induced stress-voiding observed during epitaxial CoSi2 formation on patterned Si(100) wafers associated with the Co/Ti-interposing layer scheme [1–6]. The first rapid thermal process (RTP) in a typical SALICIDE process was studied by varying the temperature and the RTP ramp-up rate. Based on ex-situ cross-sectional transmission electron microscopy (XTEM), crystal defects were observed at shallow trench isolation (STI)/Si and gate spacer/Si edges after annealing at temperatures greater than 520°C. In addition, isothermal anneals for various time periods resulted in increased encroachment of an ultra-thin CoSi2-phase at the STI/Si edge. Higher temperature anneals also resulted in a corresponding increase in void size. In addition, higher ramp-up rates led to a thicker CoSi2 “pocket” film at the tensile-stressed STI/Si edge, aligned epitaxially along the {111}-habit planes. Our attempts to bypass the CoSi formation in order to alleviate the anomalous Si diffusion was found to be irrelevant to the voiding issue, due to the inherent nature of this film stack system to nucleate CoSi2 as the first phase. By comparing our experimental observations of voiding with Hu's analysis of the trench isolation stress fields, we found good agreement with the predicted stress field distribution in the active Si and STI/Si edge with the locations of void nucleation. The anomalously large stress induced is still not known, but can be attributed to the encroaching CoSi2 film which tends to realign epitaxially along the STI/Si interface.

Ion implantation induced selective area exfoliation of InP and GaAs

Patterned exfoliation, driven by 0.45 MeV H and 1.0–1.4 MeV He implantations, has been demonstrated in single crystal GaAs and InP. In both materials implantation of 4 × 10 16 cm −2 He or 1 × 10 17 cm −2 H ions through a suitable implant mask, followed by a 350°C thermal anneal, resulted in expulsion of material exclusively from the implanted regions i.e. the exfoliation field mapped the details of the mask and in all cases to a depth determined by the depth of the implanted ion. The effect of varying the anneal temperature ramp-up rate is marked. At the highest rate so far examined (100°C/s) the expelled material from each exposed area can be in the form of a single block. Exfoliation is also demonstrated in InP containing a buried InGaAsP alloy layer.

Ultra-shallow junction formation by spike annealing in a lamp-based or hot-walled rapid thermal annealing system: effect of ramp-up rate

Ultra-shallow p-type junction formation has been investigated using 1050°C spike anneals in lamp-based and hot-walled rapid thermal processing (RTP) systems. A spike anneal may be characterized by a fast ramp-up to temperature with only a fraction of a second soak-time at temperature. The effects of the ramp-up rate during a spike anneal on junction depth and sheet resistance were measured for rates of 40, 70 and 155°C/s in a lamp-based RTP, and for 50 and 85°C/s in a hot-walled RTP. B + implants of 0.5, 2 and 5 keV at doses of 2×10 14 and 2×10 15 cm −2 were annealed. A significant reduction in junction depth was observed at the highest ramp-up rate for the shallower 0.5-keV B implants, while only a marginal improvement was observed for 2- and 5-keV implants. It is concluded that high ramp-up rates can achieve the desired ultra-shallow junctions with low sheet resistance but only when used in combination with spike anneals and the lowest energy implants.

Activation annealing of Si-implanted GaN up to 1500°C using a novel RTP technique

A novel rapid thermal processing (RTP) unit called Zapper™ has recently been developed by MHI Inc. and the University of Florida for high temperature thermal processing of semiconductors. This Zapper™ unit is capable of reaching much higher temperatures (>1500°C) than conventional tungsten-halogen lamp RTP equipment and achieving high ramp-up and ramp-down rates. Implant activation annealing studies of Si+-implanted GaN thin films (with and without an AlN encapsulation layer) have been conducted using the Zapper™ unit at temperatures up to 1500°C. The measurements of electrical properties of such annealed samples have led to the conclusion that high annealing temperatures and AlN encapsulation are needed for the optimum activation efficiency of Si+ implants in GaN. It has clearly been demonstrated that the Zapper™ unit has tremendous potential for RTP annealing of semiconductor materials, especially for wide bandgap compound semiconductors that require very high processing temperatures.

Optimization of RTA parameters to produce ultra-shallow, highly activated B+, BF 2 + , and As+ ion implanted junctions

The effects of time, temperature, ramp-up, and ramp-down rates with rapid thermal annealing employing a STEAG AST SHS3000 were investigated on 1.0 and 2.0 keV 11B+, 2.2, 5.0, and 8.9 keV 49BF 2 + , and 2 KeV 75As+, 1E15/cm2 samples implanted in a Varian VIISion-80 PLUS ion implanter at 0o tilt angles. These annealed samples were analyzed by four-point probe, secondary ion mass spectrometry (SIMS), and in select cases by spreading resistance profiling (SRP) and transmission electron microscopy (TEM). To ensure reproducibility and to minimize oxidation enhanced diffusion as an uncontrolled variable, the O2 background concentration in N2 was maintained at a controlled low level. Under these conditions, ramp-rates alone were found not to be significant. Spike anneals (1050°C, ∼ 0 s) with fast ramp-rates (240°C/s) and fast cool down rates (86°C/s) provided the shallowest junctions, while still yielding good sheet resistance values. Post annealed samples were examined for extended defect levels (by TEM) and trapped interstitial concentrations. Fluorine concentration measurements were employed to qualitatively explain differences in the B diffusion from 11B+ and 49BF 2 + ion implants at various energies. The 2.2 keV 49BF 2 + “fast” spike annealed sample at 1050°C exhibited limited, if any, enhanced diffusion, yielding a SIMS junction depth of 490A, an electrical junction of 386A (by SRP) and a sheet resistance of 406 ohm/sq.

A novel technique for RTP annealing of compound semiconductors

We introduce for the first time a novel rapid thermal processing (RTP) unit called Zapper™, which has recently been developed by MHI Inc. and the University of Florida, for high temperature thermal processing of semiconductors. This Zapper™ unit is capable of reaching much highertemperatures (>1500°C) than conventional tungsten–halogen lamp RTP equipment and achievinghigh ramp-up and ramp-down rates. We have conducted implant activation annealing studies ofSi +-implanted GaN thin films (with and without an AlN encapsulation layer) using the Zapper™ unit at temperatures up to 1500°C. The electrical property measurements of such annealed samples have led to the conclusion that high annealing temperatures and AlN encapsulation are needed for the optimum activation efficiency of Si + implants in GaN. It has clearly been demonstrated that the Zapper™ unit has tremendous potential for RTP annealing of semiconductor materials, especially for wide band-gap (WBG) compound semiconductors that require very high processing temperatures.

Dopant profile and defect control in ion implantation by RTA with high ramp-up rate

Ion implantation has been widely used for current production and would be used in sub-quarter micron devices. However, problems such as enhanced diffusion and junction leakage current result from point defects generated by implantation. Process optimization and refinement are essential to obtain an excellent performance in those devices. In this paper, the RTA process has been optimized to minimize enhanced diffusion in shallow junction formation and to reduce junction leakage current and variation in high energy implantation. In shallow junction formation, high temperature (1100 °C), high ramp-up rate (400 °C s −1) and short-time (50 ms) RTA is effective to obtain a junction as shallow as 50 nm with low sheet resistance of 305 Ω/. In high-energy implantation, high temperature (≥ 1100 °C) and high ramp-up rate (≥200 °C s −1) RTA reduces junction leakage current and variation, when P + ions were implanted at 1 MeV with a dose of 1 × 10 14 cm −2. These results suggest the effectiveness of high temperature and high ramp-up rate RTA on the controlling of dopant profiles and defects.

Effect of Various Cutting and Stirring Conditions on Curd Particle Size and Losses of Fat to the Whey during Cheddar Cheese Manufacture in Ost Vats

Abstract Nine combinations of speed and duration of cutting the coagulum were varied during the commercial manufacture of Cheddar cheese in 27 Ost IV cheese vats. The effects of cut speed ramp-up rate, vat overfilling and stirring rate after cutting were also evaluated. The effects of the variations were assessed by determining the curd particle size distribution and fat losses to the whey at draining. The results of varying the speed and duration of cutting were compared with the results of a similar investigation carried out using vertical, double O, Damrow vats. Although the results showed similar trends, compared with the Damrow vat at the same speed the Ost vat’s cutting system reduces curd particles to a constant size more rapidly, thereby avoiding excessive curd shattering and high whey fat losses during subsequent stirring. Based on these results and comparisons with the results from the Damrow trial, a model is proposed. It explains how variation in speed and duration of continuous cutting, followed by a constant stirring speed, determines curd particle size distribution in an Ost IV cheese vat. The model can be used to maximise moisture retention and minimise whey fat losses. Reducing the cut speed ramp-up rate and the stirring speed significantly increased the curd particle size. Overfilling Ost IV vats significantly increased curd the particle size but had no significant effect on whey fat losses.

Plasma behaviour with molecular beam injection in the HL-1M tokamak

A new method of gas fuelling has been introduced in the HL-1M tokamak. The method consists of a pulsed high speed molecular beam formed by a Laval type nozzle. The velocity of the well collimated hydrogen beam is about 500 m/s. About 6 × 1019 molecules pass through the nozzle and into the vacuum chamber in each pulse. A series of helium pulses was injected into the HL-1M low density (n̄e = 4 × 1018 m-3) hydrogen plasma. With penetration depth up to 12 cm, the ramp-up rate of the electron density, dn̄e/dt, was as high as 3.1 × 1020 m-3·s-1 at steady state, and the resulting plasma density reached n̄e = 5.6 × 1019 m-3. The profile peaking factor of the electron density, Qn = ne(0)/⟨ne⟩ of about 100 ms after helium molecular beam injection (MBI) reached a maximum value of more than 1.51. The energy confinement time τE measured by diamagnetism is 26 ms, which is over 30% longer than that of the gas puffing (GP) results under the same operational conditions. The improvement of τE and increase of Qn for MBI were comparable to those of small pellet injection (PI) in HL-1M, as well as those of slow PI in ASDEX (Kaufmann, M., et al., Nucl. Fusion 28 (1988) 827). It is argued that the peaked density profile induced by the deepened particle injection is a factor essential for the confinement improvement apart from the isotope effect of helium particles, because the density peaking factor Qn is normally less than 1.4 for GP plasma in HL-1M. The particle confinement time with MBI increased sixfold in comparison with that before injection.