Rail Voltage Research Articles

A high current efficiency rail-to-rail operational amplifier

ABSTRACT This paper proposes a new single stage high current efficiency rail to rail amplifier (HCE-RTR). Due to the combination of a new constant transconductance control circuit and local common mode feedback (LCMFB) technique, the proposed rail to rail amplifier not only achieves improvements in unity-gain bandwidth (GBW) and slew rate (SR), but also ensures input stage transconductance constancy within the rail to rail voltage range. Based on the SMIC 180 nm process, the post-layout simulation results show that the proposed amplifier achieves rail-to-rail input/output. The simulated open loop AC response shows the DC gain, GBW, and PM are 66.2 dB, 8.2 MHz, and 60.97 o , respectively. When the driving load capacitance is 70 pF, the transient response simulation results show that the proposed amplifier achieves 0.039 µs average 1% settling time, and about 5.73 V/µs average slew rate. Note that under the condition of 1.8 V power supply, the power consumption is only 122.4 µW, proving the proposed amplifier can achieve high current efficiency while maintaining stability.

Positive Rail Voltage Rise Behavior and Inhibition Analysis of Regenerative Braking of Medium–Low-Speed Maglev Train

When a medium–low-speed (MLS) maglev train is braking, part of its regenerative braking (RB) power consumption may cause a significant rise in the positive rail (PR) voltage. For RB energy re-utilization, an RB energy feedback system (RBEFS) is a promising application, but there is still no specific research in the field of MLS maglev trains. From this perspective, this article focuses on identifying the PR voltage rise behavior and investigating the application of an RBEFS on the over-voltage inhibition. Some development trends of the MLS maglev train, including the DC 3 kV traction grid system and the speed being raised to 160~200 km/h, are also considered in the analyzed scenarios. At first, a modeling scheme of a detailed vehicle–grid electrical power model with the RBEFS is established. On this basis, the PR voltage rise characteristics are analyzed with consideration of three pivotal influencing factors: RB power, PR impedance and supply voltage level. Subsequently, to stabilize the PR voltage fluctuations, the influence rules of the RBEFS on the voltage rise and the mutual transient voltage influences under the operating status switching for multiple vehicles running on the same power supply section are analyzed.

An improvement of stability and dynamic response in hybrid AC-DC microgrids using optimal power control management

Microgrid topologies enable more effective use of renewable resources as well as the autonomous process. Microgrids are effective frameworks for managing dispersed assets such as renewable structures with small-scale distributed generator supplies. Smart grids are adaptable electricity networks that have arisen as a result of the introduction of new technologies and features. It is suggested that a three-terminal AC/DC hybrid microgrid with DC two and AC one terminal be used. A two dual active bridge (DAB) with cascaded H-bridge (CHB) converter with AC grid link-based interactions that connect isolated two DC buses are included in the suggested structure. To minimise the energy generation stages and power devices, the DAB converters are intrinsically linked to the CHB of DC rails based on the structure-specific requirements. To present the unnecessary grid currents and DC rail voltage issues exist by this revised structure topology by simply two power alteration stages, a better solution is suggested that employs zero-sequence voltage (ZSV) injection in the CHB converters. The impacts of managed settings on structure stability and dynamic responsiveness are investigated in order to reduce conflicts among ZSV injection by structure voltage/current regulation. This paper compares the performance of a PI and a PR for DC voltage regulation. A comparison of simulation results for both control approaches is provided. The major difficulty is to normalise the system model in order to identify the appropriate controller settings for robust control. The findings are confirmed and compared to the conventional regulator PI. The suggested 3-Φ AC current and DC rail voltage regulating approach's universal efficacy is proved by MATLAB/Simulink analytical model from the three and five-terminal hybrid AC/DC power structures.

Design and Implementation of a High-Speed D Flip Flop using CMOS Inverter Logic

This paper proposes an improvised D- flip flop configuration based on tristate inverter logic, which reduces the power dissipation, decrease the transition time from the input to output as well as reduced time to reach rail to rail voltage. The flip flop uses transmission gate instead of pass transistor to achieve this requirement. The design is simulated using 90nm CMOS technology and data is propagated at 50% duty cycle. The circuit is simulated using Cadence tools to assess the performance with respect to delay and power. These D-flip flops have numerous applications such as buffers, registers, digital VLSI clocking systems, microprocessors etc.

A Multistep Charge Extractions and Voltage Bias-Flip (MCEBF) Interface Circuit for Piezoelectric Energy Harvesting Enhancement

In piezoelectric energy harvesting (PEH), interface circuits using synchronous switch actions, including synchronized charge extraction (CE) and/or bias-flip (BF), can achieve much higher energy harvesting (EH) capability, compared with the standard energy harvesting (SEH) bridge rectifier. In this article, a multistep charge extraction and voltage bias-flip (MCEBF) interface circuit is proposed to further enhance the harvesting capability under weakly coupling conditions. The EH enhancement is realized by reducing the dissipation in CE with multiple CE actions and simultaneously enlarging the extracted energy with a BF action. MCEBF can also generate positive and negative voltage rails via buck-boost topology to supply power for double-rail devices. The optimal control method of MCEBF is theoretically derived. In our experiment, under constant deflection excitation, the best MCEBF case offers 487%, 95%, and 49% more harvested power, compared with SEH, synchronous electric charge extraction (SECE), and parallel synchronized switch harvesting on inductor (P-SSHI) interface circuits, respectively. MCEBF also keeps the benefit of load independence as SECE does under weakly coupling conditions.

Online Diagnosis and Ride-Through Operation for Cascaded H-Bridge Converter Based STATCOM With a Single Open-Circuit IGBT

To address the most commonly seen single insulated gate bipolar transistor (IGBT) open-circuit fault problems in cascaded H-bridge (CHB) converter based static synchronous compensator, a simple online fault diagnosis method and the corresponding ride-through operation approach are proposed. The method can quickly determine the exact location of the open-circuit IGBT through three steps, via analyzing the relationships between the dc bias in the three-phase output current of CHB converter, the transient dc rail voltage variations with respect to the averaged dc rail voltage, and the response of dc rail voltage and output current when the modulation approach of the faulty power module is adjusted. Afterwards, a fault ride-through approach is adopted to seamlessly transfer the modulation approach of faulty H-bridge module and it behaves as a half-bridge to provide a half of the rated output ac voltage. Meanwhile, the corresponding dc offset voltage from this faulty module is compensated by producing the same dc voltage in the healthy phase legs to avoid the dc bias in the three-phase output current. It has been demonstrated that the proposed fault diagnosis approach and the fault ride-through approach are effective in various adverse situations including grid voltage sudden disturbances and the load power sudden changes. Comprehensive simulated and experimental results have been provided to validate the effectiveness of the proposed approach.

A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.

Implementation of Snubber Circuits in a PV-Based Off-Grid Electric Vehicle Charging Station—Comparative Case Studies

With the penetration of electric vehicles (EVs), there have been paradigm shifts in the transportation sector. EVs are ideally considered to be clean and eco-friendly, but they can overload the existing grid infrastructure and significantly contribute towards carbon emissions depending on the source of charging. The ideal solution is to develop a charging infrastructure for EVs that is integrated with solar energy technology. This paper presents the design of a zero-voltage switching snubber-based bidirectional converter for an off-grid charging station for EVs. The proposed system includes a solar array with a boost converter, a bidirectional converter with snubber circuits and an energy storage unit. A comprehensive comparison between various types of snubbers, such as the resistive capacitive diode snubber, active clamp snubber and flyback snubber, is presented. This type of system configuration clamps the rail voltage, due to the difference in current between leakage inductance and low voltage side-fed inductor currents, resulting in reduced current spikes at the converter’s switches. Such a converter, therefore, leads to higher efficiency of the charging station for EVs. The design of a snubber-based off-grid charging station for EVs is formulated and validated in the MATLAB/Simulink environment.

Supercapacitor-Assisted Techniques and Supercapacitor-Assisted Loss Management Concept: New Design Approaches to Change the Roadmap of Power Conversion Systems

All electrical and electronic devices require access to a suitable energy source. In a portable electronic product, such as a cell phone, an energy storage unit drives a complex array of power conversion stages to generate multiple DC voltage rails required. To optimize the overall end-to-end efficiency, these internal power conversions should waste minimal energy and deliver more to the electronic modules. Capacitors are one of the main component families used in electronics, to store and deliver electric charges. Supercapacitors, so called because they provide over a million-fold increase in capacitance relative to a traditional capacitor of the same volume, are enabling a paradigm shift in the design of power electronic converter circuits. Here we show that supercapacitors could function as a lossless voltage-dropping element in the power conversion stages, thereby significantly increasing the power conversion stage efficiency. This approach has numerous secondary benefits: it improves continuity of the supply, suppresses voltage surges, allows the voltage regulation to be electromagnetically silent, and simplifies the design of voltage regulators. The use of supercapacitors allows the development of a novel loss-circumvention theory with applicability to a wide range of supercapacitor-assisted (SCA) techniques. These include low-dropout regulators, transient surge absorbers, LED lighting for DC microgrids, and rapid energy transfer for water heating.

Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation

Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is presented. The proposed implementation consists of a new “converter-free” design based on a three-level voltage stack operating at 1.8 V ± 5%. Here, the leakage current from the SRAMs in the top stack is recycled to sustain the near/subthreshold operation of the logic circuits in the two lower stacks. A test chip with the proposed voltage-stacking technique was implemented in a 28-nm low- Vth (LVT) fully depleted silicon on insulator (FDSOI) technology. The test chip is an ultralow-power advanced system-on-chip (SoC) consisting of an RISC-V core, a coarse-grained reconfigurable accelerator, and peripherals. The SoC uses a current sink and an adaptive body-bias controller for voltage regulation of the intermediate voltage rails between the stacks. The proposed system achieves up to 95% power delivery efficiency with negligible area overhead (~ 1%). The silicon measurement shows that the system energy efficiency is improved by 1.6× on average, and the energy consumption is reduced by 37% on average compared to the flat implementation.

Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference

With advances in low power and battery-operated devices, concerns over power-efficient designs for system-on-chip devices is growing. Since some subsystems require to have both positive and negative voltage rails, it is essential to ensure this requirement is satisfied without increasing the cost and power consumption. This paper presents a novel Negative Level Shifter used to generate negative voltage levels from the positive DC power supply line. Additionally, an improved CMOS Voltage Reference generator based on a Resistorless Beta Multiplier is also proposed. The two circuits were tested under various conditions, and results validate the low-power operation of the proposed design. The proposed Negative Level Shifter required only 772 pW and has a delay equal to 4ns with a supply voltage of 0.3V. When assembled, both the reference voltage and the level shifter consume 8.5 nW with the supply voltage of 1V at room temperature.

Smart Touch Voltage Limitation

In modern railway electric infrastructure design there are two major concerns that should be considered as touch voltage and stray current. The first problem is touch and step voltage which endangers human safety even to deathly situations. Second problem is stray current which leads to corrosion of metallic infrastructure. Since human safety has higher priority early on railway systems has grounded the rail voltage to the earth but this caused stray current problem. Thus these two problems should be handled together. In this paper we present a touch voltage control and stray current monitoring solution to handle both problems. Our solution presented here uses thyristor based grounding to limit touch voltage and monitor and report stray current

Research on protection of tuning area equipment disconnection in the ZPW-2000A track circuit

To overcome the problem of tuning area faults influencing the normal operation of the ZPW-2000A track circuit, protector models are established to protect the track circuit from interference. First, the parameters of the protector models are calculated according to the circuit resonance principle. Second, a four-terminal network model of the track circuit in a normal state is established according to transmission-line theory and the transmission equations are derived. Third, the rail voltage is simulated, and an experimental platform is built to verify the models. Finally, the transmission equations of the protectors are derived, and the variation of the rail voltage is analyzed. The results indicate that tuning area faults have significant influence on the rail voltage. However, the installation of protectors can effectively reduce the influence, and not bear on the normal operation and maintenance of the track circuit, which significantly improves the protection ability of the track circuit against tuning area faults.

Influence of operating parameters on discharge mode of parallel-rail accelerator

Electromagnetic plasma accelerators which can generate hypervelocity and high density plasma jets have been widely used in the fields of nuclear physics and astrophysics. In this paper, an experimental platform of parallel-rail accelerator electromagnetically driven plasma is established, and the discharge modes under different discharge currents and gas injection conditions are studied through using magnetic probes, a spectrometer and an ICCD. A fast gas valve is used to inject argon into the rail electrode area. The time delay between the fast valve discharge and the parallel-rail accelerator discharge is fixed to be 450 μs. The waveform of power supply of the parallel-rail accelerator is a sinusoidal wave. The total capacitance is 120 μF, the total inductance is about 400 nH, and the maximum current is 170 kA. The fast valve current waveform is a double exponential waveform with a maximum current of 2.5 kA. When the discharge current is 40 kA, a current sheet with a certain thickness is generated, and the current sheet moves through different detection positions along the rail electrode at a certain velocity. Therefore, the working mode of the parallel-rail accelerator is the snowplow mode. As the discharge current increases, the trailing edge of the current channel is fixed during the current rising phase, and starts to move to the end of the rail during the current falling phase. A diffuse distributed current channel is formed, and the parallel-rail accelerator operates in a deflagration mode. As the gas injection mass increases, the current channel front velocity decreases to form a more concentrated distributed current channel, and the discharge mode turns into the snowplow mode. The stationary current channel in the deflagration mode is maintained mainly by ablating the electrode. The operating parameters mainly affect the rail voltage, which in turn affects the discharge mode of the parallel-rail accelerator. The rail voltage increases when the discharge current or the current rate of change increases. If the rail gap behind the current channel cannot withstand the high rail voltage under large discharge current or large current rate of change, the breakdown occurs, which results in the deflagration mode discharge.

Integration of PV and Battery Storage for Catenary Voltage Regulation and Stray Current Mitigation in MVDC Railways

Innovative advancement in power electronics is reshaping the conventional high-voltage transmission systems and has also opened a new paradigm for researchers to consider its benefits in the railway electrification system (RES). In this regard, the medium-voltage direct current RES (MVDC-RES) is a key area of interest nowadays. In this paper, a secondary energy source (SES) consisting of renewable energies (REs) and energy storage systems (ESSs) is proposed to solve the issues of catenary voltage regulation, rail potential, and stray current in the MVDC-RES. Some of the major integration topologies of the SES are analyzed for MVDC-RES and the most effective one is proposed and implemented. The voltage at the point of connection (PoC) of the SES is used as a reference for controlling different operation modes of REs and ESSs. Moreover, feedforward control is used at the ESS converter to attain the quick response from the batteries for the desired operation. The proposed scheme improves the catenary voltage, and reduces the rail potential and stray current. Besides, the scheme provides higher energy density and reduces line losses. Simulation results are provided to validate the operation modes and advantages of the proposed scheme.

A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and V SW Dual-Edge Dead-Time Modulation Techniques

This article presents a GaN driver operating at a switching frequency variable from 10 to 30 MHz to achieve reliable and efficient power conversion for automotive electronics applications. An active bootstrap (BST) balancing (ABB) technique is presented to stabilize the BST rail voltage by sensing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> and controlling BST rail charging. Meanwhile, a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> dual-edge dead-time (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dead</sub> ) modulation senses instant V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> and generates optimal t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dead</sub> for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> trailing and leading edges, achieving zero-voltage switching (ZVS) turn-on for GaN power switches. To operate at high frequency and retain high efficiency, pulse-based dynamic upand down-level shifters are developed to achieve sub-nanosecond propagation delay with a quiescent current of 0.5 μA. To validate this work, a switching power converter prototype is implemented using a 0.35-μm highvoltage (HV) BCD process. It maintains a constant 5.1-V BST rail voltage to prevent GaN FET from destructive breakdown and accomplishes 0.9-to-3.7-ns t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dead</sub> and 3.7-to-10.4-ns tdead for VSW trailing and leading edge, respectively, in response to load current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> change from 0.01 to 1.2 A. The proposed techniques jointly improve the efficiency by 8.3%, which peaks at 90.7% for 12-to-5-V conversion and 88% for 40-to-5-V conversion.

Mutual interference induced by single event effects in CMOS circuits

Single event effect (SEE) induced mutual interference in CMOS circuits, including single event (SE) induced coupling effects (crosstalk) and modulation in local supply voltage on power-supply rails, was studied based on the increase in metal interconnect density. The dependence of SE vulnerability on metal interconnects was experimentally investigated using heavy ions and pulsed laser. Numerical simulation was performed to evaluate the modulation in local supply voltage induced by SEEs. Two groups of test structures with various metal interconnects between well contacts and the first metal layer were designed and fabricated. All other parts, including well contacts in the active regions, are of the same structures. Experimental results show that the upset cross section decreases with an increase in metal interconnect contact (CT) density between the active region and the first metal layer, suggesting a dominant contribution of rail voltage drop induced by charge sharing rather than SE-induced crosstalk. The differences in upset cross sections with cells of different CT hole densities appear the most evident ones under low frequency and high linear energy transfer value conditions. When transient-induced upsets play a more important role, the differences get weakened due to masking effects.

Multi-Target Adaptive Reconfigurable Acceleration for Low-Power IoT Processing

Low-power processors for the Internet-of-Things (IoT) demand a high degree of adaptability to efficiently execute applications with different resource requirements under varying scenarios. Current single-ISA heterogeneous Chip Multiprocessors (CMPs), such as ARM's big.LITTLE, provide multiple cores and voltage/frequency levels to address this challenge. However, finding the best possible type of core and the corresponding voltage/frequency level for all the execution scenarios, which involve different applications and phases, remains far from being reached. In this article, we propose extending such a single-ISA heterogeneous CMP with a Coarse-Grained Reconfigurable Array (CGRA) and a hardware-based dynamic binary translation (DBT) module that transparently maps application code onto the CGRA for acceleration. To achieve low-energy levels and efficiently manage the power consumption of the CGRA, we introduce an additional voltage rail that enables operation in the Near-Threshold Voltage (NTV) regime when needed, leveraging key features of the CGRA's structure to address the implementation challenges of NTV computing. For less than 35 percent area overhead to the baseline CMP, performance and energy consumption are improved as follows. Compared to: (a) power-efficient execution in the LITTLE core, MuTARe achieves 29 percent reduction in energy consumption, and $2\times$ 2 × speedup; (b) performance-efficient execution in the big core, a speedup of $1.6\times$ 1 . 6 × with an energy reduction of 41 percent is achieved.

New PQ theory for power quality improvement using modular multilevel converter based UPFC system

The source current harmonics reduction techniques were found to be unpredictable and disparity under different loading conditions. The presence of uncertainity issue in harmonics elimination is due to nonlinear loads. Filters can be used to eliminate the harmonics and power quality issues. But these filters are not cost effective to provide dynamic performance under various loading conditions. The target of this paper is to minimize source current harmonics with optimum voltage stability under different loading conditions. A new Unified Power Flow controller is developed whose series compensator is replaced by modular multilevel converter to achieve high modular level with reduced harmonics and fast current limiting during the fault short circuit and shunt compensator is replaced with four switches and one capacitor combination to achieve the twin benefit of more reliable power system and good voltage stability for different loadings. DDSRF (Decoupled Double Synchronous Reference Frame) theory is utilized in the proposed converter for generating the reference current from the AC supply. DDSRF theory generates sinusoidal harmonics with the opposite phase to the load current. The UPFC can suck or injects the responsive power in the PCC. After DDSRF theory, hysteresis controller is used to produce PWM pulse for the shunt and series compensator. The proposed DDSRF theory is compared with existing dq theory to show its effectiveness in terms of THD analysis. The PI and fuzzy logic methodology is utilized to control the capacitor DC rail voltage. The proposed approach is simulated using Matlab under various loading condition and hardware is developed using Spartan 6E FPGA Controller.

Low Leakage SRAM Cell with Improved Stability for IoT Applications

Abstract For IoT applications, a new SRAM cell with differential write and single-ended read ability is proposed in this paper. The transmission gate is used as an access transistor to get rail to the rail voltage swing and improved stability. Analysis of leakage power and stability for proposed SRAM cell at supply voltage ranging from 0.9V to 0.5V is compared with the existing 5T and 6T SRAM bit cells at 32nm technology. The transistor stacking effect is used to minimize the leakage current of the SRAM cell. The stability increase is accomplished by isolating read line from the node that causes read disturbance problem. The proposed memory cell shows 436x and 1.15x improvement in read power in comparison to 6T and 5T cell, respectively at 0.8V supply voltage. Stability is also improved by 1.15x and 1.12x at 0.8V of supply voltage.