Radiation Hardened By Design Research Articles

A Novel 65 nm Radiation Tolerant Flash Configuration Cell Used in RTG4 Field Programmable Gate Array

The newly introduced radiation-tolerant flash-based FPGA, RTG4, uses a novel configuration cell design composed of a NMOS switch controlled by a totem pole p-channel flash and n-channel flash construction. Its radiation tolerance is far superior to that in the present available Flash-based FPGA. This paper describes the radiation hardening by design (RHBD) process for the new flash-based configuration cell. A subtle and unique retention issue was found and resolved through studying physical mechanisms and conducting experiments.

Multi-MGy Radiation Hard CMOS Image Sensor: Design, Characterization and X/Gamma Rays Total Ionizing Dose Tests

A Radiation Hard CMOS Active Pixel Image Sensor has been designed, manufactured and exposed to X and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{60}{\rm Co}\,\, \gamma $</tex></formula> -ray sources up to several MGy of Total Ionizing Dose (TID). It is demonstrated that a Radiation-Hardened-By-Design (RHBD) CMOS Image Sensor (CIS) can still provide useful images after <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$10~\hbox{MGy}({\rm SiO}_2)$</tex></formula> (i.e. 1 Grad). This paper also presents the first detailed characterizations of CIS opto-electrical performances (i.e. dark current, quantum efficiency, gain, noise, transfer functions, etc.) in the MGy range. These results show that it is possible to design a CIS with good performances even after having absorbed several MGy. Four different RHBD photodiode designs are compared: a standard photodiode design, two well known RHBD layouts and a proposed improvement of the gated photodiode design. The proposed layout exhibits the best performances over the entire studied TID range and further optimizations are discussed. Several original MGy radiation effects are presented and discussed at the device and circuit levels and mitigation techniques are proposed to improve further the radiation hardness of future Rad-Hard CIS developments for extreme TID applications (e.g. for nuclear power plant monitoring/dismantling, experimental reactors (e.g. ITER) or next generation particle physics experiments (e.g. CERN)).

Double Node Upsets Hardened Latch Circuits

A radiation hardened by design (RHBD) latch and its temporally hardened version to tolerate double node upsets are proposed in this paper. C-Elements are used to construct structures for fault corr...

Single-Event Transient and Total Dose Response of Precision Voltage Reference Circuits Designed in a 90-nm SiGe BiCMOS Technology

This paper presents an investigation of the impact of single-event transients (SETs) and total ionization dose (TID) on precision voltage reference circuits designed in a fourth-generation, 90-nm SiGe BiCMOS technology. A first-order uncompensated bandgap reference (BGR) circuit is used to benchmark the SET and TID responses of these voltage reference circuits (VRCs). Based on the first-order BGR radiation response, new circuit-level radiation-hardening-by-design (RHBD) techniques are proposed. An RHBD technique using inverse-mode (IM) transistors is demonstrated in a BGR circuit. In addition, a PIN diode VRC is presented as a potential SET and TID tolerant, circuit-level RHBD alternative.

Scalability of Capacitive Hardening for Flip-Flops in Advanced Technology Nodes

Capacitive radiation hardening by design (RHBD) techniques to reduce the single-event cross section of flip-flops are shown to be effective at highly scaled technology nodes, especially for the terrestrial environment. Test results for different values of RHBD capacitance for both 40 nm and 28 nm technology node designs show that small values of RHBD capacitance (<; 3 fF) are effective in reducing the single-event cross section for low LET particles, neutrons, and alpha particles. Reductions of 4x, 2.5x, and 14x respectively were observed for the 28 nm designs for low LET particles, neutrons, and alpha particles, and reductions of 2.4x and 2.1x were observed for the 40 nm designs for low LET particles and alpha particles. Experimental pulse width measurement results for Xenon are used to highlight operating regions where capacitive RHBD techniques are most effective.

Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism

The impact of the source on single event transient (SET) is studied for the balanced two-transistor inverter by a novel simulation structure in a 90nm twin-well bulk CMOS technology. Due to the significantly distinct mechanism of single event change collection in PMOS and NMOS, the source, which is beneficial to broadening P-hit SET pulse width (WSET) but reducing N-hit WSET, plays a different role in SET production. Based on these different source roles, different radiation hardened by design (RHBD) methods are proposed to reduce WSET for PMOS and NMOS, respectively. The simulation results show that the proposed RHBD methods can remarkably reduce WSET.

A Dual Mode Redundant Approach for Microprocessor Soft Error Hardness

A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

Combining GEANT4 and TIARA for Neutron Soft Error-Rate Prediction of 65 nm Flip-Flops

Experimental neutron characterizations of standard and radiation-hardened-by-design (RHBD) flip-flops (FFs) are compared to combined GEANT4 and TIARA simulations. Good agreement is found between experiment and simulation for both architectures exhibiting soft error-rate (SER) values ranging over more than two decades. In-depth analysis of TIARA simulation results demonstrates that different underlying mechanisms are at the origin of observed soft errors: neutron-silicon (n-Si) elastic scattering for standard 65 nm FF while multiproduct nuclear reactions are for the RHBD structure. Finally, TIARA simulation results for monoenergetic neutron sources and atmospheric-like (i.e., synthetic) neutron spectra are discussed together with their impact on SER.

RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation

A novel radiation-hardened-by-design (RHBD) technique that utilizes charge sharing to mitigate single-event voltage transients is employed to harden bias circuits. Sensitive node active charge cancellation (SNACC) compensates for injected charge at critical nodes in analog and mixed-signal circuits by combining layout techniques to enhance charge sharing with additional current mirror circuitry. The SNACC technique is verified with a bootstrap current source using simulations in a 90-nm CMOS process. Reductions of approximately 66% in transient amplitude and 62% in transient duration are observed for 60-degree single-event strikes with an LET of 40 MeV*cm2/mg. The SNACC technique can be extended to protect multiple sensitive nodes (M-SNACC). M-SNACC is used to harden the bias circuit of a complementary folded cascode operational amplifier, providing a significant reduction in single-event vulnerability for a 8-bit digital-to-analog converter.

Design of a total-dose radiation hardened monolithic CMOS DC-DC boost converter

This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation. In order to improve its radiation tolerant abilities, circuit-level and device-level RHBD (radiation-hardening by design) techniques were employed. Adaptive slope compensation was used to improve the inherent instability. The H-gate MOS transistors, annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose. A boost converter was fabricated by a standard commercial 0.35 μm CMOS process. The hardened design converter can work properly in a wide range of total dose radiation environments, with increasing total dose radiation. The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.

Application-Oriented SEU Cross-Section of a Processor Soft Core for Atmel RHBD FPGAs

Radiation Hardened By Design (RHBD) SRAM-based FPGAs are getting more and more appealing for space applications, since they embed mitigation techniques in the device itself, masking their complexity to the end-user. However, over a certain LET, this kind of devices could not guarantee hardening against radiation. It is thus necessary to perform a robustness analysis even for this kind of device. Computing the Single Event Upsets (SEU) sensitivity of the FPGA by means of the device cross-section is very pessimistic. So, we propose and validate a static analysis approach to asses the application-oriented cross-section, providing evidence on a soft processor core. The analysis is performed in a modular fashion, reporting the sensitivity of the different modules that compose the processor. Finally, results for a real environment and mission are reported, presenting the benefits of the proposed approach.

A Comprehensive Understanding of the Efficacy of N-Ring SEE Hardening Methodologies in SiGe HBTs

We investigate the efficacy of mitigating radiation-based single event effects (SEE) within circuits incorporating SiGe heterojunction bipolar transistors (HBTs) built with an N-Ring, a transistor-level layout-based radiation hardened by design (RHBD) technique. Previous work of single-device ion-beam induced charge collection (IBICC) studies has demonstrated significant reductions in peak collector charge collection and sensitive area for charge collection; however, few circuit studies using this technique have been performed. Transient studies performed with Sandia National Laboratory's (SNL) 36 MeV 16O microbeam on voltage references built with N-Ring SiGe HBTs have shown mixed results, with reductions in the number of large voltage disruptions in addition to new sensitive areas of low-level output voltage disturbances. Similar discrepancies between device-level IBICC results and circuit measurements are found for the case of digital shift registers implemented with N-Ring SiGe HBTs irradiated in a broadbeam environment at Texas A&M's Cyclotron Institute. The error cross-section curve of the N-Ring based register is found to be larger at larger ion LETs than the standard SiGe register, which is clearly counter-intuitive. We have worked to resolve the discrepancy between the measured circuit results and the device-level IBICC measurements, by re-measuring single-device N-Ring SiGe HBTs using a time-resolved ion beam induced charge (TRIBIC) set-up that allows direct capture of nodal transients. Coupling these measurements with full 3-D TCAD simulations provides complete insight into the origin of transient currents in an N-Ring SiGe HBT. The detailed structure of these transients and their bias dependencies are discussed, together with the ramifications for the design of space-borne analog and digital circuits using SiGe HBTs.

An RHBD Technique to Mitigate Missing Pulses in Delay Locked Loops

A radiation-hardened-by-design (RHBD) voltage- controlled delay line (VCDL) for single-event mitigation in delay-locked loops (DLLs) is proposed. A modified fully differential delay cell topology is used to harden the VCDL, resulting in a dramatic reduction of the missing pulses generated by the DLL after an ion strike. By increasing the width-to-length ratios of the feedback transistors of the VCDL delay cells, this topology provides substantially reduced single-event errors while maintaining high operating frequency, wide tuning range and small area penalty.

A Rad-Hard Miniaturized Switching Module for High-Voltage Applications

A miniaturized, scalable, and rad-hard high-voltage module is demonstrated as a “proof-of-concept.” The module is suitable for space applications. The design uses a commercial process that combines 0.25-μm complementary metal-oxide semiconductor (CMOS) transistors with a high-voltage lateral double-diffused metal-oxide-semiconductor (DMOS) device (>600 V). The design was simulated, fabricated, and tested and shows functionality up to 2.5 kV. Several radiation-hardening-by-design (RHBD) techniques were used to improve radiation hardness over 100 krad.

Single Event Upset and Multiple Cell Upset Modeling in Commercial Bulk 65-nm CMOS SRAMs and Flip-Flops

A proprietary Monte-Carlo simulation code dedicated to heavy ion cross-section prediction has been developed. The code is based on diffusion-collection equations, takes into account recombination processes, uses an improved drain strike model, and includes new upset analysis algorithms for different circuit architectures. Simulated cross-sections are compared to heavy ion experimental characterizations for commercial bulk 65-nm single- and dual-port SRAMs. Simulation capabilities of much more complex circuits are demonstrated considering a 65-nm radiation-hardened-by-design (RHBD) Flip-Flop (FF).

Nuclear microbeam studies of silicon–germanium heterojunction bipolar transistors (HBTs)

Abstract SiGe HBTs are very attractive devices to be used in space communication applications. This technology combines the high speed of the III–V semiconductors with the well-established and easy manufacturing processes of silicon, which allows the manufacturing of RF, analog, and digital devices on the same wafer. In addition, SiGe HBTs were found to be extremely radiation hard in the context of total ionizing dose and displacement damage. However, it was shown through experiments and simulations that these devices are vulnerable to single event effects (SEEs). SEEs are changes in the normal operation of the device (its logical state, currents, transients, etc.) due to the induced currents in the electrodes by the movement of carriers created by the incident ions. We used four electrode (base, emitter, collector, and substrate) IBIC measurements at the Sandia Heavy Ion Nuclear Microprobe Facility. SiGe HBTs are usually designed using deep trench isolation (DTI) to minimize parasitic capacitances from the subcollector to the substrate (faster speed), as well as allow devices to be fabricated much closer together. It is an added bonus that the DTI does not let carriers from outside hits to diffuse into the junction and induce current. Our experiments and TCAD simulations showed that while the above goal was accomplished by this design, it increased the amount of induced charge for ion hits in the active area. Single event transients (SETs) were investigated in both standard and radiation hardened by design (RHBD) bandgap voltage reference (BGR) circuits.

Single Event Transient Response of SiGe Voltage References and Its Impact on the Performance of Analog and Mixed-Signal Circuits

We investigate the single-event transient (SET) response of bandgap voltage references (BGRs) implemented in SiGe BiCMOS technology through heavy ion microbeam experiments. The SiGe BGR circuit is used to provide the input reference voltage to a voltage regulator. SiGe HBTs in the BGR circuit are struck with 36-MeV oxygen ions, and the subsequent transient responses are captured at the output of the regulator. Sensitive devices responsible for generating transients with large peak magnitudes (more than 5% of the dc output voltage) are identified. To determine the effectiveness of a transistor-layout-based radiation hardened by design (RHBD) technique with respect to immunity to SETs at the circuit level, the BGR circuit implemented with HBTs surrounded by an alternate reverse-biased <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pn</i> junction (n-ring RHBD) is also bombarded with oxygen ions, and subsequent SETs are captured. Experimental results indicate that the number of events causing transients with peak magnitude more than 5% above the dc level have been reduced in the RHBD version; however, with the inclusion of the n-ring RHBD, new locations for the occurrence of transients (albeit with smaller peak magnitude) are created. Transients at the transistor-level are also independently captured and are presented. It is demonstrated that while the transients are short at the transistor level (ns duration), relatively long transients are obtained at the circuit level (hundreds of nanoseconds). In addition, the impact of the SET response of the BGR on the performance of an ultra-high-speed 3-bit SiGe analog-to-digital converter (ADC) is investigated through simulation. It is shown that ion-induced transients in the reference voltage could eventually lead to data corruption at the output of the ADC.

A radiation-hardened-by-design technique for improving single-event transient tolerance of charge pumps in PLLs

A radiation-hardened-by-design (RHBD) technique for phase-locked loops (PLLs) has been developed for single-event transient (SET) mitigation. By presenting a novel SET-resistant complementary current limiter (CCL) and implementing it between the charge pump (CP) and the loop filter (LPF), the PLL's single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 93.1 % and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.

The Impact of Total Ionizing Dose on Unhardened SRAM Cell Margins

Static random access memory (SRAM) cells have diminishing read and write margins due to fabrication variations. These variations are a direct result of the small device sizes necessary to maintain scaling commensurate with Moore's law. Total ionizing dose (TID) primarily affects NMOS device characteristics, which are the most important to maintaining SRAM cell read stability. A test structure allowing direct measurement of SRAM cell electrical characteristics in an SRAM memory bank is presented. Experimentally measured results from this structure, fabricated on a 90 nm process, show impact of Co-60 irradiation on SRAM cell margins. This test structure is fabricated on the same die as a 1.2 Mbit SRAM, allowing comparison of the individual cell characteristics with the overall leakage impact on the large SRAM. The results indicate that by simply providing sufficient margins during SRAM cell design, functionality at high TID can be achieved without the use of radiation hardening by design (RHBD) techniques. The implications for future unhardened SRAMs operating in TID environments and on design to maintain margins are discussed.

A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed-Signal Phase-Locked Loops

A voltage-controlled-oscillator (VCO) circuit has been designed for radiation-hardened-by-design (RHBD) single-event transient (SET) mitigation. The RHBD technique, which can be readily implemented in mixed-signal phase-locked loops and delay-locked loops, is shown to substantially improve the single-event performance of the VCO while decreasing the RMS phase jitter due to power supply noise. Additionally, using the probabilistic analysis technique presented, the RHBD VCO shows a maximally improved SET response over that of the conventional VCO, decreasing the output phase displacement to below the nominal phase jitter.