Quantum Wire Transistors Research Articles

Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method

ABSTRACTA two-dimensional quantum mechanical model is presented for calculating carrier transport in ultra-thin gate-all-around quantum wire transistor (GAAQWT) and carbon nanotube field effect transistor (CNTFET) using coupled mode space approach. Schrödinger and Poisson’s equations are self-consistently solved involving Non-Equilibrium Green’s Function (NEGF) formalism under the ballistic limit along with dissipative effects in terms of self-energy at both the source and drain ends. Effect of structural parameters on drain current, channel length modulation parameter, quantum capacitance, transconductance, subthreshold swing (SS) and drain induced barrier lowering (DIBL) are studied assuming occupancy of only a few lower sub-bands, where comparison is performed taking all other factors, biases and dimensions identical. High-k dielectric (HfO2) independently surrounding the quantum wire (GaAs) and carbon nanotube shows higher drain current and transconductance for GAAQWT but lower quantum capacitance than that obtained for CNTFET. A smaller variation of CLM for CNFET speaks in favour of it for digital quantum circuit applications, whereas GAAQWT is suitable candidate for low-power applications. Effect of structural parameters is investigated within fabrication limit to analyse the effect on electrical characteristics under lower biasing ranges.

Improving the intrinsic cut-off frequency of gate-all-around quantum-wire transistors without channel length scaling

Progress in high-frequency transistors is based on reducing electron transit time, either by scaling their lengths or by introducing materials with higher electron mobility. For gate-all-around quantum-wire transistors with lateral dimensions similar or smaller than their length, a careful analysis of the displacement current reveals that a time shorter than the transit time controls their high-frequency performance. Monte Carlo simulations of such transistors with a self-consistent solution of the 3D Poisson equation clearly show an improvement of the intrinsic cut-off frequency when their lateral areas are reduced, without length scaling.

A novel self consistent calculation approach for the capacitance‐voltage characteristics of semiconductor quantum wire transistors based on a split‐gate configuration

PurposeThe purpose of this paper is to develop an efficient numerical algorithm for the self‐consistent solution of Schrodinger and Poisson equations in one‐dimensional systems. The goal is to compute the charge‐control and capacitance‐voltage characteristics of quantum wire transistors.Design/methodology/approachThe paper presents a numerical formulation employing a non‐uniform finite difference discretization scheme, in which the wavefunctions and electronic energy levels are obtained by solving the Schrödinger equation through the split‐operator method while a relaxation method in the FTCS scheme (“Forward Time Centered Space”) is used to solve the two‐dimensional Poisson equation.FindingsThe numerical model is validated by taking previously published results as a benchmark and then applying them to yield the charge‐control characteristics and the capacitance‐voltage relationship for a split‐gate quantum wire device.Originality/valueThe paper helps to fulfill the need for C‐V models of quantum wire device. To do so, the authors implemented a straightforward calculation method for the two‐dimensional electronic carrier density n(x,y). The formulation reduces the computational procedure to a much simpler problem, similar to the one‐dimensional quantization case, significantly diminishing running time.

Room temperature single-electron memory and light sensor with three-dimensionally positioned InAs quantum dots

The authors report on the fabrication and characterization of single-electron memories based on site-controlled InAs quantum dots (QDs) embedded in a GaAs/AlGaAs quantum-wire transistor. By using a hole structure template on a modulation-doped GaAs/AlGaAs heterostructure in combination with etching techniques, two single InAs QDs were centrally positioned in a quantum-wire transistor so that pronounced shifts of the transistor threshold occur by charging of the QDs with single electrons. Single-electron read and write functionalities up to room temperature were observed. The memory function can be also controlled by light with a wavelength in the telecommunication range.

Influence of Band Non-Parabolicity on Few Ballistic Properties of III–V Quantum Wire Field Effect Transistors Under Strong Inversion

A simplified yet analytical approach on few ballistic properties of III-V quantum wire transistor has been presented by considering the band non-parabolicity of the electrons in accordance with Kane's energy band model using the Bohr-Sommerfeld's technique. The confinement of the electrons in the vertical and lateral directions are modeled by an infinite triangular and square well potentials respectively, giving rise to a two dimensional electron confinement. It has been shown that the quantum gate capacitance, the drain currents and the channel conductance in such systems are oscillatory functions of the applied gate and drain voltages at the strong inversion regime. The formation of subbands due to the electrical and structural quantization leads to the discreetness in the characteristics of such 1D ballistic transistors. A comparison has also been sought out between the self-consistent solution of the Poisson's-Schrodinger's equations using numerical techniques and analytical results using Bohr-Sommerfeld's method. The results as derived in this paper for all the energy band models gets simplified to the well known results under certain limiting conditions which forms the mathematical compatibility of our generalized theoretical formalism.

Inversion of hysteresis in quantum dot controlled quantum-wire transistor

In a quantum-wire transistor, pronounced floating-gate function of quantum dots is demonstrated with large threshold hysteresis exceeding 1.5 V. The charge state of the quantum dots is electrically controlled and, by applying a critical bias voltage along the quantum wire, the charging mechanism of the quantum dots is deactivated or, for bias voltages above this critical bias point, even inverted. It is shown that the charging as well as discharging of the quantum dots can be selectively switched off; i.e., the floating-gate function of the quantum dots is suppressed. The inversion of the hysteresis is explained within the framework of a capacitor model and the control of the charging mechanism is attributed to a dynamic gate efficiency of the quantum wire, which can be either larger or smaller than the quantum dot gate efficiency.

A nonparabolicity model compared to tight-binding: The case of square silicon quantum wires

This work presents a nonparabolicity (NP) model which is able to improve the effective mass approximation (EMA) for computing transfer characteristics of square silicon quantum wire transistors (SQWT) working in the ballistic regime and subjected to bandstructure effects. The model is found to be treatable within the same transport framework as used in a present 3D EMA Poisson–Schrödinger solver thus keeping a comparable time efficiency. A full-band tight-binding (TB) code provides the bandstructures as well as the transfer characteristics related to a series of SQWTs needed for calibrating the NP model. In comparison with the EMA, the threshold voltage ( V T ) obtained via the NP model is notably closer to the TB data for all wire widths considered in this work. In addition, the NP model is found to satisfactorily predict the increase of the conduction masses belonging to the unprimed conduction valleys of the TB bandstructure.

Schrödinger equation Monte Carlo in three dimensions for simulation of carrier transport in three-dimensional nanoscale metal oxide semiconductor field-effect transistors

A quantum transport simulator, Schrödinger equation Monte Carlo (SEMC) in three dimensions, is presented that provides a rigorous yet reasonably computationally efficient quantum mechanical treatment of real scattering processes within quantum transport simulations of nanoscale three-dimensional (3D) metal oxide semiconductor field-effect transistor (MOSFET) geometries such as quantum wire and multigate field-effect transistors. This work represents an extension of earlier versions of SEMC for simulating quantum transport and scattering in systems with relatively simpler quasi-one-dimensional and quasi-two-dimensional geometries such as quantum-cascade lasers (via SEMC in one dimension) and silicon-on-insulator or dual-gate MOSFETs (via SEMC in two dimensions), respectively. However, the limiting computational considerations can be significantly different. The SEMC approach represents a variation in nonequilibrium Green’s function techniques with scattering as well as carrier injection into the simulation region treated via Monte Carlo techniques. Scattering mechanisms include intravalley and intervalley scatterings, intrasubband and intersubband scatterings via acoustic and optical phonons, and, in the former case, surface roughness scattering. SEMC-3D simulations of a silicon omega-gate nanoscale n-channel MOSFET are provided to illustrate the modeling technique as well as the complexity of scattering effects in such nanoscale devices.

Room temperature memory operation of a single InAs quantum dot layer in a GaAs∕AlGaAs heterostructure

Room temperature (RT) memory operation of a single InAs quantum dot (QD) layer serving as floating gate is demonstrated. In an in-plane gated quantum-wire transistor, the charge state of the self-assembled InAs QDs is controlled by the applied gate voltage. Due to the floating-gate function of the QDs on a nearby transport channel, threshold hysteresis exceeding 200mV and storage times of several minutes are observed. The RT operation is attributed to an optimized positioning of the QDs at the site of a local minimum in the AlGaAs conduction band.

Effect of Size Reduction on Switching Characteristics in GaAs-Based Schottky-Wrap-Gate Quantum Wire Transistors

The effect of size reduction on switching characteristics is investigated experimentally for the low-switching-power operation of GaAs-based quantum wire transistors (QWRTr's) utilizing etched AlGaAs/GaAs nanowires controlled by Schottky wrap gates (WPGs). WPG QWRTr's in which the wire width, W, and gate length, LG, are systematically changed are fabricated and characterized with respect to operation temperature, switching voltage, ΔVG, gate voltage to Fermi energy scaling factor, α, and power-delay product, PDP. When W is less than 200 nm, more than 80% of the fabricated devices exhibit quantized conductance at 30 K. The device with W=40 nm shows a large α of 0.7. Decreasing LG into the sub-100-nm range is found to be effective for improving power consumption, since the short channel effect is suppressed by tight potential control in the WPG structure.

Novel room-temperature functional analogue and digital nanoelectronic circuits based on three-terminal ballistic junctions and planar quantum-wire transistors

Three-Terminal ballistic junctions (TBJs) and planar quantum-wire transistors (QWTs) are emerging nanoelectronic devices with various novel electrical properties. In this work, we realize novel nanoelectronic analogue and digital circuits with TBJs and planar QWTs made on In0.75Ga0.25As/InP two-dimensional electron gas (2DEG) material. First we show that a single TBJ can work as a frequency mixer or a phase detector. Second, we fabricate an integrated nanostructure containing two planar QWTs, which can be used as an RS flip-flop element. Third, we make a nanoelectronic circuit by the integration of two TBJs and two planar QWTs. This circuit shows the RS flip-flop functionalities with much larger noise margins in both high and low level inputs. All measurements in this work are done at room temperature.

In‐situ X‐ray photoelectron spectroscopy characterization of Si interlayer based surface passivation process for AlGaAs/GaAs quantum wire transistors

AbstractDetailed properties of the Si interface control layer (Si ICL)‐based surface passivation structure are characterized by in‐situ X‐ray photoelectron spectroscopy (XPS) in an ultra‐high vacuum multi‐chamber system. Si ICLs were grown by molecular beam epitaxy (MBE) on GaAs and AlGaAs(001) and (111)B surfaces, and were partially converted to SiNx by nitrogen radical beam. Freshly MBE‐grown clean GaAs and AlGaAs surfaces showed strong Fermi level pinning. Large shifts of the surface Fermi level position corresponding to reduction of pinning took place after Si ICL growth, particularly on (111)B surface (around 500 meV). However, subsequent surface nitridation increased pinning again. Then, a significant reduction of pinning was obtained by changing SiNx to silicon oxynitride by intentional air‐exposure and subsequent annealing. This has led to realization of a stable passivation structure with an ultrathin oxynitride/Si ICL structure which prevented subcutaneous oxidation during further device processing under air‐exposure. The Si‐ICL‐based passivation process was applied to surface passivation of quantum wire (QWR) transistors where anomalously large side‐gating phenomenon was completely eliminated. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Surface-induced large side-gating phenomenon in GaAs quantum wire transistors and its removal by surface passivation using Si interface control layer

Side-gating behaviors of GaAs-based quantum wire transistors (QWRTr’s) were investigated. Using AlGaAs∕GaAs high electron mobility transistor wafer, the QWRTr was fabricated with a nanosized side gate beside the nanowire. Anomalous large side-gating effect was found for the QWRTr. Experiments showed that the large side-gating effect was owing to the strong surface Fermi level pinning around the nanowire, which is caused by a thin layer of deep traps located at the surface. Then, Si interface control layer passivation technology was performed to remove the large side gating.

Phonon exacerbated quantum interference effects in III-V nanowire transistors

In recent years, a great deal of attention has been focused on the development of quantum wire transistors as a means of extending Moore’s Law. Here we present, results of fully three-dimensional, self-consistent quantum mechanical device simulations of InAs tri-gate nanowire transistor (NWT). The effects of inelastic scattering have been included as real-space self-energy terms. We find that the position of dopant atoms in these devices can lead a reduction in the amount of scattering the carriers experience. We find that the combination of deeply buried dopant atoms and the high energy localization of polar optical phonon processes allow devices to recover their ballistic behavior even in the presence of strong inelastic phonon processes. However, we find that dopant atoms close to the source-channel interface cause severe quantum interference effects leading to significant performance reduction.

Ballistic recovery in III-V nanowire transistors

In recent years, a great deal of attention has been focused on the development of quantum wire transistors as a means of extending Moore’s law. Here the authors present results of fully three-dimensional, self-consistent quantum mechanical device simulations of InAs trigate nanowire transistor. The effects of inelastic scattering have been included as real-space self-energy terms. They find that the position of dopant atoms in these devices can lead to a reduction in the amount of scattering the carriers experience. They find that the combination of deeply buried dopant atoms and the high energy localization of polar optical phonon processes allow devices to recover their ballistic behavior even in the presence of strong inelastic phonon processes.

Bias Voltage Controlled Memory Effect in In-Plane Quantum-Wire Transistors With Embedded Quantum Dots

The drain-current through GaAs/AlGaAs quantum-wire transistors (QWTs) with InGaAs quantum dots (QDs) exploited as floating gates is studied for temperatures up to 150 K. It is found that the threshold hysteresis between the up sweep and the down sweep of the gate voltage decreases with increasing bias voltage and is suppressed at a critical bias voltage. It is proposed and demonstrated that these QWTs show logic OR-gate functionality with the option to store the corresponding logic state by switching the bias voltage to zero. The authors explain this behavior by a bias voltage dependent efficiency of the gate to control differently the QDs and the quantum wire

Device interference in GaAs quantum wire transistors and its suppression by surface passivation using Si interface control layer

In order to establish feasibility of high density integration of gate-controlled GaAs nanodevices, this article investigates device interference in GaAs-based quantum wire transistors (QWRTrs) by using a side-gating test structure and attempts to suppress the observed anomalously large side-gating with surface passivation using a silicon interface control layer (Si ICL). QWRTrs were formed on AlGaAs∕GaAs etched quantum wires (QWRs) and were controlled by nanometer sized Schottky wrap gates. A Schottky side gate was formed at a distance dsg from the QWR. When dsg was large, the QWRTr showed weak side gating which can be explained by the electrostatic side gating. However, when the side gates was placed close to the nanowire with dsg<500nm, anomalously large side gating started to take place which cannot be explained by the electrostatic side gating. On the basis of detailed measurements of side-gating behavior and side-gate leakage currents at various temperatures, the anomalous side gating was explained by a model in which occupation of deep traps at the back AlGaAs∕GaAs interface of the QWR is modulated by tunneling injection of electrons from the side-gate edge resulting from strong Fermi level pinning by surface states. Based on this model, attempts to reduce surface states by surface passivation were made. Formation of the Si ICL structure on a regrown thin GaAs cap layer completely removed the anomalous side-gating effect.

Phonon Limited Performance of III-V Nanowire Transistors

We use a fully self-consistent three-dimensional quantum mechanical transport formalism to examine the performance of InAs based quantum wire transistors both in the ballistic limit and with phonon scattering included. We present a method for the inclusion of polar optical phonon scattering as a real-space self-energy term. We find that the ballistic performance of the devices can be recovered if the dopants in the system are kept away from the channel entrance and exit. When dopants are present at these key points, we find that the altered carrier energy, particularly in the source, has a significant impact on the device. This ballistic recovery is aided by the fact that at higher energies, polar optical phonon scattering loses its non-locality which leads to a reduced scattering rate in these confined systems.

Scattering in quantum simulations of silicon nanowire transistors

One of the most interesting devices under exploration now is the nanowire transistor. Because of the size of these devices, there have been many approaches to implement full quantum mechanical simulations. To date, most of these approaches have considered only ballistic transport or impurity scattering through the self-consistent potential. However, in order to understand the operation of any type of semiconductor device, one must consider the effects of scattering. For many years, Monte Carlo has been the workhorse that has yielded great insight into the operation of a wide variety of semiconductor devices because of the ease in treating various scattering effects, and these approaches have been modified for simple quantum effects. But in these very small devices, a more exact treatment of the quantum effects is required. To address this problem, we have developed a proper real-space self-energy which can be included within the Hamiltonian formalism for either the recursive scattering matrix approach or the non-equilibrium Green's function approach. More importantly, this treatment with the proper self-energy is norm-conserving but converts the Hamiltonian to a non-Hermitian form, as expected. When the model is applied to a gated quantum wire transistor structure under bias, we find that the scattering due to phonons causes the electrons to scatter to higher subbands than previously available during simple ballistic transport, with the result that the ballistic-to-diffusive transition in Si devices occurs for gate lengths of the order of 1 nm.

Self‐consistent calculations of phonon scattering rates in the GaAs transistor structure with one‐dimensional electron gas

AbstractSelf‐consistent calculations of acoustic and polar optical phonon scattering rates in GaAs quantum wire transistor structures were carried out with account of collisional broadening. The influence of the gate bias on the scattering rates was examined, too. It was shown that in order to treat the scattering rates rigorously it is important to search for electron energy levels by means of the self‐consistent solution of Schrödinger and Poisson equations and to take into account the collisional broadening. (© 2005 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)