Quantum-dot Cellular Automata Cells Research Articles

Reversible arithmetic and logic unit using a novel reversible NRRG gate in quantum dot technology

Quantum-dot Cellular Automata (QCA) has become one of the promising studies for nano-scale computing. QCA is one of the candidate technologies to be replaced with CMOS technology. QCA technology not only reduces power consumption and delay but also increases operating frequency and speed. The arithmetic logic unit is the essential component in a processor that performs arithmetic and logical operations. This paper presents a novel 5 × 5 reversible logic gate called the NRRG (Norouzi_Rasouli Reversible Gate) which can be used as the basic building block of 4:1 and 8:1 reversible multiplexers. Then, we have designed a RALU (reversible arithmetic and logic unit) using this gate. Our design can perform 20 operations such as AND, NAND, OR, XOR, XNOR, COPY, addition, and increment. The proposed QCA RALU requires 0.44 μm2 area, 480 QCA cells, and 10 clock phases. The proposed design needs less cell count, delay, and cost of QCA compared to previous works. The structure is implemented without any rotated cells and only uses one layer which improves the manufacturability of the design. The architectures are designed and simulated using QCA Designer 2.0.3.

Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model.

Quad-functioning parity layout for nanocomputing: A QCA design

Quantum dot cellular automata (QCA) is considered an alternative to conventional technologies like CMOS (Complementary Metal-Oxide-Semiconductor) technology due to its potential for lower power consumption, higher speed, and increased device density. QCA introduces a novel approach to designing nano communication circuits and systems. Nano communications data mistakes are detected via parity generators and checkers. The parity bit of each data block ensures that the number of 1′s is either even or odd. Consequently, the system requires four circuits: an even parity generator, an odd parity generator, an even parity checker, and an odd parity checker. The whole system requires more space and cell complexity. In this work, we propose a QCA architecture that serves as a generator for both even and odd parities, as well as a checker for both even and odd parities. It is a quad-functioning circuit that performs four distinct operations within a single design, utilizing 118 QCA cells and occupying an area of 0.17 μm2. The recommended approach uses an efficient XOR gate, resulting in improvements across several performance metrics. QCAPro calculates energy dissipation and design parameters. The recommended QCA circuit outperformed similar QCA circuits in size, complexity, and energy dissipation. The circuit's design cost functions are also low. There has been a 17% reduction in latency and an 86% improvement in QCA-specific costs when compared to the optimal existing design. Moreover, it necessitates a 40% reduction in majority gate usage. The proposed design may compete effectively with other equivalent higher-order circuit designs by reducing the need for multiple blocks in conventional circuits to execute the same task. This architecture holds potential benefits for nano processors and nano communication networks.

An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology

The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount significance. On the other hand, the quickly developing Internet of Things (IoT) market aims to produce high-speed, low-power gadgets. A comparator is a crucial component in the analog-to-digital conversion process used by IoT devices. In order to meet the power and latency requirements of IoT devices, a high-speed, low-power comparator is greatly required. Consequently, the strategic design of comparators within the QCA framework has ascended to a position of heightened importance in cutting-edge research. This study undertakes the formidable task of conceiving QCA-centric designs for MV32, the majority gate, and the inverter gate, thereby contributing to the development of a sophisticated multi-layered comparator architecture for IoT devices. In the realization of a three-layer comparator implemented in QCA, we attain an impressive feat—a minimal clock zone demanding only a singular clock pulse coupled with exceptional compaction (measuring at a mere 0.03 μm2). Experimental revelations corroborate the substantial advancement of the proposed design over traditional methodologies, particularly in terms of circuit area, cell count, and clock efficiency.

Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells

Extensive research is now being conducted on the design and construction of logic circuits utilizing quantum-dot cellular automata (QCA) technology. This area of study is of great interest due to the inherent advantages it offers, such as its compact size, high speed, low power dissipation, and enhanced switching frequency in the nanoscale domain. This work presents a design of a highly efficient RAM cell in QCA, utilizing a combination of a 3-input and 5-input Majority Voter (MV) gate, together with a 2 × 1 Multiplexer (MUX). The proposed design is also investigated for various faults such as single cell deletion, single cell addition and single cell displacement or misalignment defects. The circuit under consideration has a high degree of fault tolerance. The functionality of the suggested design is showcased and verified through the utilization of the QCADesigner tool. Based on the observed performance correlation, it is evident that the proposed design demonstrates effectiveness in terms of cell count, area, and latency. Furthermore, it achieves a notable improvement of up to 76.72% compared to the present configuration in terms of quantum cost. The analysis of energy dissipation, conducted using the QCAPro tool, is also shown for various scenarios. It is seen that this design exhibits the lowest energy dispersion, hence enabling the development of ultra-low power designs for diverse microprocessors and microcontrollers.

Novel level and edge-triggered universal shift registers with low latency in QCA technology

Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performance in regards of the number of cells, occupied area, delay, and power. These designs also have reset abilities. Simulations show that the proposed 4-bit level triggered universal shift register with reset ability has 1057 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clock. In addition, the proposed rising edge triggered 4-bit universal shift register with reset ability has 1085 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clocks.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

Novel energy efficient RND inverter using quantum dot cellular automata in nanotechnology

Quantum-Dot Cellular Automata (QCA) is a promising technology for designing high-performance and efficient logic circuits, surpassing traditional Complementary Metal Oxide Semiconductor approaches. In today’s digital era, the demand for digital circuits with high speed, device density, and energy efficiency is paramount. This paper focuses on the innovative Rotated Normal Cells with Displacement (RND) inverter model, employing normal and rotated cells with a 10 nm displacement through a cell interactive method. Digital circuits designed using the RND inverter exhibit superior performance compared to existing designs. The proposed RND inverter gate utilizes only four QCA cells, occupying a total area of 4525.55 nm2. With a total energy dissipation of 0.508 meV and an average energy dissipation per cycle of 0.0462 meV, it achieves a polarization of 9.77. The novel RND inverter demonstrates a 44% improvement in cell area and a 63% reduction in total area compared to current designs, offering enhanced energy efficiency with 0.26 improved polarization. The RND inverter and the digital circuits facilitate finding applications in efficiently constructing various components within Quantum Computers. Beyond quantum computing, the RND inverter proves applicable in designing Nano-sized electronic gadgets and temperature-controlled circuits, showcasing its versatility across diverse technological applications.

Universal and Reversible Gate Design in Quantum-dot Cellular Automata Nanotechnology

Background: Growing progress in the field of nanoelectronics necessitates ever more advanced nanotechnology due to the continued scaling of conventional devices. For the purpose of fabricating current integrated circuits (ICs), Quantum-dot cellular automata (QCA) nanotechnology is the most suitable substitute for complementary metal oxide semiconductor (CMOS) technology. The problem of short-channel secondary effects at the ultra-nanoscale level confronts CMOS technology Aims: QCA nanotechnology overcomes the issues of conventional logic circuit design methods due to its numerous advantages. This research work aims to design an energy-efficient, reliable, universal, 3×3, and reversible logic gate for the implementation of various logical and Boolean functions in QCA nanotechnology. Objective: It is desirable for portable systems to have a small size, extremely low power consumption, and a clock rate in the terahertz. As a result, QCA nanotechnology is an incredible advancement for digital system applications and the design of future systems. Methods: This research article proposes a novel, ultra-efficient, multi-operative, 3×3 universal reversible gate implemented in QCA nanotechnology using precise QCA cell interaction. The proposed gate is used for the implementation of all the basic logic gates to validate its universality. The implementation of all thirteen standard Boolean functions establishes the proposed gate's multi-operational nature. The energy dissipation analysis of the design has been presented for the varying setups. Results: The proposed gate is area-efficient because it uses minimum QCA cells. Various logical and Boolean functions are effectively implemented using the proposed gate. The result analysis establishes the minimum energy dissipation of the proposed design and endorses it as an ultra-efficient design. Conclusion: The QCA cell interaction method demonstrates the best way to design a universal, reversible, and multi-operative gate.

Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit.

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell and electrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lower power, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer's central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCADesigner-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area.

Design of BCD Adder Using QCA Technology

Abstract: Quantum-dot Cellular Automata (QCA) technology is a promising alternative to traditional complementary metaloxide-semiconductor (CMOS) technology for implementing digital circuits due to its potential for high speed, low power consumption, and small size. In this paper, we present a design for a Binary Coded Decimal (BCD) adder using QCA technology. The BCD adder is a crucial building block for arithmetic operations in decimal representation. The proposed design uses QCA cells to perform the addition operation of two BCD digits, which are encoded as a 4-bit binary number. The design includes a full-adder circuit, a BCD-to-binary converter, and a carry-lookahead adder. Simulation results using QCA Designer software demonstrate the functionality and feasibility of the proposed BCD adder design. The proposed design provides a promising alternative to traditional CMOS-based BCD adders and can contribute to the development of QCA-based digital circuits

A quantum-based building block for designing a nanoscale full adder circuit with power analysis

Quantum-dot cellular automata (QCA) concentrates charges using the Coulomb interaction. Despite the nanometric scale and the extremely high projected working frequency, the need for transmission is eliminated, resulting in very low power consumption. Few designs exist to reduce energy consumption and provide simple access to inputs and outputs. There have been few studies on the optimizations of majority and inverter gates for different types of adders. The design of adders using a QCA framework is becoming more significant in current research. This work aims to design a multi-layered full adder architecture that uses three-input XOR and a majority gate for the QCA framework. The primary goal of this article is to design a circuit with low power consumption and easy access to inputs and outputs. For a full adder by the QCA technology, a minimum clock zone of two clocks and 18 QCA cells by high compaction (0.02 μm2) are obtained. Additionally, the synthesis of high-level logic establishes the design's utility. In comparison to traditional design methodologies, experimental results show considerable design level gains in terms of circuit area, cell count, power, and clock. Experiments show how the design level has significantly improved compared to traditional design methodologies regarding circuit area, cell count, power, and clock.

Designing a one-bit coplanar QCA ALU using a novel robust area-efficient three-input majority gate design

Quantum-dot cellular automata (QCA) which is a suitable alternative to conventional CMOS technology is susceptible to some defects in chemical synthesis and deposition phases of circuit fabrication. Besides, the majority gate is one of the most important primary gates for designing digital circuits in this emerging technology. Designing a fault-tolerant majority gate is one of the hot topics in QCA technology. Most previous works tried to improve the majority gate reliability by increasing the number of QCA cells which resulted in occupying more area. In this paper we propose a novel area-efficient three-input majority gate which can tolerate the single-cell omission and extra-cell deposition defects by 86% and 75%, respectively. The proposed majority gate consists of 11 simple QCA cells with $$0.006\,$$ µ $$\hbox {m}^{2}$$ and 1.62 e-002 MeV area and energy consumption, respectively. A complete fault tolerance analysis for our proposed majority gate against cell omission, extra-cell deposition, and cell displacement and misalignment defects is also provided. We design a fault-tolerant coplanar fulladder/fullsubtractor and a two-to-one multiplexer using the proposed majority gate and compare it with the same previous works. Simulation results from QCADesigner 2.0.3 and QCADesigner-E show that in all cases our proposed robust circuits can reduce the area consumption. Finally, we implement a fault-tolerant coplanar one-bit ALU using the proposed circuits that can perform four logical and mathematical operations.

A systematic and bibliometric review of the latest techniques in quantum-dot computers

When designing and manufacturing logic circuits, minimal energy loss, high packing densities, and functioning at Tera-hertz frequencies are highly sought characteristics. Due to the rapid growth of large-scale integration technology, producing a dependable architecture with minimal power consumption is crucial. Quantum dot Cellular Automata (QCA) is a potential substitute to the traditional semiconductor-based technique for constructing logic circuits in the nano-scale range due to the promising implementation of these highly desired properties. QCA cells may be used to create arbitrary circuits by following a few straightforward layout criteria. In contrast to conventional computers, quantum computers work faster by utilizing the principles of quantum physics. It is crucial to consider what applications these devices may aid, given that quantum computing technologies are on the cusp of commercialization and quantum dominance. As a result, this paper offers a thorough and bibliometric assessment of the most recent quantum-dot computing methods. In order to present some intriguing directions for any future study, it provides the benefits and drawbacks of the evaluated mechanisms and their significant problems. According to the results, reversible logic in QCA may be regarded as one of the most hopeful technologies for next-generation computers.

Parity Generators for Nanocommunication Systems Using QCA Nanotechnology

Quantum-dot cellular automata (QCA) nanotechnology has the capability to design highly-dense, ultra-low power, and high-speed digital circuits at ultra-deep sub-micron (ultra-DSM) level. QCA nanostructure provides a transistor-free operation that saves large energy dissipation as compared to the conventional metal oxide semiconductor field effect transistor (MOSFET) technology. In this paper, 3-input exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are presented using QCA cells. XOR and XNOR (XOR-XNOR) gates are further utilized to design the 2-, 3-, 4-, and 5-bit even and odd parity generators. The QCA-based 3-input XNOR gate is constructed using only 10 QCA cells and two clock phases. The target of the presented designs is to use the minimum count of QCA cells in a simplistic way to form the higher bit-size parity generators. The comparative analyses for the different performance metrics are showing that the developed designs are performing well for the cell count, latency, area, and layout cost as compared to the existing designs. Energy dissipation for the designs is calculated to check the energy efficiency by using the QCA Designer-E and QCA Pro tools.

New Methodology for the Design of Nanostructured Integrated Circuits

Background: A metal oxide semiconductor field effect transistor (MOSFET) is widely used to make integrated circuits (ICs). MOSFET devices are reaching the practical limitations for further scaling in the nanoscale regime. It motivates the researchers to explore and develop new ways to advance the electronics industry. Quantum-dot cellular automata (QCA) is a potential way to replace the MOSFET devices in the nanoscale regime. QCA nanotechnology not only solves the issue of scalability but also degrades the leakage current. It has numerous benefits, such as a highly dense design, fast speed, and energy efficiency compared to complementary metal-oxide-semiconductor (CMOS) technology. Objective: An extensive study of QCA nanotechnology is needed to quickly understand the field. Optimizing the QCA designs is the mandatory requirement to minimize the occupied cell area, latency and quantum cost. The preliminary knowledge of QCA nanotechnology boosts the idea of generating different logic functions. This review paper presents the methodology for making the fundamental logic gates using QCA nanotechnology. XOR gate is commonly used to implement popular circuits such as adders, subtractors, comparators, code converters, reversible gates etc. The various available QCA-based 2-input XOR gate designs are discussed and compared for the different performance metrics. Methods: Columbic interaction causes logical operations, and data is transferred from one cell to another cell using cell-to-cell interaction. A specific arrangement of QCA cells produces a specific logic. QCA Designer tool using a Bi-stable simulation engine is used to design different digital circuits. Results: This review paper deals with the design of the 2-input XOR gate. The considered performance metrics for the comparison purpose are cell count, occupied area, clock cycle, and quantum cost. Existing works on 2-input XOR gates show that a minimum of 8 QCA cells are needed for a 2-input XOR gate using QCA nanotechnology. A single clock cycle-based 2-input XOR gate requires at least 9 QCA cells. The quantum cost can be minimized by reducing the number of QCA cells and clock cycles. Conclusion: This review paper helps the circuit designers to select the appropriate 2-input XOR gate for the design of complex circuits. Circuit designers can use the fundamental concepts detailed in the paper to implement any Boolean function and optimize it for the existing designs. A researcher had developed a 2-input XOR gate using only 8 QCA cells with 0.50 clock cycles. Therefore, designers can start from here to further optimize the 2-input XOR gate with a single clock cycle.

Tree router design using a novel optimal QCA DEMUX

Quantum-dot cellular automata (QCA) is a new technology to replace CMOS technology in digital circuits. This replacement is necessary since further miniaturization of CMOS devices has posed serious challenges. In this paper, an optimized 1:2 demultiplexer (1:2 DEMUX) as a tree network switch is proposed. The tree network is examined, and the switches, which are the main components of the network, are used for routing. The proposed 1:2 DEMUX uses a rotated majority gate (RMG) based on QCA technology. According to the evaluation of the proposed 1:2 DEMUX circuit, 16 QCA cells are used with a total area and latency of 0.02μm2 and 0.25 clock cycles, respectively. A comparison with the best reported similar designs shows 15.78% improvement in the complexity, cell area, and area usage of the proposed 1:2 DEMUX. Another parameter that plays a very important role in QCA circuits is energy consumption, which can be measured with QCAPro software. In the proposed DEMUX circuit, the values of energy dissipation for 0.5, 1, and 1.5 Ek are 16.75, 24.84, and 34.6 meV respectively. The proposed router is the first of its kind that uses QCA-based DEMUX. This router has 146 cells, and its total area and latency are equal to 0.25μm2 and 0.75 clock cycles, respectively.

3-bit Shift Register Using QCA Nanotechnology

Background:: Quantum-dot Cellular Automata (QCA) is a new emerging nanotechnology that has been proven to be an improved alternative to complementary metal oxide semiconductor (CMOS) technology. It consists of a group of cells that can perform computational functions when combined and arranged in a particular manner. Objective:: The Flip-Flops are widely affiliated with the circuits of logical and arithmetic unit structures that are used for the processors. Data (D) Flip-Flop is the most important and widely used Flip-Flop among all different types due to its better performance and efficiency. Hence, an efficient D Flip-Flop needs to be developed using QCA nanotechnology. Method:: This paper proposes a new design for D Flip-Flop in QCA nanotechnology. The proposed D Flip-Flop has 28 quantum cells and covers an area of 0.03 μm2 . Furthermore, the paper presents a new design for a 3-bit Shift Register using the proposed D Flip-Flops in QCA nanotechnology keeping in mind the importance of the same in storing and transferring multiple bits of data. Result:: The proposed D Flip-Flop and the 3-bit Shift Register are compared with the existing QCAbased designs. The proposed Shift Register has 100 quantum cells and covers an area of 0.11 μm2 . Conclusion:: The comparison concludes that the proposed D Flip-Flop and the 3-bit Shift Register have used a lesser number of QCA cells and covered smaller areas than the previous works. The proposed designs have been designed in a single layer without any crossover.

QCA-Based Reliable Fundamental Units for Multiplexer-Demultiplexer and D-Flip-Flop

Quantum-dot cellular automata (QCA) is an advanced nanotechnology. It is applied to delineate nanoscale technology-based logic circuits. It can potentially be replaced the complementary metal oxide semiconductor (CMOS) technology. This paper proposes an optimal and single clocked multiplexer (Mux) circuit, which is made with the help of 12 number of QCA cells in QCA nanotechnology. The proposed Mux circuit is designed in such a way that it can be used easily for the design of the demultiplexer (DeMux) and data flip-flop (DFF) circuits. The proposed Mux is easily converted to DeMux by exchanging the input and output terminals only. The effectiveness of the proposed Mux, DeMux, and DFF is examined with the designs that are similar and available in literature using the QCA Designer-E and QCA Pro tools. The design of the proposed Mux is 89.06% fault-tolerant and has decreased the quantum cost by 62.50% as compared to best reported design. Energy measurement plays a key role when designs are operating at nanoscale level. Energy approximation is done with the help of the QCA Pro tool. The proposed designs are more energy efficient compared to the existing works.