Quadrature Generation Research Articles

A 28 GHz Highly Linear Up-Conversion Mixer for 5G Cellular Communications

In this paper, we present a highly linear direct in-phase/quadrature (I/Q) up-conversion mixer for 5G millimeter-wave applications. To enhance the linearity of the mixer, we propose a complementary derivative superposition technique with pre-distortion. The proposed up-conversion mixer consists of a quadrature generator, LO buffer amplifiers, and an I/Q up-conversion mixer core and achieves an output third-order intercept point of 15.7 dBm and an output 1 dB compression point of 2 dBm at 27.6 GHz, while it consumes 15 mW at a supply voltage of 1 V. The conversion gain is 11.4 dB and the LO leakage and image rejection ratio are −56 dBc and 61 dB, respectively, in the measurement. The proposed I/Q up-conversion mixer is suitable for 5G cellular communication systems.

Independent Control of Active and Reactive Power Flow for a Single-Phase, Unidirectional Onboard Power Converter Connecting the DC Power Bus to the AC Bus

The paper presents a proposed system that supplies a 400 Hz single-phase onboard grid from the DC onboard bus. This system enables independent compensation of reactive power in the AC grid. Independent control of active and reactive power flow requires the decomposition of current in the grid into active and reactive components. Independent control of active and reactive power requires the use of synchronizers that operate in the dq frame system. If synchronization is performed with a single-phase grid, the transformation of dq requires the virtual quadrature signals. Standard quadrature signal generation systems use a second-order generalized integrator. To improve the dynamics of the system, the paper proposes a new quadrature generator that operates on the basis of trigonometric calculations instead of a second-order integration system. The developed system was implemented in a proportional-resonant current control system. Tests carried out in steady state and in dynamic states related to typical grid disturbances proved significantly better dynamic properties than those of a standard integrator-based system.

A High-Efficiency High-Power 170-176-GHz Frequency Stabilized Quadrature Radiator

In this article, we present a high-efficiency high-power radiator with on-chip frequency stabilization and quadrature generation capabilities for short-coherence-time imaging and wireless communication applications. To achieve efficient sub-terahertz (sub-THz) signal generation, a systematic design approach using the device-centric gain-plane optimization is employed. In addition, an on-chip frequency stabilization mechanism utilizing the inherent power level variation over the tuning range is proposed. To show the feasibility of this approach, a 170–176-GHz radiator prototype is demonstrated, which has an effective isotropic radiated power (EIRP) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 24.6 dBm and a dc-to-RF efficiency of 9.2%. The prototype is fabricated in a 55-nm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) process and achieves one of the highest output power and dc-to-RF efficiency among designs beyond <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\text{max}}$</tex-math> </inline-formula> /2. The frequency stabilization mechanism reduces the long-term frequency drifts by 4.3 times.

Układ regulacji jednofazowego przekształtnika fotowoltaicznego ze zmodyfikowanym generatorem kwadraturowym

Control of a photovoltaic converter connected to a single-phase grid requires synchronization with the fundamental component of the voltage. This is performed by the Park transformation of the measured voltage to a rotating orthogonal xy frame. This transformation in single-phase systems requires quadrature signals. The paper proposes that a quadrature generator replace the standard second-order generalized integrator

A compact 90–96 GHz 6‐bit passive vector modulator phase shifter in 28‐nm CMOS for phase array applications

AbstractThis letter presents a 90–96 GHz 6‐bit digital control passive vector modulator phase shifter (PS) in a 28‐nm complementary metal–oxide–semiconductor for phase array application. In PS, a full differential directional coupler as a quadrature generator (QG) is proposed, which achieves wide bandwidth and a high‐performance orthogonal network by introducing more pole‐zero pairs. In the vector modulator, two 6‐bit binary‐weighted vector modulators, respectively scale the quadrature signal generated by QG to achieve a high‐resolution vector phase. The measured PS cover and the minimal root mean square (RMS) phase error is and RMS gain error 0.3 dB at 93 GHz, respectively. The fabricated PS occupies excluding pads with no power consumption.

A 32–40 GHz 7-bit Bi-Directional Phase Shifter With 0.36 dB/1.6° RMS Magnitude/Phase Errors for Phased Array Systems

This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$220\times 630\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> and has no power consumption.

A CMOS Vector-Sum Phase Shifter for 5G mm-Wave Application

This paper presents a wideband CMOS vector-sum phase shifter (VSPS) targeting the n260 band of 5G communication. A differential quadrature generator is implemented using a Marchand balun and two 90° coupled-line couplers to improve robustness to process and temperature variations. The quadrature vector signals are combined by a following vector modulator that adopts a double Gilbert-cell topology. The linearity and input-matching performance are enhanced at the expense of extra DC consumption by stacking a current source with high bias. The measurement shows that the VSPS provides a continuous 360° phase shift with an average insertion loss of 16.3 dB at 37 GHz. The root-mean-square (RMS) amplitude and phase errors maintain less than 1.5 dB and 4.9°, respectively, from 30.9 GHz to 41.7 GHz. The input-referred 1-dB compression point is 5.7 dBm at 38 GHz. It is also demonstrated by 484-state measurement that the phase and amplitude can be adjusted in a fine resolution.

2.4-GHz Low-Power Low-IF Receiver With a Quadrature Local Oscillator Buffer for Bluetooth Low Energy Applications

In this brief, a 2.4-GHz low-power single-quadrature low-IF Bluetooth low energy receiver employing a quadrature local oscillator (LO) buffer is presented for Internet of Things applications. The quadrature LO buffer, which consists of common-source amplifiers with capacitive degeneration, compensating resistors, compensating PMOS transistors and LC tanks, performs quadrature generation and supplies quadrature signals to a single-quadrature mixer, thus eliminating an additional circuitry for quadrature generation in the LO path and saving dc current consumption. The implemented receiver consists of a low-noise amplifier, a G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -stage, double-balanced current-mode passive mixers, transimpedance amplifiers, an active- RC complex bandpass filter, and the quadrature LO buffer. Fabricated in a 65-nm CMOS process, the implemented receiver achieves a noise figure of 8.16 dB, a conversion gain of 54.5 dB, an image rejection ratio of 32.1 dB, and an input-referred third-order intercept point of -27.5 dBm. It draws a bias current of 2.5 mA from a nominal supply voltage of 0.8 V, and the active die area is 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Fast multipole methods for the evaluation of layer potentials with locally-corrected quadratures

While fast multipole methods (FMMs) are in widespread use for the rapid evaluation of potential fields governed by the Laplace, Helmholtz, Maxwell or Stokes equations, their coupling to high-order quadratures for evaluating layer potentials is still an area of active research. In three dimensions, a number of issues need to be addressed, including the specification of the surface as the union of high-order patches, the incorporation of accurate quadrature rules for integrating singular or weakly singular Green's functions on such patches, and their coupling to the oct-tree data structures on which the FMM separates near and far field interactions. Although the latter is straightforward for point distributions, the near field for a patch is determined by its physical dimensions, not the distribution of discretization points on the surface.Here, we present a general framework for efficiently coupling locally corrected quadratures with FMMs, relying primarily on what are called generalized Gaussian quadratures rules, supplemented by adaptive integration. The approach, however, is quite general and easily applicable to other schemes, such as Quadrature by Expansion (QBX). We also introduce a number of accelerations to reduce the cost of quadrature generation itself, and present several numerical examples of acoustic scattering that demonstrate the accuracy, robustness, and computational efficiency of the scheme. On a single core of an Intel i5 2.3 GHz processor, a Fortran implementation of the scheme can generate near field quadrature corrections for between 1000 and 10,000 points per second, depending on the order of accuracy and the desired precision. A Fortran implementation of the algorithm described in this work is available at https://gitlab.com/fastalgorithms/fmm3dbie.

A Reduction of Peak-to-Average Power Ratio Based Faster-Than-Nyquist Quadrature Signals for Satellite Communication

The increase in the throughput of digital television and radio broadcasting (DVB) channels can be achieved due to application of signals with a compact spectrum and a relatively small peak-to-average power ratio (PAPR). The reason is the usage of traveling wave tubes (TWT) for amplifying and transmitting signals from a satellite repeater in DVB-S2X systems. At the same time, given that the bandwidth allocated for transmission should be used as efficiently as possible, a high reduction rate of out-of-band emissions level is required. The most effective solution in this direction is the transition to spectrum-economic signals, such as optimal Faster-Than-Nyquist (FTN) signals, which can provide a certain reduction rate of the out-of-band emissions level and minimum acceptable PAPR. This article proposes a method for obtaining optimal FTN pulses, which have symmetry in time domain, with specified PAPR and reduction rate of out-of-band emissions for the quadrature phase shift keying (QPSK) and offset quadrature phase shift keying (OQPSK). The possibility of synthesizing signals with OQPSK modulation is presented theoretically for the first time. Optimal FTN signals can provide PAPR reduction by at most 3 dB and outperform known root raised cosine (RRC) pulses. The simulation model adopts an architecture for quadrature generation of optimal FTN signals with OQPSK modulation with blocks for adjustable pre-amplification, clipping, and power amplification. The proposed signals can be used to increase the spectral and energy efficiencies of satellite broadcasting systems, such as DVB-S2/S2X, as well as low-rate return channels of interactive broadcasting systems with a frequency resource shortage.

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

In this paper, a 2.4 GHz Bluetooth low energy receiver employing a power-efficient quadrature RF-to-baseband-current-reuse architecture is presented for low-power low-voltage internet of things applications. The proposed quadrature RF-to-baseband-current-reuse RF front-end consists of a low-noise transconductance amplifier, an active-type polyphase filter-based quadrature generator, transimpedance amplifiers, and double-balanced current-mode passive mixers on a single dc current path. An input matching network is used to perform power-constrained simultaneous noise and input power matching and 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> noise reduction in the RF and baseband domains, respectively. The quadrature RF signals are provided to the single-quadrature mixers through an embedded active-type polyphase filter-based quadrature generator. The implemented Bluetooth low energy receiver is composed of the RF-to-baseband-current-reuse RF front-end, IF amplifiers, two-stage passive- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> polyphase filter, and fifth-order Chebyshev-II <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-C</i> filters. The proposed design was fabricated using a 65-nm CMOS process and characterized primarily in the Bluetooth low energy operating frequency bands. The active die area of the implemented receiver was 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the receiver drew a bias current of 1.41 mA from a nominal supply voltage of 0.8 V. The Bluetooth low energy receiver achieved a noise figure of 13.2 dB, conversion gain of 42 dB, image rejection ratio of more than 30 dB, and input-referred third-order intercept point of −25 dBm.

2.4-GHz Bluetooth Low Energy Receiver Employing New Quadrature Low-Noise Amplifier for Low-Power Low-Voltage IoT Applications

In this article, a 2.4-GHz Bluetooth low-energy (BLE) receiver employing a new quadrature low-noise amplifier (LNA) is presented for low-power low-voltage Internet of Things (IoT) applications. The proposed quadrature LNA consists of a common-source (CS) amplifier with inductive degeneration, an active-type poly-phase filter (PPF), and an LC tank. The proposed active-type PPF between the CS amplifier and the LC tank provides quadrature generation, and the CS amplifier determines and optimizes the overall LNA performance parameters. Moreover, the proposed active-type PPF shares the dc bias current with the CS amplifier, thereby eliminating the necessity for additional current consumption. The implemented BLE receiver is composed of the quadrature LNA, a $G_{m}$ -stage, a double-balanced current-mode passive mixer, a transimpedance amplifier, and an active- RC complex bandpass filter. The proposed design was fabricated in a 65-nm CMOS process and mainly characterized in the BLE operating frequency bands. The receiver achieves a noise figure of 8.2 dB, a conversion gain of 49.5 dB, an image rejection ratio of more than 33 dB, and an IIP3 of −25.75 dBm. The active die area of the implemented receiver is 1.16 mm2, and it draws a bias current of 2.7 mA from a nominal supply voltage of 0.8 V.

Higher-order finite elements for embedded simulation

As demands for high-fidelity physics-based animations increase, the need for accurate methods for simulating deformable solids grows. While higherorder finite elements are commonplace in engineering due to their superior approximation properties for many problems, they have gained little traction in the computer graphics community. This may partially be explained by the need for finite element meshes to approximate the highly complex geometry of models used in graphics applications. Due to the additional perelement computational expense of higher-order elements, larger elements are needed, and the error incurred due to the geometry mismatch eradicates the benefits of higher-order discretizations. One solution to this problem is the embedding of the geometry into a coarser finite element mesh. However, to date there is no adequate, practical computational framework that permits the accurate embedding into higher-order elements. We develop a novel, robust quadrature generation method that generates theoretically guaranteed high-quality sub-cell integration rules of arbitrary polynomial accuracy. The number of quadrature points generated is bounded only by the desired degree of the polynomial, independent of the embedded geometry. Additionally, we build on recent work in the Finite Cell Method (FCM) community so as to tackle the severe ill-conditioning caused by partially filled elements by adapting an Additive-Schwarz-based preconditioner so that it is suitable for use with state-of-the-art non-linear material models from the graphics literature. Together these two contributions constitute a general-purpose framework for embedded simulation with higher-order finite elements. We finally demonstrate the benefits of our framework in several scenarios, in which second-order hexahedra and tetrahedra clearly outperform their first-order counterparts.

A 2.4-㎓ Low-power Low-IF Receiver Employing a Quadrature Low-noise Amplifier for Bluetooth Low Energy Applications

In this paper, a low-power low-IF receiver employing a quadrature low-noise amplifier (LNA) is proposed for Bluetooth low energy (BLE) applications. The proposed quadrature LNA, which can provide accurate quadrature signals in the RF path, consists of a common-source amplifier with inductive degeneration and a quadrature generator based on a common-gate amplifier with a single RC network. Therefore, a BLE receiver using the proposed LNA can eliminate quadrature generating circuitry of the LO chain, thereby reducing power consumption. The implemented receiver is composed of the quadrature LNA, single-to-differential double-balanced active mixer, and second-order G<SUB>m-</SUB>C complex filter. Simulated in a 65-nm CMOS process, it achieves a conversion gain, noise figure, and an image rejection ratio of 53.2 dB, 4.81 dB and 38 dB, respectively, and consumes 2.2 mA from a supply voltage of 0.8 V. The die area is 2.24 ㎟.

A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications

In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR) to transfer four data in one clock cycle. In recent graphic memories, QDR is being implemented by a phase-locked loop (PLL). However, it is hard to apply a PLL to main and mobile memories for its high power dissipation and hardware cost. Therefore, we propose a new delay-locked loop-based quadrature clock generator (DLL-QCG) to replace a PLL. A sub-range technique is adopted for a phase interpolator (PI) to achieve a very fine resolution with low power and small area. A tiny resolution mitigates the jitter accumulation effect of the conventional all-digital DLL-QCG and reduces a phase error. With the introduction of the sub-range PI, the delay line structure is changed from two-stage (coarse-fine) to three-stage (coarse-fine-finer). To control this, we also develop a new controller, which ensures clock quality through seamless boundary switching at the fine-to-finer. The circuit is fabricated using a 28 nm CMOS FDSOI technology with a 1 V supply voltage and an area of 0.0072 mm2. It operates from 1.8 to 2.5 GHz and achieves a phase error of 3.35° to 6.35° without a quadrature-phase collector. In addition, the measured RMS and peak-to-peak jitters at operating bandwidth are 1.05 to 1.71 ps and 8.4 to 12 ps, respectively.

A 12.5 Gb/s 1.93 pJ/Bit Optical Receiver Exploiting Silicon Photonic Delay Lines for Clock Phases Generation Replacement

This brief describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by high-speed optical measurements. The receiver achieves an error-free transmission (BER < 10−12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of −4 dBm from a 1 V supply.

A Compact Digitally-Assisted Merged LNA Vector Modulator Using Coupled Resonators for Integrated Beamforming Transceivers

This paper presents a compact differential quadrature generation scheme using transformer coupled resonators for use in scalable fifth-generation (5G) phased-array architectures. A merged low-noise amplifier vector modulator (LNA-VM) architecture is introduced where quadrature generation, conventionally implemented using an explicit quadrature hybrid, is now seamlessly integrated with the load of an LNA gain stage facilitating a compact design. The outputs of a low- $Q$ coupled-resonator load in the LNA is used for quadrature generation, and Cartesian combining is implemented by phase-invariant programmable gain amplifiers (PGAs) with constant input capacitance and output conductance across phase settings—this ensures low rms gain and phase errors. A 25.1–27.6-GHz phased array channel employing the proposed scheme is implemented in 65-nm CMOS. The merged LNA-VM is digitally tunable across 2.5 GHz (25.1–27.6 GHz) and achieves rms gain and phase errors (measured at band edges) better than 0.42 dB (0.64 dB) and 4.5° (6.9°), respectively, for a bandwidth of 500 MHz (700 MHz). It occupies a composite area of only 0.123 mm2 while consuming 30.5 mW from a 1-V supply. To achieve quadrature locking at the desired frequency within the LNA-VM’s tuning range, an on-chip mixer-based quadrature error detection and calibration scheme is presented. The proposed scheme is demonstrated to be robust in the face of gain and layout-induced mismatches which can be significant at millimeter-wave (mm-wave) frequencies.

An S-Band CMOS 6-Bit Vector-Sum Phase Shifter with Low RMS Phase Error Using Frequency-to-Voltage Converter Feedforward Loop

In this paper, a wideband full-360o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2–4[Formula: see text]GHz) applications. The designed phase shifter in 180[Formula: see text]nm CMOS technology achieves an RMS phase error in the range of 0.607–1.18∘ with [Formula: see text][Formula: see text]dBm input signal over 2–4[Formula: see text]GHz frequency band. With lower input signal of [Formula: see text][Formula: see text]dBm, the RMS phase error is 0.621–1.34∘ for 2–4[Formula: see text]GHz input frequency. The proposed phase shifter shows an RMS amplitude error less than 0.41[Formula: see text]dB over 2–4[Formula: see text]GHz frequency. The 1-dB compression point ([Formula: see text]) of the proposed phase shifter is [Formula: see text][Formula: see text]dBm. The proposed wideband phase shifter draws 32 mA from 1.8 supply voltage. It occupies an active area of only 0.025[Formula: see text]mm2, due to active design without any inductor.

Analysis of the operation modes of the quadrature harmonic generator oscillations in the PSIM software environment

Analysis of the operation modes of the quadrature harmonic generator oscillations in the PSIM software environment

A PVT-Tolerant &gt;40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS

Precise generation of quadrature signals over a wide frequency range is a key function for the next-generation 5G communication systems. In this paper, we present a wideband quadrature generator based on a single-stage polyphase filter (PPF). A phase detector senses the phase error from quadrature signals generated by a single-stage PPF, and a feedback circuit continuously tunes the filter center frequency to the input signal frequency by varying the polyphase resistance of an nMOS device in triode. Transformer-based resonant circuits at the input and output of the PPF ensure wide bandwidth and low loss. Prototypes have been realized in a 55-nm CMOS technology. Tailored to the next-generation 5G systems for cross-network interoperability requirements, the measured quadrature generator shows an image rejection ratio IRR > 40 dB over a bandwidth from 28 to 44 GHz. The power consumption is 36 mW for the PPF and buffers, and 3 mW only for the calibration loop. One key aspect of the proposed solution is its robustness over process, voltage and temperature (PVT), one of the weak aspects of alternatives proposed in the literature. This solution compares favorably with the state of the art and shows the largest fractional bandwidth (44%) among the quadrature generators at frequencies greater than 20 GHz, to authors’ knowledge.