Pulse Width Modulation Switching Patterns Research Articles

Advanced Single-Phase Nine-Level Converter for the Integration of Multiterminal DC Supplies

This paper presents a new symmetrical single-phase nine-level dc–ac converter for the applications of distributed generation systems. The proposed multilevel inverter (MLI) utilizes four independent dc sources to generate the nine output voltage levels considering a reduced number of switching devices. The proposed inverter consists of main and auxiliary circuits. The main circuit is a single H-bridge circuit, which is responsible for output voltage polarity. The auxiliary circuit consists of a special combination of switching devices, which are used to synthesize the multilevel output voltage. The merits of the proposed MLI are: increased output voltage levels at reduced number of switching devices, low switching loss, low total harmonic distortion, low dv/dt stress on the switches, and hence, low ratings of the switching devices, and low cost. The effectiveness of the proposed MLI and its pulsewidth modulation switching pattern has been verified experimentally by using a laboratory prototype controlled by DSPACE-1103.

On Stability of Voltage Source Inverters in Weak Grids

As the number of inverters increases in the power grid, the stability of grid-tied inverters becomes an important concern for the power industry. In particular, a weak grid can lead to voltage fluctuations at the inverter terminals and consequently cause inverter instability. In this paper, impacts of circuit and control parameters on the stability of voltage source inverters are studied using a small-signal state-space model in the synchronously rotating $dq$ -frame of reference. The full-order state-space model developed in this paper is directly extracted from the pulsewidth modulation switching pattern and enables the stability analysis of concurrent variations in the three-phase circuit and control parameters. This paper demonstrates that the full-order model of a grid-tied active (P) and reactive (Q) power (PQ)-controlled voltage source inverter (VSI) can be significantly reduced to a second-order model, preserving the overall system stability in the case of grid impedance variations. This paper also shows that a decrease in the grid inductance does not necessarily improve the stability of grid-tied VSIs. The system stability is a function of both the grid R/X ratio and grid inductance. Despite the grid-side inductor of the LCL filter is in series with the grid impedance, they have different impacts on the stability of a grid-tied PQ-controlled VSI, i.e., an increase in the filter inductance may improve the system stability in a weak grid. These findings are verified through simulated and experimentally obtained data.

Common-Mode Voltage Reduction of Three-Level Four-Leg PWM Converter

This paper presents a carrier-based pulsewidth modulation (PWM) method that reduces the common-mode voltage (CMV) of a three-level four-leg converter. Based on an analysis of space vector PWM (SVPWM) and sinusoidal-PWM switching patterns, the fourth-leg pole voltage of a three-phase converter, known as the “f pole voltage,” is manipulated to reduce the CMV. To synthesize the f pole voltage for the suppression of the CMV, positive and negative pole voltage references of the f leg are calculated. In addition, the offset voltage to prevent distortion of the a, b, and c phase voltages regarding the neutral point is deduced. The proposed PWM strategy can be easily implemented in the software of a DSP-based converter control. The three-level four-leg converter with the proposed PWM algorithm results in a remarkable reduction in the peak-to-peak value of the CMV. From the simulation and the experimental results, the peak-to-peak value of the CMV when using the proposed PWM method is 33% compared to that when using the SVPWM method, while the number of CMV transitions during the switching period in the proposed PWM method is only 25% of that when using the SVPWM method.

3레벨 4레그 PWM 컨버터의 커먼 모드 전압 저감

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

FPGA-based PWM for three-phase SEPIC rectifier

This paper presents the design and implementation of synchronous pulse-width modulation (PWM) for a three-phase three-switch Single Ended Primary Inductance Converter (SEPIC). The PWM switching patterns are generated from an Altera Cyclone II field programmable gate array (FPGA) device. Two types of carrier waveforms are used with two 60°sine waveforms, taking less space in the FPGA, providing more space for control circuits. Comparative study of two PWM methods is also shown. Verification of simulation results are based on hardware-in-the-loop technique, to show the effectiveness of digital-based PWM control.

A Discontinuous PWM Method for Balancing the Neutral Point Voltage in Three-Level Inverter-Fed Variable Frequency Drives

The paper describes a new discontinuous carrier-based pulsewidth modulation (PWM) method for use in variable frequency drives (VFD) driven by three-level inverters. The method introduces three different switching patterns for the full range of operating speeds. Depending on the actual operating speed, the proposed algorithm is developed to select the most suitable PWM switching pattern that improves the VFD performance. This results in low imbalance in the DC-link capacitor voltage, and low current distortions without increasing switching losses. Theory, simulation, and experimental results are presented.

Performance of grid connected inverter with maximum power point tracker and power factor control

Detailed analysis, simulation and hardware results of grid connected inverter with maximum power point tracker and power factor control in Malaysian climate are presented. A six-switch topology inverter with symmetrical pulse width modulation (PWM) switching technique is used. A low-pass filter is incorporated in the circuit to filter out unwanted harmonics and produce a sinusoidal AC current. Low total harmonic current distortion at the inverter output can be achieved. The three-phase PWM switching pattern was developed using Xilinx FPGA. The developed system is also capable of adjusting the power factor to unity. A 3 kVA power transformer with a 1:2 ratio is constructed to provide galvanic isolation for better circuit performance and circuit protection. Hardware results for proposed solar photovoltaic inverter configuration interconnected to the grid are also presented. From the experimental results, it is confirmed that the harmonic distortion of the inverter output waveform is within the limits laid down by the utility companies.

PWM optimisation for three-level voltage inverter based on clonal selection algorithm

A clonal selection algorithm (CSA) is first applied to determine the switching time for a three-level voltage pulse width modulation (PWM) inverter. To obtain an optimal PWM switching pattern, CSA should calculate a set of nonlinear transcendental equations with nonlinear equality and inequality constraints. Unlike the general CSA by penalising infeasible solutions, this new CSA deals with constraints and guides the search to the true optimum solution by an infeasibility degree with a random disturbance (IFDD) selection operation. The proposed method minimise the total harmonic distortion and generates a waveform with adjustable amplitude of the fundamental component. Calculation results verify that the proposed method is efficient to obtain the optimal PWM switching pattern and is superior to natural sampling and genetic algorithm-based PWM switching pattern.

A Simple Method for Suppression of Resonance Oscillation in PWM Current Source Converter

This paper deals with a suppression method for the resonance oscillation in the ac side of a pulse-width modulation (PWM) current source converter. The converter is operated with the PWM switching pattern which is generated by the full digital control of computer software. The resonance current, caused by the LC low pass filter at the step change of the pattern, can be effectively suppressed by one pulse control of the pattern. The proposed method does not need to have the feedback loop of the current/voltage and does not offer the switching stress of the devices. The switching timing of the control is determined by pre-calculation of the off-line in consideration of the circuit constants. The experimental and the simulated results in the single-phase and the three-phase PWM converters are given, compared with those without the control, and show good response of the supply current.

Application of the ZVS-PWM commutation cell to a full-bridge DC-DC converter

This paper presents the analysis and design procedures of a new DC-DC full bridge pulse-width modulation (PWM) converter, using the zero voltage switch (ZVS)-PWM commutation cell to achieve soft switching. Experimental results obtained from a laboratory prototype rated 1500 W are also presented. It is demonstrated that the inclusion of the auxiliary switches does not modify the PWM switching pattern. Bench tests on the prototype confirm that the proposed circuit exhibits high efficiency and behaves as a constant voltage source over an extended power output range.

Characterization of induction motors in adjustable-speed drives using a time-stepping coupled finite-element state-space method including experimental validation

This paper describes how a comprehensive time-stepping coupled finite element phase flux linkage-based state-space modeling approach can be used for the characterization of induction motors in adjustable-speed drives. The model implemented the faster indirect and iterative coupling approach based on the curl-curl nondiffusion equation rather than the direct coupling approach, which is based on the curl-curl diffusion equation. The model presented in this paper is capable of rigorously modeling the effects of magnetic nonlinearities and space harmonics due to the machine magnetic circuits' topology and winding layouts, time harmonics resulting from electronic switching of inverters, as well as the synergistic interaction between these time and space harmonics. This includes the presentation of a unique approach for the calculation of electromagnetic torque by means of a concept of energy balance computed from instantaneous magnetic field solutions calculated at each time sample in an at cycle. This approach reveals higher content of torque ripples than given by more conventional approaches to torque calculations. The results of motor drive performance simulations and corresponding test results are shown to correlate well here with current waveforms and torque averages. This includes sinusoidal excitation and six-switch inverter excitation with pulsewidth modulation switching pattern, respectively.

Modulated integral control technique for compensating switch delays and nonideal DC buses in voltage-source inverters

Standard pulsewidth modulation (PWM) techniques assume a ripple-free DC-link voltage at the inverter input terminals and ideal switches. Most techniques proposed in the literature to compensate the nonideal characteristics require additional and complex circuitry. This paper proposes and analyzes a simple method of generating PWM switching patterns which ensures a high-quality output voltage and inherently compensates for a nonideal DC bus and switching delays. The method is based on maintaining a sinusoidal volt-second distribution at the inverter output by sensing the output voltage and generating the gating pattern online. The principles of operation are explained, and a design procedure is presented. Simulation results illustrating the features of the proposed modulator are verified experimentally on a 3 kVA prototype unit.

A new PWM speed control system for high-performance AC motor drives

An approach to speed control for AC motor drives that uses programmed PWM (pulse width modulation) switching patterns over the complete range of output speed is presented. The scheme provides smooth operation during the required switching-pattern changes and guarantees high-quality output voltage and current in the AC motor load, making it most suitable for high-performance, high-efficiency applications. A detailed description of the scheme and its realization is provided. Results of an experimental investigation on a variable-speed induction motor and a permanent-magnet synchronous motor drive system illustrate the advantages of the scheme. >