PTAT Voltage Research Articles

A Sub-1-V 8.5-ppm/°C Sampled Bandgap Voltage Reference

This brief proposes a novel sub-1V discrete-time CMOS bandgap reference circuit where a constant voltage is produced by summation of a CTAT and a PTAT voltage that are sampled onto a capacitor. By sampling the voltages onto a capacitor, we eliminate the need for an opamp in the bandgap core, which tends to be the dominant source of noise and offset concerns in low voltage bandgap designs in scaled technologies. A prototype was designed and fabricated in 28nm TSMC HPC+ technology with a nominal output voltage of 108mV. It demonstrates a temperature coefficient of 8.5ppm/°C between −40°C and 125°C, and occupies an area of 0.0075mm2 while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.6\mu \text{W}$ </tex-math></inline-formula> of power.

A 210 nW NPN-Based Temperature Sensor With an Inaccuracy of ±0.15 °C (3σ) From −15 °C to 85 °C Utilizing Dual-Mode Frontend

This paper describes an NPN-based temperature sensor that achieves a 1-point trimmed inaccuracy of ±0.15 ∘C (3σ) from –15 to 85 ∘C while dissipating only 210 nW. It uses a dual-mode front-end to roughly halve the power consumption of conventional front-ends. First, two NPNs are used to generate a well-defined PTAT bias current, then this current is sampled and applied to the same NPNs to generate well-defined PTAT and CTAT voltages. These voltages are then applied to a low power tracking Σ modulator-based ADC, which employs a digital filter to efficiently generate a multi-bit representation of temperature. A prototype fabricated in a 180-nm BCD process achieves 15 mK resolution in a 50 ms conversion time, which translates into a state-of-the-art resolution FoM of 2.3 pJK2.

A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply

This brief proposes a sub-1V, voltage mode CMOS bandgap reference circuit. Conventionally, sub-1V references are obtained by converting PTAT and CTAT voltages to currents and summing them in the current domain. Such techniques have multiple operating points and cannot natively support applications that require PTAT currents in addition to a bandgap voltage. This brief presents a voltage mode reference circuit, which adds a PTAT voltage with a scaled version of a CTAT voltage all within the sub-1V domain. Compared to current mode bandgaps, summing in voltage domain enables reduction of one CTAT current mirror stage and a significant reduction in PTAT current mirror ratio resulting in a reduced number of error sources. In addition, this circuit also natively supports applications that require PTAT current. A novel, high-accuracy self-biasing technique has been adopted to minimize the systematic offset induced temperature coefficient. A prototype designed in 45nm TSMC CMOS technology for a nominal voltage of 500mV demonstrates 24.4ppm/°C temperature coefficient from -40°C to 125°C, 0.15% line regulation, and draws 7.2μ\textA from a 1.05V supply.

A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-capacitor Bandgap Voltage Reference

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

A 167.18 ppm/°C temperature coefficient, area efficient voltage reference using only MOS transistors

In this paper, design of a voltage reference circuit using only MOS transistors and without employing an operational amplifier is presented. A proportional to absolute temperature [PTAT] voltage and a PTAT current are designed then difference of the PTAT voltage and product of the PTAT current and resistor gives the temperature independent voltage. The advantages of both sub-threshold and strong inversion region operation of MOS transistors are exploited in the design. The voltage reference is implemented using standard CMOS 180 nm technology. The voltage reference provides a voltage of 224.3 mV consuming a quiescent current of 30 ?A at room temperature. Post layout simulation results show that the proposed voltage reference has a temperature coefficient of 167.18 ppm/?C and varies only 3mV when there is a ?10% variation in supply voltage. The circuit occupies an area of only 93.6?32.6?m on the chip, making it suitable for area constraint applications.

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm2. The obtained average reference current is 6 nA having a slope of 5.5pA/°C.

A 0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub-threshold operation

A nano-watt bandgap voltage reference (BGR) is presented. To provide a low-voltage and low-power BGR, the circuit has been biased in the sub-threshold region; thereby, drawing a few nano-amperes current from the source, has been achieved. In order to reduce die area and also power consumption, instead of resistor, transistor is used. To generate PTAT voltage, self-cascode composite structure is used for the transistors. The results from post-layout simulation using 0.18-μm standard CMOS technology show that the proposed BGR circuit generates a reference voltage of 625 mV, obtaining temperature coefficient of 13 ppm/ °C in the temperature range of − 25 °C to 110 °C. The simulated power supply rejection ratio is 42 dB. Fully designed with MOS transistors, the circuit draws 18 nA from a 0.9-V supply. The active area of the proposed BGR is 0.00067 mm2.

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30°C to +70°C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15°C to +0.35°C. Similarly, CTAT generator has mean temperature accuracy of ±1°C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18mV/°C with the temperature inaccuracy of ±1.3°C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5°C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2μW.

A Consideration of Temperature Coefficient on Gate-Voltage-Controlled PTAT Voltage Generator under Ultra Low Power Supply

A way of large temperature coefficient on PTAT voltage generator is proposed. By stacking the proposed circuits, a PTAT voltage generator with large temperature coefficient can be realized. The PTAT voltage generator is analyzed by use of 4-terminal MOSFET model in subthreshold region based on the diffusion current. The temperature coefficient of measured value is compared with that of theoretical value.

LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR

Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 &lt; t &lt; 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 &lt; t &lt; 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

PTAT Voltage Generator under Ultra Low Power Supply with Two Subthreshold MOSFETs between Rails

A proportional to absolute temperature voltage (PTAT Voltage) generator under ultra low power supply with MOSFETs operating in weak inversion region is proposed. The PTAT voltage generator is a necessary circuit for temperature sensor and bandgap reference circuit under low power supply in minimized CMOS analog integrated circuit. When two MOSFETs operating in weak inversion region are connected between rails, the PTAT voltage generator can be driven even under ultra low power supply voltage. As gate terminals are common in two MOSFETs connected in series and also bulk terminals are common, a gate to bulk voltage for MOS diode in a MOSFET is equal to that in another MOSFET. The proposed PTAT voltage generator operating under supply voltage from 0.2V to 1.8V with -70dB PSRR is fabricated with a standard 0.18μ m n-well CMOS technology and measured to investigate the basic principle. The measured characteristics of output voltage versus temperature fit to the theoretical ones deriving from design principle exactly.

Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages

A new curvature-correction technique for improving the temperature behavior of a CMOS voltage reference will be presented. The reducing of the temperature coefficient for the reference voltage will be realized compensating the nonlinear temperature dependence of the gate-source voltage for a MOS transistor working in weak inversion with the difference between two gate-source voltages. These MOS transistors are biased at drain currents with different temperature dependencies (PTAT and PTAT ?, respectively), ? parameter being selected to the optimal value for the implementing technology. The PTAT voltage generator will be designed using an original Offset Voltage Follower block, with the advantage of a reduced silicon occupied area as a result of replacing classical resistors by MOS active devices. SPICE simulation reports TC = 1.95 ppm/K for an extended temperature range, 273 K < T < 363 K, without considering the parameters spread. The circuit is compatible with low-power low-voltage designed, having a maximal power consumption of 0.4 μW for a minimal supply voltage of 1.1 V.

Temperature sensors and voltage references implemented in CMOS technology

This paper reviews the concepts, opportunities and limitations of temperature sensors and voltage references realized in CMOS technology. It is shown that bipolar substrate transis- tors are very suited to be applied to generate the basic and PTAT voltages. Furthermore, it is shown that dynamic element matching and auto-calibration can solve the problems related to mismatching of components and noise. The effects of mechan- ical stress are a major source of inaccuracy. In CMOS technology, the mechanical-stress effects are small, as compared to those in bipolar technology. It is concluded that, with low-cost CMOS tech- nolog, rather accurate voltage references and temperature sensors can be realized.

The temperature characteristics of bipolar transistors fabricated in CMOS technology

This paper presents the results of an experimental investigation of the temperature characteristics of bipolar transistors fabricated in CMOS technology. These results have to be known and understood to enable the design of high-performance temperature sensors and bandgap references in CMOS integrated circuits. The non-idealities of proportional to the absolute temperature voltage ( V PTAT) have been studied, and the results show that we can generate accurate PTAT voltages by optimizing the operating condition and layout of the transistors (error<0.1%). The measurement results of V BE( I C, T) characteristics show that the existing theory for transistors fabricated in bipolar technology is also quite useful for bipolar substrate transistors fabricated in CMOS technology. We found that the temperature sensors and the bandgap references fabricated in CMOS technology might even be better than those fabricated in bipolar technology.

The piezojunction effect in NPN and PNP vertical transistors and its influence on silicon temperature sensors

This paper describes a test structure to characterize the piezojunction effect for the base-emitter voltage V BE and the PTAT voltage Δ V BE. The piezojunction effect directly affects the accuracy of temperature sensors and special types of pressure sensors. Packaging is a source of mechanical stress in electronics circuits. Measurements have been performed for two types of vertical bipolar transistors. Firstly, an NPN transistor of a BiCMOS technology and secondly, a PNP substrate transistor of a CMOS technology, both of them using a [100] silicon wafer geometry. It has been found that the sensitivity for the uniaxial stress of the V BE of the PNP is four times less than that of the NPN transistor. In both cases, the PTAT voltage appears to be hardly stress-sensitive.

A CMOS interface for thermocouples with reference-junction compensation

This paper presents a CMOS interface for a thermocouple, including reference-junction compensation. The interface contains a first-order oscillator whose period is modulated by the signal from the thermocouple (V_x) and two other signals generated internally. One is a base-emitter voltage (V_BE) and the other is a PTAT voltage (V_PTAT). Linear combinations of the periods corresponding to these two voltages are made by a µC, to obtain a reference signal and a temperature-dependent signal. The internal signals are required to provide auto-calibration for offset and gain and to measure the interface internal temperature. Dynamic Element Matching is applied to generate an accurate and reliable PTAT voltage. The inaccuracy in the base-emitter voltage is calibrated using a vertical PNP substrate transistor with multi-emitter areas. The applied modulator used in the circuit has a second-order filtering which suppresses low-frequency (1/f) noise. This filtering property enables the use of a low-cost CMOS process for the implementation of the circuit. The interface is able to measure a voltage (V_x) in the range of −27 mV to 100 mV, the measured accuracy of the system over a temperature range of −25°C to 75°C is 550 ppm of V_x ± 2µV. The inaccuracy in determining the reference-junction temperature is 0.6 K. The measuring time is ≤50 ms.