Pseudo-exhaustive Test Research Articles

Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets

The generation of pseudoexhaustive test sets for the built-in self-test (BIST) of combinational circuits is addressed, using as a test pattern generator a simple linear feedback register (LFSR), structure, known as LFSR/SR. It is shown that particular orderings of the LFSR cells can significantly reduce the test set size. In addition, it is shown that an LFSR/SK designed with a particular cell ordering and the allowance of a marginal number of additional cells guarantees pseudoexhaustive test sets of the minimum size 2/sup w/, where w is the maximum input dependency limit of the circuit under test. Extensive experimentation on benchmark circuits and comparisons with the hardware overhead of other methods indicate the advantage of this approach. >

Design of pseudoexhaustive testable PLA with low overhead

The pseudoexhaustive testing (PET) scheme is an economical approach to testing a large embedded programmable logic array (PLA). The authors propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying this algorithm, both the area overhead and test length are reduced significantly. >

Vector space theoretic analysis of additive cellular automata and its application for pseudoexhaustive test pattern generation

A novel scheme for utilizing the regular structure of three neighborhood additive cellular automata (CAs) for pseudoexhaustive test pattern generation is introduced. The vector space generated by a CA can be decomposed into several cyclic subspaces. A cycle corresponding to an m-dimensional cyclic subspace has been shown to pseudoexhaustively test an n-input circuit (n>or=m). Such a cycle is shown to supply a (m-1) bit exhaustive pattern including the all-zeros (m-1)-tuple. Schemes have been reported specifying how one or more subsets of (m-1) cell positions of an n-cell CA can be identified to generate exhaustive patterns in an m-dimensional cyclic subspace.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Applications of one-dimensional cellular automata and linear feedback shift registers for pseudo-exhaustive testing

Recent studies have shown that cellular automata (CA) can be used in place of linear feedback shift registers (LFSRs). Due to their regular structure and local feedback connections, VLSI layout of CA is easy and results in saving silicon area. Some properties of CAs derived using Rules 90 and 150 in terms of characteristic polynomials are presented. In particular, (a) computation of characteristic polynomials in CA, (b) computation of sequence lengths generated by various CA/LFSRs, and (c) pseudo-exhaustive testing by sequences generated by CA/LFSRs are accomplished. >

Recursive pseudoexhaustive test pattern generation

A recursive technique for generating exhaustive patterns is presented. The method is optimal, i.e., in one experiment it covers exhaustively every block of k adjacent inputs in the first 2/sup k/ vectors. Implementation methods based on characteristic functions of test vectors are provided. They include a parallel pattern generator employing an exclusive-or array, and two serial generators that can be easily adopted in a scan-based built-in self-test environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The pseudoexhaustive test of sequential circuits

The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optimization of test parallelism with limited hardware overhead

The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead.

Partitioning Techniques for Built‐In Self‐Test Design

An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis of pseudo‐exhaustive test generator for Built‐In Self‐Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm may generate a sub‐optimal design which requires more test patterns and/or hardware overhead. In order to generate a globally optimal design, further improvement of two‐phase algorithm can be achieved by expanding the design space for the formation of linear sum so that the number of test signals required for pseudo‐exhaustive testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of our results against those that would be obtained by existing techniques.

Pseudoexhaustive test pattern generator with enhanced fault coverage

A method of pseudoexhaustive test pattern generation is proposed that is suitable above all for circuits using random access scan. Two linear feedback shift registers are used to generate scan addresses and test patterns to be scanned into these addresses. It is shown that the method gives better results than random testing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Linear feedback shift register design using cyclic codes

A design technique is given for linear-feedback shift registers (LFSR) that generate test patterns for pseudoexhaustive testing of networks with restricted output dependency. This technique is based on cyclic code theory. Examples indicate that LFSRs based on cyclic codes are easier to implement and have lower hardware overhead than LFSRs that use other linear codes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Circuits for pseudoexhaustive test pattern generation

Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required. >

Partitioning for pseudo-exhaustive testing is NP-complete

In the letter, two schemes of circuit partitioning for pseudo-exhaustive testing are described. The complexities of both are proved to be NP-complete.

Pseudoexhaustively testable ASM-based designs of digital systems

The concept of pseudoexhaustive testing is combined with that of qualifier preselection to provide easily testable designs of digital systems based on the algorithmic state machine (ASM) method. The highly structured implementations resulting from direct synthesis procedures with modern programmable devices are augmented by the incorporation of a serial shadow state register to provide built-in testability. A basic general test procedure is outlined and some refinements for particular ASMs are discussed. These can be incorporated at little extra cost or loss of generality.

Pseudo-exhaustive testing strategy for large combinational circuits

Pseudo-exhaustive testing strategy for large combinational circuits

Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique

This paper presents a design technique for linear feedback shift registers that generate test patterns for pseudoexhaustive testing. This technique is applicable to any combinational network in which none of the outputs depends on all inputs. It does not rewire the original network inputs during in-circuit test pattern generation. Thus, the possibility of undetected faults on some inputs is eliminated.

Self-Tested Data Flow Logic: A New Approach

The article describes a new approach to the self-testing and testability analysis of the types of logic structure encountered in the data flow paths of computers. The main purpose of the new methodology is to avoid the costs associated with manual or automatic test pattern generation. Instead of relying upon an automated process of scanning through a gatelevel description of the logic, this is an analytical approach applied to a block-level functional description of the logic structure. This approach allows a hybrid test technique to be adopted, based on both random and pseudoexhaustive test styles, and gives fault coverage figures in excess of 99.5 percent. The methodology is suitable only for highly structured and well-partitioned logic designs.

Verification Testing—A Pseudoexhaustive Test Technique

A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.