Pseudo-exhaustive Test Research Articles

Linear dependencies in extended LFSMs

In this paper, the linear dependencies of extended linear finite state machines (LFSMs) used as test pattern generators (TPGs) are examined. The TPG mechanism considered is a shift register whose initial portion is configured as an LFSM. This mechanism (LFSM/SR) can be used for pseudorandom and circuit-specific pseudoexhaustive test pattern generation. A formula is presented that relates the linear dependencies that can occur among the LFSM/SR cells with the characteristic polynomial of the LFSM. Previously, such an easily computable formula had only been established for Type-1 linear feedback shift registers (LFSRs). The generalization allows the fast determination of linear dependencies for any LFSM, including in particular Type-2 LFSRs and cellular automata.

Testing schemes for FIR filter structures

This paper presents a new pseudoexhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed to detect any combinational faults within the basic cell of the functional units occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudoexhaustive patterns to systematically test all FIR filter building blocks.

A timing-driven pseudoexhaustive testing for VLSI circuits

Because of its ability to detect all nonredundant combinational faults, exhaustive testing, which applies all possible input combinations to a circuit, is an attractive test method. However, the test application time for exhaustive testing can be very large. To reduce the test time, pseudoexhaustive testing inserts some bypass storage cells (bscs) so that the dependency of each node is within some predetermined value. Though bsc insertion can reduce the test time, it may increase circuit delay, In this paper, our objective is to reduce the delay penalty of bsc insertion for pseudoexhaustive testing. We first propose a tight delay lower bound algorithm, which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, ne can propose a bsc insertion heuristic that tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.

Cellular automata-based recursive pseudoexhaustive test pattern generator

This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that the first 2/sup k/ vectors cover all adjacent k-bit spaces exhaustively. It requires substantially less hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization.

Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits

This brief introduces a partitioning algorithm, which facilitates pseudoexhaustive testing, to detect and locate faults in digital VLSI circuits. The algorithm is based on an analysis of circuit's primary input cones and fanout (PIFAN) values. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous ISCAS 1985 and 1989 benchmark circuits containing up to 5597 gates. Our results show that the PIFAN algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms.

Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced.

Testing Configurable LUT-Based FPGAs

A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. The whole chip is configured as a group of one-dimensional iterative logic arrays of cells. We assume that in each linear cell array, there is at most one faulty cell, and that multiple faulty CLBs in the same cell can be detected. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The switch stuck-on and stuck-off fault models are adopted for multiplexers. New conditions for C-testability of programmable reconfigurable arrays are also derived. Our idea is to configure the cells so as to make each cell function bijective. This property is helpful for applying pseudoexhaustive test patterns to each cell and propagating errors to the observable outputs. In order to detect all the faults defined, k+2 configurations are required, and the resulting number of test patterns is 2(superscript k). A novel built-in self-test structure is also proposed in this paper. The input patterns can be easily generated with a k-bit counter. The number of configurations for our BIST structures is 2k+4. Our BIST approaches also have the advantage of requiring fewer hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three test sessions are required. However, the maximum number of configurations for diagnosing a faulty CLB is k+4.

Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits

A new test architecture, called TLS (tree-LFSR/SR), generates pseudo-exhaustive test patterns for both combinational and sequential VLSI circuit is presented. Instead of using a single scan chain, the proposed test architecture routes a scan tree driven by the LFSR to generate all possible input patterns for each output cone. The new test architecture is able to take advantages of both signal sharing and signal reuse. The benefits are: the difficulty of test architecture synthesis can be eased by accelerating the searching process of appropriate residues; and the number of XOR gates to satisfy the pseudo-exhaustive test criterion can be reduced. The TLS test scheme mainly contains three phases: backbone generation, tree growing, and XOR-tree generation. Experimental results obtained by simulating combinational and sequential benchmark circuits are very encouraging.

Novel test pattern generators for pseudoexhaustive testing

Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detectable multiple stuck-at faults in the circuit and all detectable combinational faults within individual cones. Test pattern generators based on coding theory principles are not tailored to a specific circuit as they do not utilize any structural information. They usually generate test sets that are several orders of magnitude larger than the minimum size pseudoexhaustive test set required for a specific circuit. In this paper, we describe hardware efficient test pattern generators that employ knowledge of the circuit output cone structures for generating minimal test sets. Using our techniques, we have designed generators that generate minimum size test sets for the ISCAS benchmark circuits.

Bounds on pseudoexhaustive test lengths

Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (cone-independent) and circuit-specific (cone-dependent) bounds on the minimal length of a test required so that each cone in a circuit is exhaustively tested. For any circuit with five or fewer outputs, and where each output has k or fewer inputs, we show that the circuit can always be pseudoexhaustively tested with just 2/sup k/ patterns. We derive a tight upper bound on pseudoexhaustive test length for a given circuit by utilizing the knowledge of the structure of the circuit output cones. Since our circuit-specific bound is sensitive to the ordering of the circuit inputs, we show how the bound can be improved by permuting these inputs.

Transparent random access memory testing for pattern sensitive faults

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design : Chien-in Henry Chen and Joel T. Yuen. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2, 3, 273 (September 1994)

Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design : Chien-in Henry Chen and Joel T. Yuen. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2, 3, 273 (September 1994)

Arithmetic additive generators of pseudo-exhaustive test patterns

Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme (Rajski and Tyszer, 1993) facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.

Graph partitioning applied to the logic testing of combinational circuits

Logical testing of integrated circuits is an indispensable part of their fabrication. Exhaustive testing of a VLSI (very large scale integration) circuit, which can detect all its faults, is impractical due to the complexity of such circuits and the number of input patterns that have to be applied. A circuit with n inputs would require 2 n different input patterns to be exhaustively tested. To overcome this problem when n is larger than about 20, the circuit can be partitioned into subscircuits each with fewer inputs, which can then be tested exhaustively. This procedure, known as the pseudo-exhaustive testing has a better fault coverage than classical methods. In this paper we present a graph partitioning model for the problem of partitioning a combinational VLSI circuit represented by a directed acyclic graph. However, any direct approach to finding an optimal solution to the graph partitioning problem will require an inordinate amount of computation. Therefore, we propose a polynomial complexity algorithm, composed of two phases, which has been tested with benchmark ISCAS circuits.

Avoiding linear dependencies in LFSR test pattern generators

Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudoexhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be controlled by selecting appropriate characteristic polynomials and reordering the LFSR cells. We identify two classes of such polynomials which, by appropriate LFSR cell ordering, guarantee that a large ratio of linear dependencies cannot occur. Experimental results show significant enhancements on the fault coverage for pseudo-random testing and support the theoretical relation between minimization of linear dependencies and effective fault coverage.

A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits

In this paper, we present a circuit partitioning and test pattern generation technique for pseudo-exhaustive built-in self-testing of VLSI circuits. The circuit partitioning process divides a given circuit into a set of subcircuits which can be exhaustively tested, while the test pattern generation process generates reduced exhaustive test patterns for each subcircuit using a linear feedback shift register (LFSR). In conventional approaches, these two problems are considered separately. However, in this paper, both problems are considered and solved in the same phase. A graph theoretic model of VLSI circuits is proposed. Based on this model, a circuit partitioning algorithm using the concept of minimum vertex cut is devised to partition the circuit into a set of exhaustively testable subcircuits with restricted hardware overhead. Each time a subcircuit is generated by the partitioning algorithm, the test pattern generation problem is considered. A new algorithm, based on the subcircuit modification technique, is proposed with the objective of generating reduced exhaustive test patterns of limited length (e.g., /spl les/2/sup 20/) using LFSR's, for each of the subcircuits. This task is embedded in the circuit partitioning process itself, leading to an efficient and well-coordinated solution. Experiments using ISCAS benchmark circuit simulation have been conducted. The results demonstrate that the proposed method is very good. >

Pseudo-exhaustive built-in TPG for sequential circuits

We address the issue of pseudo-exhaustive test pattern generation (TPG) for the built-in self-test (BIST) of sequential circuits. Let d be the sequential depth, and w be the input dependency limit. We use an LFSR/SR Test Pattern Generator and a small additional hardware overhead to automatically generate d/spl middot/2/sup w/ test patterns to test the circuit pseudo exhaustively or, alternatively, pseudo-randomly with less hardware overhead and extremely high fault coverage. Our scheme uses novel retiming algorithms and transforms the circuit to an equivalent (for test purposes) one by scanning a subset of flip-flops for breaking its cyclic structure, bounding the sequential depth, forcing the input dependency limit, balancing the circuit, and maintaining the clock period. We present the first polynomial time algorithm to bound the sequential depth of a circuit by retiming with minimum number of flip-flops and subject to a clock period bound. We also give a retiming-based polynomial time algorithm to balance a circuit by inserting a minimum number of bypass delay cells. Experimental results on the ISCAS'89 benchmarks indicate that our method outperforms a previously proposed approach, which not only does not provide for on-chip test pattern generation but also requires O(q/spl middot/f/spl middot/2/sup w/) test patterns, where q is the total number of primary or pseudo-primary outputs in the circuit and f is the total number of flip-flops.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits

The logical test of integrated VLSI circuits is one of the main phases of their design and fabrication. The pseudo-exhaustive approach for the logical test of integrated circults consists in partitioning the original circuits to be tested into non-overlapping subcircuits with a small, bounded number of subcircuits, which are then exhaustively tested in parallel. In this work, we present an approximate algorithm for the problem of partitioning integrated combinational circuits, based on the tabu search metaheuristic. The proposed algorithm presents several original features, such as: the use of a reduced neighborhood, obtained from moves involving only a subset of boundary nodes; complex moves which entail several resulting moves, although the variations in the cost function are easily computable; a bi-criteria cost function combining the number of subcircuits and the number of cuts, which simultaneously adds a diversification strategy to the search; and the use of a bin-packing heuristic as a post-optimization step. The behavior of the proposed algorithm was evaluated through its application to a set of benchmark circuits. The computational results have been compared with those obtained by the other algorithms in the literature, with significant improvements. The average reduction rates have been of the order of 30% in the number of subcircuits in the partition, and of the order of 40% in the number of cuts.

Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design

Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named three-phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test generator for VLSI BIST design. Previous approaches to the problem of test generation have optimized computational efficiency at the expense of the required hardware overhead, or vice versa. Our design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive test. Based on three-phase cluster partitioning, a design generator named BISTSYN has been developed and implemented to facilitate the BIST design. The input to the design generator is a circuit description at the gate level which is viewed as a netlist. BISTSYN provides the BIST mechanisms as the output. For those conventional circuits which are extremely unsuitable for pseudo-exhaustive test, BISTSYN employs a circuit partitioning tool, named Autonomous, to partition the combinational portion of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. We demonstrate the effectiveness of BISTSYN by applying the method to different examples and practical VLSI designs. The detailed comparisons of our benchmark simulation results against those that would be obtained by existing techniques are also presented. >

A method for pseudo-exhaustive test pattern generation

In order for pseudo-exhaustive test pattern generation to be practical (time requirement less than 2/sup /spl omega//, /spl omega//spl les/20), two conditions must be satisfied: 1). The function of every element in the circuit must be controllable from no more than /spl omega/ inputs, and 2). The overall time to exercise all elements in the circuit must not exceed 2/sup /spl omega//. We address both these requirements by inserting a small number of bypass storage cells in the circuit under test and constructing appropriate Linear Feedback Shift Registers (LFSRs) to serve as built-in test pattern generators. Our method is applicable to both the gate-level and the module-level and achieves low hardware overhead by using a new graph model for the representation of the circuit and a metric quantity that couples requirements 1 and 2 above. >