Pseudo-exhaustive Test Research Articles

Pseudoexhaustive memory testing based on March A type march tests

The relevance of testing of memory devices of modern computing systems is shown. The methods and algorithms for implementing test procedures based on classical March tests are analyzed. Multiple March tests are highlighted to detect complex pattern-sensitive memory faults. To detect them, the necessary condition that test procedures must satisfy to deal complex faults, is substantiated. This condition is in the formation of a pseudo-exhaustive test for a given number of arbitrary memory cells. We study the effectiveness of single and double application of tests like MATS ++, March C– and March A, and also give its analytical estimates for a different number of k ≤ 10 memory cells participating in a malfunction. The applicability of the mathematical model of the combinatorial problem of the coupon collector for describing multiple memory testing is substantiated. The values of the average, minimum, and maximum multiplicity of multiple tests are presented to provide an exhaustive set of binary combinations for a given number of arbitrary memory cells. The validity of analytical estimates is experimentally shown and the high efficiency of the formation of a pseudo-exhaustive coverage by tests of the March A type is confirmed.

VLSI Implementation of Linear Feedback Shift Register (LFSR) based Test Pattern Generator for Pseudo Exhaustive Testing

Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design engineers to implement highly performing and testable digital systems. Linear feedback shift registers (LFSR) are the critical elements in the testing and self testing of contemporary complex electronic systems like processors, Built-in-self-test (BIST) controllers and integrated circuits (ICs) etc. Fundamentally BIST is a Design-for-Testability (DFT) technique meant to configure testing functions physically with the circuit under test (CUT). To enhance the percentage of fault coverage as a part of BIST operations (testing the IC), LFSRs are deployed (as test pattern generator) to generate the test vectors inside logic BIST for testing digital systems. Proposed work is focused upon designing a fast adder based variable length pseudorandom binary sequence pattern generator (PRBSPG) and experimental validations. LFSR possess characteristics of high speed, better encoding efficiency, high fault coverage, low test volume data and low power consumption specially suitable in processing environment where uniform distribution random numbers are required. Verilog HDL is employed for structuring the modular design units while Xilinx ISE tool is deployed for validating the proposed LFSR design work and associated modular units.

Scalable pseudo‐exhaustive methodology for testing and diagnosis in flow‐based microfluidic biochips

Microfluidics is an upcoming field of science that is going to be used widely in many safety-critical applications including healthcare, medical research and defence. Hence, technologies for fault testing and fault diagnosis of these chips are of extreme importance. In this study, the authors propose a scalable pseudo-exhaustive testing and diagnosis methodology for flow-based microfluidic biochips. The proposed approach employs a divide-and-conquer based technique wherein, large architectures are split into smaller sub-architectures and each of these are tested and diagnosed independently.

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.

New Test Pattern Generators for the BIST Pseudo-Exhaustive Testing based on Coding Theory Principles

In this paper, an efficient algorithm to design convolved LFSR/SR (Linear Feedback Shift Register / Shift Register) for the pseudo-exhaustive testing (PET) is presented as far as the lengths of the test set and hardware overhead are concerning. In this algorithm, an efficient search to reduce the constraint in the size of the shift register (SR) segment and makes an efficient search to restrict on the number of feed forward stages into two stages at most and no restriction on the size of the SR segment. The residues are assigned such that minimum hardware overhead is achieved. This search generates several possible solutions for each case, from which the minimal hardware solutions may be chosen. In addition, a new test pattern generator (TPG) for the PET that bridges the gap between convolved LFSR/SR and permuted LFSR/SR is presented. It is considered to be the optimal pseudoexhaustive test pattern generator (PETPG) as far as the lengths of the test set and hardware overhead are concerning. An efficient residue assignment for the inputs of the CUT to reduce the hardware overhead is presented. With small number of permutations in the assigned residues, the chance of obtaining efficient solutions may be increased. The presented generator in this paper is considered the general form of the PETPG. The simple LFSR/SR, the permuted LFSR/SR, and convolved LFSR/SR are considered the special case. The experimental results for all combinational benchmark circuits [1] indicate the superiority of the presented approach with respect to previous published works.

VLSI Circuit Partitioning Using Ant Colony Optimisation to Yield Fault Tolerant Testable Systems

As CMOS technology enters the nanometer regime, digital designs are becoming more susceptible to permanent, transient and delay faults. Due to higher probability of faults, there is a fundamental need for addressing reliability and design for testability (DFT) issues, while designing fault tolerant VLSI systems. In this paper, a simulation framework and optimisation technique are presented to guide partitioning of VLSI circuits in order to develop fault tolerant testable designs. This framework utilises ant colony optimisation (ACO) and a primary input primary output fan in fan out partitioning algorithm to determine the optimal DFT locations. The DFT cells are added at the partition points to apply pseudo-exhaustive test patterns for fault detection. The number of DFT cells to be inserted and its locations are critical as it affects the system reliability and performance. Hence, their selection is crucial in order to optimise system performance and reliability. In the present work, the design constraints of the partitioned circuit considered for optimisation include critical path delay, hardware overhead, reliability and test time. ACO uses the parameters of the circuit obtained after partitioning, to determine the optimal values of circuits maximum primary input cone size (N) and minimum fan-out value (F) to decide on the number of partitions and its locations. Experiments conducted using ISCAS85 benchmark circuits demonstrate that this novel approach significantly outperforms results of the state-of-the-art works. The effectiveness of proposed optimisation technique is verified using hardware implementation of the partitioned system in Virtex-6E field programmable gate array.

BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs

This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distributed RAM mode of the memory block, the TPG based on FSM is designed to provide March C-testing patterns. Besides, the comparator-based output response analyzer (ORA) and the cascaded ORA scan chain are used to locate the faulty CLB and propagate the comparison output in every row. Finally, fault-injection experiment results verify its ability to detect and diagnose multiple faulty CLBs in faulty FPGAs.

A New Testing Method for Hardware Trojan Detection

Abstract This paper presents a partitioning approach to improve the Trojan detection process. The proposed transition probability based method tries to partition combinational circuits for pseudo exhaustive testing. The nodes of digital circuit in which the transition probability is less than predefined threshold mark as the potential point for hardware Trojan insertion. Thus, our objective is new circuit partitioning method to increase the transition probability of the potential points. We propose I-PIFAN partitioning algorithm in which the optimal size of primary input cone (N) and Fan-out (F) values are selected to partition a given combinational circuit. The partitioning method determines the optimal values of N and F to increase the transition probability and minimize 1) the number of test vector, 2) the number of partitions and 3) the critical path delay. This work ensures that all nodes with low transition probability pass the threshold after partitioning. The proposed algorithm reduces the test time of digital combinational circuits and improves Trojan detection quality. The partitioning method is applied to the ISCAS’85 benchmark circuits and the simulation results show the test vectors reduction and improvement of transition probabilities.

Pseudo-Exhaustive Testing

There are many test generation algorithms currently. With continuously increasing of circuit scale, complexities of these algorithms are also increasingly sharply. Simple algorithms based on circuit structure, including exhaustive testing and pesudo-exhaustive testing, and simplicity of generation of test vector are more and more highlighted by scientific researchers and scholars. The dissertation mainly analyzes pseudo-exhaustive testing.

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

This work presents the first case of using the pseudoexhaustive testing (PET) for high-speed high-order (>;32 -bit) adders. It is shown that all single stack-at faults are detected by a pseudoexhaustive test set of 54 K patterns, compared to 264×2 patterns in the past. Also, all transition faults are detected by a pseudoexhaustive test set of 13 M patterns, compared to 264×4 patterns in the past. In addition, with a programmable-delay clock generated from DLL, the adder latency is accurately measured. The proposed technique was validated by an example of a 6.4-GHz domino adder with 181 ps latency in a 90-nm CMOS technology. With the latency measurement, speed binning of high performance CPUs is now possible.

A NEW SINGLE TEST PATTERN GENERATOR FOR PSEUDOEXHAUSTIVE TESTING

In this paper, we present a novel test pattern generator for pseudoexhaustive testing. This generator bridges the gap between convolved LFSR/SR and permuted LFSR/SR. It is considered to be the optimal pseudoexhaustive test pattern generator as far as the lengths of test set and hardware overhead are concerning. We present an efficient search to assign the residues for the inputs of the CUT to increase the chance to get several solutions and reduce the hardware overhead. With small number of permutations in the assigned residues, the chance of obtaining efficient results may be increased. The novel generator is considered the general form of the pseudoexhaustive test pattern generator. The simple LFSR/ SR, the permuted LFSR/SR, and convolved LFSR/SR are considered the special case of the novel generator. The experimental results indicate the superiority of this generator and the efficiency of our approach.

Recursive Pseudo-Exhaustive Two-Pattern Generation

Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> )-adjacent bit pseudo-exhaustive test sets, all 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> binary combinations appear to all adjacent <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -bit groups of inputs. With recursive pseudoexhaustive generation, all ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> )-adjacent bit pseudoexhaustive tests are generated for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> and more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> )-adjacent bit pseudoexhaustive tests for all <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> . To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.

Accumulator-based pseudo-exhaustive two-pattern generation

In this paper, a novel scheme for the generation of pseudo-exhaustive two-pattern tests for combinational modules under test is presented. The proposed scheme utilizes an accumulator with 1's complement adder to generate the patterns in time equal to the theoretical minimum. Since accumulators are commonly found in current, high-speed signal processing VLSI circuits, the presented scheme may prove a practical solution for the pseudo-exhaustive testing of such circuits for delay and stuck-open faults. Comparisons of the proposed scheme with previously proposed schemes for pseudo-exhaustive two-pattern testing reveals that the proposed generator compares favorably with respect to the required hardware overhead.

Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits

This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reduction in the number of test vectors required to detect faults in VLSI circuits. The algorithm is based on the circuit's maximum primary input cone size ( N) and minimum fanout ( F) values to decide the location and number of partitions. Particle swarm optimization (PSO) is used to determine the optimal values of N and F to minimize the number of test vectors, the number of partitions, and the increase in critical path delay due to the added partitions. The proposed algorithm has been applied to the ISCAS’85 benchmark circuits and the results are compared to other partitioning approaches, showing that the PSO partitioning algorithm produces similar results, approximately one-order of magnitude faster.

Maximum sequence test pattern generators with irreducible characteristic polynomials

Abstract Mechanisms that can generate maximum-length sequences (M-sequences) are of particular interest in pseudoexhaustive or pseudorandom built-in Test Pattern Generation (TPG). The characteristic polynomial of these mechanisms is restricted to be chosen among primitive polynomials only, since the latter require only one initialization state (seed). Recently, it was shown that any non-primitive irreducible polynomial can be used as characteristic polynomial to generate an M-sequence in the minimum number of cycles and with hardware overhead bounded by a low constant irrespectively of the number of seeds. In this paper, we describe and analyze the hardware overhead of two alternative schemes for the same purpose. These schemes offer even lower hardware overhead than the original one for a large majority of non-primitive irreducible polynomials of each degree. We also catalog each non-primitive irreducible polynomial of degree 12–22 according to the least costly of these schemes that can be used with it to generate an M-sequence.

Phase Shifter Merging

Phase shifters are used in conjunction with Linear Feedback Shift Registers and Cellular Automata in order to impose sufficient channel separations on the bit sequences produced by their successive cells. The aim is to reduce structural correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive built-in test pattern generation (TPG). In this paper we present a synthesis approach that merges the logic of the original TPG mechanism with that of the required phase shifter network and yields a new compact structure that can offer lower area overhead and improved frequency of operation than the existing approach.

Multiple fault detection and diagnosis techniques for lookup table FPGAs

A novel fault detection and diagnosis technique named the ‘ping-pong’ type approach for field programmable gate arrays (FPGAs) is proposed in the paper. The authors first derive efficient (k+1) test configurations for a single configurable logic block (CLB) which guarantees 100% fault coverage, where k denotes the number of inputs of a lookup table (LUT). Furthermore, the whole CLB array is divided into cell groups and each group contains two cells – the master cell and the slave cell. Since both cells can be used as the test pattern generator (TPG) and the blocks under test (BUTs) at the same time, one test session is required instead of two test sessions for traditional fault detection techniques. The test complexity can then be reduced significantly. The name of the ping-pong type approach comes from the fact that, if the master cell sends a test pattern to the slave cell, the output of the slave cell is forwarded to the input of the master cell as a test pattern. By iterating this process, all cells will receive pseudo-exhaustive test patterns. The output of each cell is read out immediately after one test pattern is applied through the configuration memory readback or implicit scan circuitry. Therefore, multiple fault detection and location can be achieved easily. Since the number of test sessions is less than that for the traditional approaches, significant speedup can be guaranteed. The detection and diagnosis complexity are compared with those of other works.

A counter-based pseudo-exhaustive pattern generator for BIST applications

Built-in self test (BIST) has been accepted as an efficient alternative to external testing, since it provides for both test generation and response verification operations, on chip. Pseudo-exhaustive BIST generators provide 100% fault coverage for detectable combinational faults with much fewer test vectors than exhaustive testing. An (n,k) adjacent bit pseudo-exhaustive test set (PETS) is a set of n-bit vectors in which all 2k binary combinations appear to all adjacent k-bit groups of inputs.In this paper a novel, counter-based pseudo-exhaustive BIST generator is presented, termed pseudo-exhaustive counter (PEC). An n-stage PEC can generate (n,k) adjacent bit PETS for any value of k, k<n. This kind of testing is termed Generic pseudo-exhaustive testing. A Generic pseudo-exhaustive generator can be used to pseudo-exhaustively test more than one module. The PEC scheme is then extended to recursively generate all (n,k) adjacent bit pseudo-exhaustive tests sets for k<=n. This kind of testing is termed progressive pseudo-exhaustive testing in the literature; α progressive pseudo-exhaustive generator can pseudo-exhaustively test more than one modules in parallel.Comparisons of PEC with techniques proposed in the literature that can be used for Generic and Progressive pseudo-exhaustive testing reveal that PEC is more effective in terms of both hardware overhead and time required to complete the test.

LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds

A fully scanned digital circuit can be tested pseudo-exhaustively by first introducing a number of extra bypass storage cells to limit the test-phase input dependency of each test-phase output and then using a Linear Feedback Shift Register (LFSR) to feed the chain of the original scan cells and the extra cells. For the design of the LFSR, the goal is to minimize the pseudo-exhaustive test length with low hardware overhead. If the LFSR uses a primitive characteristic polynomial then it requires only one seed, but the candidate primitive polynomials may all fail to satisfy the target test length. In this paper, we present a methodology that enlarges the list of candidate polynomials, if the prescribed number of seeds is more than one. Experimental results show that the new candidate polynomials are often instrumental in satisfying the given test length and seed restriction.