Proposed Pulse Width Modulation Method Research Articles

A Modified DPWM Method With Minimal Line Current Ripple and Zero-Sequence Circulating Current for Two Parallel Interleaved 2L-VSIs

High-performance comprehensive optimization of line current ripple, zero-sequence circulating current (ZSCC), and switching losses is a challenge for parallel interleaved inverters. This article proposes a modified discontinuous pulse width modulation (PWM) method for two parallel interleaved two-level voltage-source inverters (2L-VSIs), which are regarded as a single 3L-VSI to optimize its vector sequence. The line current ripple is the priority optimization target to guarantee the principle of the nearest three vectors is applied in each subsector. To reduce the ZSCC and switching losses, the vector combinations with smaller changing rate of ZSCC are selected, and the phase-leg carrying the highest current is clamped. The detailed design procedure of 3L-vector sequence and how to distribute to 2L-VSIs are revealed. The quantitative performance comparison between the proposed PWM method and existing ones in terms of line current ripple, ZSCC, and switching losses are made. Experimental results confirm the effectiveness of the proposed method.

Optimized Multi-Carrier PWM Strategy and Topology Review for Multi-Cell Series-Parallel Medium-Voltage Rectifier

Solid-state transformer (SST) acting as a medium-voltage (MV) rectifier is a viable solution to supply low-voltage DC (LVDC) loads directly from the MV ac grid. Different from a classical boost-derived power-factor-correction (PFC) topology, the multicell series-parallel (MCSP) converter steps down and distributes the input ac voltage by multiple switching cells while providing the PFC function. We propose an optimized multicarrier pulsewidth modulation (PWM) strategy to avoid unwanted modes by modified multicarrier waveforms for ensuring frequent parallel connectivity to improve balancing effect while preserving simple current control implementation. Compared with conventional phase-shifted (PS) PWM and other modified multilevel carrier methods, the proposed method has no adverse effect on the input current distortion and optimizes the balancing effect on the capacitor voltages resulting suppressed circulating currents. Effectively reduced current stresses on the switch devices could lead a reduction of conduction loss on the device. Topology discussion, circulating currents, digital implementation, and loss analysis are provided. Finally, the superiority of the proposed PWM method is validated by thermal-based simulation presenting a power loss breakdown and comparing with other PWM methods. A full-scale prototype is developed, and the experimental outcomes verify the remarkable performance of proposed PWM scheme in balanced and even suppressed switch currents with improved system efficiency.

Optimal PWM in Three-Level Inverter for THD Minimization with Quarter Wave Symmetry Relaxed

Background: Previous works on total harmonic distortion (THD) minimization for multilevel inverters (MLI’s) has made a symmetrical approach that imposes Quarter Wave Symmetry (QWS) and Half Wave Symmetry (HWS) with the aim to restrict the computational difficulties to solve the finalized non-linear expressions. Objective: However, QWS constraint can be abolished, which leads to more generalized formulations and multiple solutions corresponding to minimum THD for complete modulation index-range. Methods: A systematic search approach using MATLAB in-build function is adopted to investigate ideal angles of switching related to three-level, three-phase inverter restricted to only HWS as a constraint for two and three (i.e., N= 2 and 3) switching transitions per quarter cycle. Results: On account of the effective minimization of the dominant low-order odd line voltage harmonics, the proposed pulse-width-modulation (PWM) scheme proved its superiority based on minimum THD% performance compared to the previously reported PWM techniques with both HWS and QWS being retained. Conclusion: The simulation, as well as experimental results to confirm the efficacy of the proposed non-symmetrical PWM scheme over the traditional PWM method restricted to QWS and HWS symmetries over the entire modulation-index range with added advantage of general formulation and multiple solutions.

A hybrid reference pulse width modulation technique for binary source multilevel inverter

The article presents a seven-level reduced switch asymmetrical multilevel inverter with two different methods of pulse width modulation (PWM) techniques. Phase disposition (PD) PWM and hybrid variable-frequency phase disposition PWM (HVFPD-PWM) are the two different PWM methods for making the quality of output voltage waveform. In the first method, the unipolar sine reference with triangular carriers is used. In the second method, the hybrid unipolar reference (sinusoidal with trapezoidal) is proposed with variable frequency carriers to generate the switching pulses for asymmetric multilevel inverter (MLI). The main objective of this proposed method is to reduce the total harmonic distortion in the output voltage waveforms. A comprehensive comparison of the proposed HVFPD-PWM and the conventional PD-PWM with asymmetrical seven-level inverter is presented to show the enriched performances of the proposed method. The performance and viability of the suggested PWM are evaluated through simulation and experimental results using an asymmetrical seven-level inverter. The total harmonic distortion for the proposed PWM method (16.95%) is significantly reduced as compared with the conventional PWM method (18.01%) at the modulation index of one.

Improved Modulation Strategy for Singe-Phase Cascaded H-Bridge Multilevel Inverter

In this letter, two new improved pulsewidth modulation (PWM) techniques are proposed for single-phase cascaded H-bridge inverter. Compared with the conventional modulation methods, including phase-shifted PWM (PS-PWM), level-shifted PWM (LS-PWM), discontinuous modulation (D-PWM), only PS-PWM can ensure the output quality and maintain the power balance between each module. That is why it is widely used. However, the switch with PS-PWM always operates in a high-frequency mode, resulting in the high switching losses and low efficiency. In order to solve the problem, two improved cascaded H-bridge multilevel PWM methods are proposed in this letter. With the proposed PWM methods, the power can be evenly distributed among modules, the utilization rate of switching devices is the same, while the switching times are reduced, which improves the system efficiency. Finally, the experimental tests are carried out on a digital-control single-phase cascaded H-bridge seven-level inverter. And the experimental results verify the effectiveness of the proposed solution.

Hybrid PWM Techniques for a DCM-232 Three-Phase Transformerless Inverter with Reduced Leakage Ground Current.

Pulse Width Modulation (PWM) strategies are crucial for controlling DC–AC power converters. In particular, transformerless inverters require specific PWM techniques to improve efficiency and to deal with leakage ground current issues. In this paper, three hybrid PWM methods are proposed for a DCM-232 three-phase topology. These methods are based on the concepts of carrier-based PWM and space vector modulation. Calculations of time intervals for active and null vectors are performed in a conventional way, and the resulting waveforms are compared with a carrier signal. The digital signals obtained are processed using Boolean functions, generating ten signals to control the DCM-232 three-phase inverter. The performance of the three proposed PWM methods is evaluated considering the reduction in leakage ground current and efficiency. The proposed modulation techniques have relevant performances complying with international standards, which make them suitable for transformerless three-phase photovoltaic (PV) inverter markets. To validate the proposed hybrid PWM strategies, numerical simulations and experimental tests were performed.

Common-Mode Voltage Reduction Method for Three-Level Inverter With Unbalanced Neutral-Point Voltage Conditions

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method.

Reliability and Performance Improvement of PUC Converter Using a New Single-Carrier Sensor-Less PWM Method With Pseudo Reference Functions

A new single-carrier sensor-less pulsewidth modulation (PWM) method using suggested pseudo reference functions is proposed for packed U-cell (PUC) converter to improve performance and reliability of the PUC converter. It is composed of one PWM carrier signal and two suggested pseudo reference functions. By employing the proposed modulation method, the PUC dc capacitor voltage ripple is substantially decreased, and faster sensor-less capacitor voltage balancing is obtained. Moreover, the power losses are evenly distributed among all power switches. Consequently, notable reduction of the PUC dc capacitor voltage ripple and even distribution of the power loss among switches enhance the PUC converter's reliability and lifetime. In addition, odd multiples of the switching harmonic clusters are eliminated from the output voltage; thus, the values of output passive filter components are halved. Hence, applying the proposed single-carrier sensor-less PWM method remarkably improves the performance, power density, reliability, and lifetime of the PUC converter and notably simplifies implementation of the switching pattern. Provided experimental results and comparisons as well as reliability analysis verify the viability and effectiveness of the proposed PWM method.

Sinusoidal Harmonic Voltage Injection PWM Method for Vienna Rectifier With an LCL Filter

This article proposes a harmonic voltage injection pulsewidth modulation (PWM) method for a Vienna rectifier with an LCL filter. Existing PWM methods for Vienna rectifiers with full power factor can lead to resonance problems. It generates current oscillation at the resonant frequency. It is analyzed that why the resonance problem occurs in Vienna rectifier with the existing PWM methods. To solve these resonance problems, the proposed method injects a sinusoidal harmonic voltage into the sinusoidal reference voltage. The magnitude and phase of the injection voltage are determined by the power factor of the rectifier-side. Compared to other PWM methods, the proposed PWM method eliminates the possibility of resonant problems. Considering the operation characteristics of the proposed PWM method, this article suggests a design process for an LCL filter. The effectiveness and performance of the proposed PWM method and the design process for an LCL filter are verified by simulation and experiment.

Analysis of Current Flowing Through Disabled Converters in Parallel AC/DC Power Conversion System

When not all the converters are enabled in a parallel ac/dc power conversion system, some current flows through the disabled converters. This current not only distorts the current waveform of the ac side but also causes extra loss and unintended power flow from the ac to the dc side. In this article, the reason for this current flow is identified, and the total current according to the number of paralleled converters and its operating conditions are analyzed. A new pulsewidth modulation (PWM) method is proposed to minimize the current. And, the zero-sequence voltage and the consequent current flowing through the disabled converters under the proposed PWM method are compared to those under the conventional PWM methods. As a result, it was identified that discontinuous space vector PWM (DPWM) is not a proper PWM method because it causes a large current at some operating conditions. According to both simulation and experimental results, the magnitude of the current flows through disabled converters under the proposed PWM was about 40% less than that under sine PWM and DPWM, and it was about 10% less than that under continuous space vector PWM.

Carrier-Based Discontinuous PWM Method for Five-Leg Inverter

This paper proposes a rotation carrier-based discontinuous pulse width modulation (CB-DPWM) method for the five-leg inverter (FLI). The FLI based on two-level topology consists of 10 switching devices for driving dual motors. Therefore, two switching devices can be reduced to compare the configuration using two three-leg inverters for driving dual motors. The proposed pulse width modulation (PWM) method is based on the reference signals which are used in existing carrier-based continuous pulse width modulation (CB-CPWM) method for FLI. In the proposed rotation CB-DPWM method, one of five-leg is periodically clamped to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /2 or - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> /2 by adding the offset voltage to the reference voltages of the existing CB-CPWM method. The five reference voltages for all legs are considered to calculate the offset voltage of the proposed rotation CB-DPWM method. Consequently, since the proposed rotation CB-DPWM method has less switching than the existing CB-CPWM, the switching loss can be reduced and it results in the efficiency improvement. Simulation and experimental results confirm the effectiveness and feasibility of the proposed method.

Direct Torque Control Techniques of Three-Level H-Bridge Inverter Fed Induction Motor for Torque Ripple Reduction at Low Speed Operations

In this article, two constant switching frequency direct torque control (CSF-DTC) techniques are proposed for H-bridge three-level inverter (HB-TLI) fed induction motor (IM) for reducing torque ripple at low-speed operation. Both the methods use modulators and characteristics of the pulsewidth modulation (PWM) mainly determine the motor drive performance. The first method uses two level-shifted carriers signals, whereas the second method uses carrier signals with appropriate offset voltages. Detailed analytical expressions describing complete harmonic characteristics of HB-TLI are also presented using double Fourier integral approach. Superior harmonic performance is obtained with the proposed PWM methods compared to the existing ones. Drawback of one of the envisaged CSF-DTC techniques entering into overmodulation is rectified at higher motor speeds and a smooth slide-over using zero offset voltage to carrier signals is recommended to overcome the issue. The proposed CSF-DTC techniques are simulated and experimentally validated. The dynamic and steady-state torque performance obtained with the proposed CSF-DTC techniques for IM are compared with the existing DTC methods, which show a significant reduction in the steady-state torque and current ripple, whereas the torque dynamic performance is almost preserved thus, demonstrating its usefulness especially at lower motor speeds.

High dynamic range pseudo–two‐level digital pulse‐width modulation for power‐efficient RF transmitters

SummaryRadio frequency (RF) power amplification based on pulse‐width modulation (PWM) has been widely discussed as a potential solution to achieve higher efficiency in RF transmitters. A digitally implemented PWM introduces a large amount of in‐band distortion due to spectral aliasing. In this paper, a novel memoryless PWM modulator with a built‐in anti‐aliasing filter is proposed that effectively reduces the in‐band distortion in digital implementation. The spectral characteristics of the proposed PWM modulator as well as the statistical properties of its output PWM signal are analytically studied. The pseudo–two‐level output of the proposed modulator provides the capability to compromise between the efficiency, linearity, and complexity of transmitter, based on the given design targets. The proposed PWM method benefits from a simple circuit implementation in both digital and RF sections of the transmitter. Moreover, it preserves the low distortion property at low oversampling ratios of digital baseband. Simulations, as well as measurements, verify the performance of the proposed method.

A simplified hybrid carrier‐based PWM technique for three‐level NPC inverters considering neutral‐point voltage balance

An in‐depth analysis and comparison between the virtual space vector pulse width modulation (VSVPWM) method and the space vector pulse width modulation (SVPWM) method is presented in this paper. Compared to SVPWM, VSVPWM can achieve the balance of the neutral‐point voltage for any load over the full range of the inverter output voltage and for all load power factors. Nevertheless, VSVPWM would cause higher dv/dt of output voltages, higher voltage total harmonic distortion, and slower voltage‐balancing dynamic. A detailed analysis on these drawbacks is given. Then, the relationship between the neutral‐point current and the factor k0, which is employed to adjust the ratio of time of application of small vectors in a pair, is studied comprehensively, and a modified zero‐sequence voltage injection method for the two‐level inverter is introduced into the small hexagons of the three‐level space vector diagram. A simplified hybrid carrier‐based pulse width modulation (PWM) method is developed. Compared to VSVPWM, the proposed PWM method is not only easy to implement voltage‐balancing control but also reduces the switching frequencies of the devices and achieves better output voltage spectra and faster voltage‐balancing dynamic. All these benefits of the proposed method are verified through experimentation. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

Common-Mode Voltage Reduction for Paralleled Inverters

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters’ phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors’ sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise.

An Efficient Four-State Zero Common-Mode Voltage PWM Scheme With Reduced Current Distortion for a Three-Level Inverter

In this paper, a new carrier-based pulse width modulation (PWM) strategy providing common-mode voltage (CMV) elimination and reduced current ripple in a three-level neutral-point-clamped inverter is introduced. The employed switching sequences are made up of the three zero CMV (ZCMV) vectors, and one among the three vec-tors is applied at two ends of a half-carrier cycle. The output current ripple characteristics pertaining to those switching sequences are investigated. In a carrier cycle, the root-mean-square current ripple minimization is analyzed and an optimal sequence is derived accordingly. The presented PWM scheme results in a considerably reduced current harmonic distortion in a wide modulation region as compared to the two existing ZCMV schemes on the same average switching frequency. Also, an implementation of sawtooth-carrier-based PWM patterns is proposed for further improvement of the harmonic performance. The algorithm requires small computational burden and is straightforward for an online implementation. Simulation and experimental results are both provided to validate the good performance of the proposed PWM method.

Torque ripple reduction PWMs for a single DC source powered dual‐inverter fed open‐end winding induction motor drive

Two new pulse width modulation (PWM) methods are proposed for a dual two-level inverter (DTLI) fed open-end winding induction motor drive for complete elimination of zero sequence voltage (ZSV), enabling the DTLI drive to be powered from a single DC power supply only. One of the PWM methods is carefully devised and uses a single inverter only to be switched at all instants of time and dwell times of that switching inverter are derived by applying a simple volt-second balance principle, for ZSV elimination. The second PWM method involves switching of both the inverters, for ZSV elimination in the DTLI. While the dwell times of first inverter are derived using the concept of ‘effective-time’, whereas dwell times of the second inverter are obtained by thoughtfully exploiting the notion of ‘phase-shift’. Additionally, torque ripple performance of the open-end winding induction motor is theoretically analysed; ripple content is quantified to compare the performance of the proposed PWM methods. Finally, a typical PWM variant that results in the least torque ripple in the induction motor is recommended. All the envisaged ZSV elimination PWM methods and its variants are simple to implement and are first analysed, simulated and experimentally verified.

Analysis and Compensation of Inverter Nonlinearity for Three-Level T-Type Inverters

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well.

A Novel Pulse-Width Modulation Method for Reactive Power Generation on a CoolMOS- and SiC-Diode-Based Transformerless Inverter

For efficiency considerations in the photovoltaic (PV) power generation, high-efficiency CoolMOS- and SiC-diode-based transformerless inverters have been proposed and studied in the previous literatures, but the reactive power generation capability to meet the upcoming standards has never been discussed. By reviewing the high efficiency converters with CoolMOS and SiC-diodes, this paper improves a previous transformerless inverter circuit and presents related operating modes for reactive power generation. A novel pulse-width modulation (PWM) method for this improved inverter topology is then proposed for reactive power generation. The ground-loop voltage of this inverter under the proposed PWM method is also derived with common mode (CM) and differential mode (DM) circuit analyses, which indicate that high-frequency voltage components can be minimized with symmetrical design of inductors. A 250-W inverter hardware prototype has been designed and fabricated. Steady-state and transient operating conditions are tested to demonstrate the validity of the improved inverter and proposed PWM method for reactive power generation, and the high-frequency-free ground loop voltage.

Common-Mode Voltage Reduction of Three-Level Four-Leg PWM Converter

This paper presents a carrier-based pulsewidth modulation (PWM) method that reduces the common-mode voltage (CMV) of a three-level four-leg converter. Based on an analysis of space vector PWM (SVPWM) and sinusoidal-PWM switching patterns, the fourth-leg pole voltage of a three-phase converter, known as the “f pole voltage,” is manipulated to reduce the CMV. To synthesize the f pole voltage for the suppression of the CMV, positive and negative pole voltage references of the f leg are calculated. In addition, the offset voltage to prevent distortion of the a, b, and c phase voltages regarding the neutral point is deduced. The proposed PWM strategy can be easily implemented in the software of a DSP-based converter control. The three-level four-leg converter with the proposed PWM algorithm results in a remarkable reduction in the peak-to-peak value of the CMV. From the simulation and the experimental results, the peak-to-peak value of the CMV when using the proposed PWM method is 33% compared to that when using the SVPWM method, while the number of CMV transitions during the switching period in the proposed PWM method is only 25% of that when using the SVPWM method.