Proposed Gate Driver Research Articles

2.4: Integrated Gate Driver Circuit Technology with IGZO TFT for AMOLED Displays of Simultaneous Emission Driving Method

In this paper, we propose a new integrated gate driver circuit for a simultaneous emission (SE) driving method using IGZO TFT. Simulation results indicate that the proposed gate driver prevents the output waveforms the effect of positive and negative biases, and VTH variations of IGZO TFTs. Furthermore, the proposed circuit is suitable for AMOLED displays with the SE driving method.

A gate driver circuit with the two-stage pre-charge structure for in-cell touch panels

Due to the charge leakage during the touch sensing period and the threshold voltage shift of the driving thin-film transistors (TFTs), the conventional gate driver circuits suffer from poor stability for in-cell touch displays with an increased touch reporting rate. This paper shows a new gate driver circuit, consisting of a two-stage pre-charge structure, which can reduce the charge leakage during the touch sensing period and suppress the threshold voltage shift of the driving TFTs. Simulation results demonstrate that, the rising and falling time differences between adjacent stages are 9.3% and 1.6% for the conventional and the proposed gate driver circuit, respectively. In the case that the threshold voltage of key TFT shifts by +10 V, the rising and falling time degradation ratios are 120% and 2.4% for the conventional and the proposed gate driver circuit, respectively. Therefore, the proposed gate driver circuit is stable for in-cell touch panels with a high touch reporting rate.

15‐3: Hydrogenated Amorphous Silicon Gate Driver on Array with Time‐Division Driving Method for In‐Cell Touch Liquid‐Crystal Display

In this paper, a new gate driver circuit architecture for a hydrogenated amorphous silicon thin film transistor (a‐Si:H TFT) is proposed for the touch sensing stage and the normal stage of gate driver. The circuit operates with the time‐division driving method which integrates between normal display driving and touch interval to reduce the crosstalk between the touch signals and outputs of gate driver. This new gate driver circuit can transmit undistorted signals after a long period of touch sensing and the simple circuit structure could fit narrow bezel TFT‐LCD application by reducing the number of TFTs significantly. Moreover, the proposed gate driver could also slow down the degradation of driving TFTs by inserting the duplicated stage for touching. The results of 25 °C simulation, 85 °C simulation, −40 °C simulation will be discussed. Finally, the measurement results show that the proposed gate driver could suspend about 1000μs touch interval without output distortion for the gate driver and the performance could fit the in‐cell touch screen application.

P‐15: Student Poster: Reliable Gate Driver for Real‐Time External Compensated AMOLED Display Using InGaZnO TFTs

The a‐IGZO TFTs integrated gate driver circuit with inter‐frame memory module and isolated bootstrapping node structure is proposed for AMOLED display. The driver can provide progressive display signal, inter‐frame detection signal and standby detection signal. Compared with conventional ones, the proposed inter‐frame memory shows enhanced driving ability due to the introduce of voltage bootstrapping function. Besides, the proposed gate driver can tolerate larger threshold voltage variations (ΔVth) than the conventional circuit due to the isolated bootstrap node structure.

A Novel Single-Gate Driver Circuit for SiC+Si Hybrid Switch With Variable Triggering Pattern

Hybrid switches are attracting increasing attention recently, due to their high efficiency and low cost. Normally, two separated gate drivers and driving signals are needed for the hybrid switch, which leads to more cost and more control complexity. A novel gate driver circuit for SiC+Si hybrid switches is proposed using single driving signal and single-gate driver in this article. Two simple resistance-capacitance (RC) delay circuits are used for generating different time-delays required by two different triggering patterns to provide more flexibility. The detailed operation principles, mathematical analysis, and the guidance for the selection of key components of the proposed circuit are provided. The merits of the proposed driver are: first, simple structure; second, low control complexity; third, more flexibility; and fourth, low cost. A 2-kW Silicon Carbide (SiC)-MOSFET+Si-insulated gate bipolar transistor (IGBT) hybrid switch buck converter is built to validate the proposed gate driver circuit. The analysis and experimental results match very well, which shows the effectiveness and merits of the proposed method.

A compact gate driver with bifunctional capacitor for in‐cell touch mobile display

AbstractA thin‐film transistors (TFTs) integrated gate driver circuit with bifunctional capacitors for in‐cell touch with horizontal blanking display mode is proposed in this paper. The coupling capacitor, which conventionally enables low‐level‐maintaining parts in display periods, is reused to store transfer charges during touch detection periods. Consequently, only nine TFTs and two capacitors are used for a single stage of the proposed gate driver for in‐cell touch display. Furthermore, the bifunctional capacitor scheme not only avoids the driving TFT from long‐time voltage stress but also suppresses the transfer charges leakage effectively. Therefore, the variation ratios of rising/falling time between adjacent gate driver stages are suppressed within 6%. For a 5.7‐in. display with HD+ resolution, the layout of a single gate driver stage is 623 μm (width) × 171 μm (height). The proposed gate driver circuit has been prepared with the state‐of‐the‐art hydrogenated amorphous silicon (a‐Si:H) TFT manufacturing process. The measured results verified the circuit functions. The gate driver output waveforms are well maintained and being almost independent of touch detection time interval from 100 to 300 μs.

Gate Driver for Wide-Bandgap Power Semiconductors With Small Negative Spike and Switching Ringing in Zero-Voltage Switching Circuit

Because SiC MOSFET-based zero-voltage switching (ZVS) power converter circuits provide high-speed switching, high power density and high efficiency can be achieved. However, an undesired negative spike is formed at the gate-source voltage owing to the crosstalk phenomenon in leg structures, such as half-bridge switch configurations, during high-speed switching. Additionally, ringing voltage occurs owing to resonance between the snubber capacitor and the common source inductance of the SiC MOSFET. Because SiC MOSFETs have a lower gate voltage rating than conventional Si devices, it is essential to reduce the negative spike and ringing voltages to ensure reliability. In this paper, the gate driver circuit is proposed for reducing the negative spike and ringing voltages of the gate-source in ZVS circuits. Because the proposed gate driver circuit provides an effective impedance path for each section through an active switch, a stable driving voltage range of the gate-source can be achieved. To verify the proposed gate driver circuit, an accurate simulation model of the 3-pin SiC MOSFET package is proposed, and the validity of the proposed model is verified through comparison of the simulated waveforms with experimental waveforms. The performance of the proposed gate driver circuit is verified through PSpice simulation.

A Closed-Loop Current Source Gate Driver With Active Gate Current Control for Dynamic Voltage Balancing in Series-Connected GaN HEMTs

The voltage rating of commercial Gallium Nitride (GaN) power semiconductors is limited to 600/650 V because of the lateral structure. Stacking low-voltage switches is an effective way to block higher dc-link voltage. However, unbalanced voltage sharing can occur even with well-matched gate drivers and semiconductors due to the device-to-ground displacement currents. As a result, the low-voltage switches may suffer from over-voltage breakdown. This study presents a novel closed-loop current source gate driver to address the unbalanced dynamic voltage sharing issue. Additional compensation current is actively injected into the switch gate to counteract the voltage imbalance brought by the device-to-ground displacement currents. Compared with the conventional voltage source gate driver-based active gate control method, the proposed current source gate driver tunes the switch turn-off timing and dv/dt more accurately because the switch gate current is directly regulated. Meanwhile, since both the pulse width and amplitude of the compensation gate current can be adjusted, the proposed active gate control is more flexible for adapting to different operating conditions. Moreover, without employing snubber circuits or extra Miller capacitors, the switching speed and switching energy of the GaN devices are not compromised. By implementing the proposed gate driver and voltage balancing schemes, well-balanced voltage sharing can be obtained for both soft-switching and hard-switching scenarios. A series-connected GaN-based multiple pulse tester (MPT) is built to prove the effectiveness of the proposed approach under different load and different switching speed (dv/dt) conditions.

A novel gate driver for Si/SiC hybrid switch for multi‐objective optimization

A novel gate driver with simple functional and structural integration is proposed here, which splits the input gate signal and outputs two separate signals with a dedicated delay time to drive the two constitutional switches, aiming at the cost-effectiveness and power loss reduction of the Si/SiC hybrid switch. The dependency of the hybrid switch's thermal and efficiency performance on the parameters of the gate driver are theoretically and experimentally investigated in a 9 kW 20 kHz Si/SiC hybrid switch based boost converter. A novel load current dependent gate control strategy is proposed to be implemented in the proposed gate driver to achieve the high conversion efficiency under light to medium load condition and balanced junction temperature between the two internal devices under heavy load conditions. The experimental results based on a 20 kHz boost converter show that the Si/SiC hybrid switch with the novel gate driver and optimal current dependent control strategy offers a 163% and 10% rise in power handling capability, respectively, compared to that using the all-IGBT device and all-SiC MOSFET device, and yet a considerably lower device cost.

25‐3: Fault‐Tolerant Integrated Gate Driver for Flexible Displays

This paper proposes a fault‐tolerant integrated gate driver for flexible displays. To achieve fault‐tolerance, decoder‐type gate driver circuit is chosen. Fault detection circuit and redundant circuits are also added. The function of the proposed circuit is verified by simulation and fabrication results. The measurement results of the proposed gate driver with 16 stages on PI substrate comprising a‐IGZO TFT is presented.

High‐reliability gate driver on array using noise sharing of precharging node for thin film transistor–liquid crystal display application

AbstractA hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with negative bias stress on precharging node for noise sharing with high‐reliability 10.7‐in. automotive display has been proposed. The proposed circuit is composed of precharging block, pull‐up and pull‐down block, and noise‐free block. The precharging block not only starts up the gate driver but also reduces noise with 33% duty cycle. Duplicate output signals are responsible for turning on next stage to decrease the loading of output of gate line. Moreover, negative bias voltage recovering of TFTs could be created by setting another lower voltage source to lower the threshold voltage degradation of TFTs. According to lifetime test results, the proposed gate driver of 708 stages passes the extreme temperature range test (90°C and −40°C) for simulation and −40°C for measurement and remains stable over 800 h at 90°C test. Finally, this design is successfully demonstrated in a 10.7‐in. HD (1280 × RGB × 720) TFT‐LCD panel.

Self-Driven Gate Driver for LLC Synchronous Rectification

This letter proposes a self-driven gate driver solely composed of passive components for synchronous rectification (SR). It utilizes the energy of the converter itself, automatically considers component tolerances and temperature variations of critical design parameters, and tunes the SRs on-time. Furthermore, no microcontroller, auxiliary power supply, or current-sensing/voltage-sensing components is required. A great amount of cost is therefore saved. The proposed gate driver is preferable to be used to some resonant converters operating as dc transformers. This letter presents its practical implementation in an LLC resonant converter. Experimental results illustrate that the body diodes' conduction and reverse recovery are eliminated.

A Quasi-Multilevel Gate Driver for Fast Switching and Crosstalk Suppression of SiC Devices

The crosstalk phenomenon in a phase-leg configuration forbids the operation of SiC devices at high switching speed. A multilevel gate driver (MGD) is well-known for crosstalk mitigation, however, it requires two driver ICs and two voltage supplies to generate four different levels in the gate-source waveform. This paper presents a low-cost quasi-multilevel gate driver (QMGD) for crosstalk suppression which can be implemented on a single driver IC using only positive supply voltage. With a simple auxiliary circuit of the parallel-connected transistor, zener diode, and a capacitor, the proposed driver can generate multilevel output. The auxiliary transistor governs the charging and discharging of the capacitor, controlling voltage at the source terminal of SiC MOSFET and thus generating different voltage levels essential for crosstalk suppression. Performance of the proposed gate driver is validated through Spice based simulation as well as experimental tests conducted with Cree C2M0025120D. It is concluded that the proposed QMGD can replace a complicated MGD without any loss of performance.

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement- and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the $\text{V}_{\mathrm{ OUT}}$ ripple voltage because the threshold voltage ( $\text{V}_{\mathrm{ TH}}$ ) of the pull-down units is compensated regardless of the a-IGZO TFT operation characteristics (enhancement mode: positive value of $\text{V}_{\mathrm{ TH}}$ , depletion mode: negative value of $\text{V}_{\mathrm{ TH}}$ ). Many groups proposed the $\text{V}_{\mathrm{ TH}}$ compensation method for pull-down TFTs in the gate driver circuit using a diode connection structure. However, the diode connection structure to extract the $\text{V}_{\mathrm{ TH}}$ value cannot be applied in the depletion-mode oxide TFTs because TFT enters the turn-on state even when the $\text{V}_{\mathrm{ GS}}$ value is 0 V. To solve this problem, we adopted the $\text{V}_{\mathrm{ TH}}$ extraction period only once in one frame time. As a result, our circuit can compensate for $\text{V}_{\mathrm{ TH}}$ of the pull-down unit in the enhancement mode and can be normally operated in the depletion mode. Adjunctively, two low signals (VGL1 and VGL2) and QC node were designed to prevent the leakage current path for Q and $\text{V}_{\mathrm{ OUT}}$ nodes. To verify the threshold voltage tolerance for various stress conditions, we demonstrated the reliability of the circuit according to the threshold voltage change of the TFTs. The simulation result shows that all the $\text{V}_{\mathrm{ OUT}}$ waveforms are maintained at +28 V (VGH) under the $\text{V}_{\mathrm{ TH}}$ shift conditions from −7 V to +11 V; further, the rising time and falling time are less than $0.62~{\mu }\text{s}$ and $0.96~{\mu }\text{s}$ , respectively. Based on a 120-Hz ultra-high definition (UHD) graphics ( $3840{\times }2160$ ) display panel, the proposed circuit has uniform $\text{V}_{\mathrm{ OUT}}$ characteristics compared to previous $\text{V}_{\mathrm{ TH}}$ compensation circuit when $\Delta \text{V}_{\mathrm{ TH}}$ changes from −3 V to +11 V. When $\Delta \text{V}_{\mathrm{ TH}}$ changes from −4 V to −7 V, there is also no circuit malfunction, even with slight increase in the falling time and power consumption.

A Multilevel Gate Driver of SiC mosfets for Mitigating Coupling Noise in Bridge-Leg Converter

Silicon carbide (SiC) devices can significantly increase power efficiency, temperature reliability, power capacity, and power density because of their outstanding characteristics. Nevertheless, in the bridge-leg configuration of a power converter, the high-speed switching capability of SiC mosfet s is often restricted by the coupling noise between high-side mosfet and low-side mosfet . The coupling noise caused by high ${dv/dt}$ and ${di/dt}$ in switching transient will increase the switching loss and the risk of mosfet breakdown. In order to completely take advantage of the superior feature of SiC mosfet s, a novel multilevel gate driver is proposed in this article to mitigate the coupling noise effectively. Compared to the conventional gate drivers, the proposed gate driver adds a capacitor, an auxiliary mosfet , a Zener diode, and two resistors to regulate the turn- off voltage bias felicitously. In this article, the operation principle of the proposed gate driver is first introduced, to the best of our knowledge. Moreover, to obtain the circuit parameters accurately, a series of formulas have also been derived by equivalent circuit models. A 230-V/4.6-A synchronous buck converter based on SiC mosfet s is successfully experimented to verify this proposed gate driver.

A Single Voltage-Balancing Gate Driver Combined With Limiting Snubber Circuits for Series-Connected SiC MOSFETs

Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are required to be connected in series to meet the high-voltage requirement since the blocking voltage of a single device is limited. In order to solve the voltage unbalancing problem in such a series-connection application, a single voltage-balancing gate driver combined with limiting Snubber circuits is proposed in this article. This gate driver only requires one standard driver circuit to drive two series-connected SiC MOSFETs by adding simple coupling circuits, and limiting Snubber circuits are applied for voltage balancing, and thus, low-cost, simple structure and high reliability are acquired. The analysis is given to demonstrate the working process of such a circuit structure, and the key parameters’ design and setting are focused on. In the LTspice simulation of two SiC MOSFETs in series, the proposed gate driver shows good voltage balancing performance as the power loop current increasing. Besides, the branch of series-connected SiC MOSFETs is in reliable ON- or OFF-state during steady process. Finally, the experimental results further verify the performance of proposed single voltage-balancing gate driver.

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

AbstractIn this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (VGS) value for pull‐down units. The results showed all the VOUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable VOUT voltage when the threshold voltage for all TFTs was changed from −6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved VOUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.

A metal oxide TFT gate driver with a single negative power source employing a boosting module

This paper presents a new gate driver integrated by In-Zn-O thin-film transistors (IZO TFTs) with the etch stop layer (ESL) structure, in which only a single negative power source is used on account of a new boosting module. The boosting module is controlled only by the VIN signal for generating a lower level than VSS. The proposed gate driver with 15 stages is fabricated through the IZO TFT process on a glass substrate to verify its function. The experiment results showed that the proposed gate driver can successfully output full-swing waveforms with resistive load RL=2 kΩ and capacitive load CL=30 pF at the 16.7 and 66.7 kHz clock frequencies, and can also output as small as 3.2 μs pulse width with little distortion, revealing good stability.

Smart Self-Driving Multilevel Gate Driver for Fast Switching and Crosstalk Suppression of SiC MOSFETs

Wide-bandgap devices, such as silicon carbide and gallium nitride, have high switching speed potential. However, the actual speed in practical application is limited by circuit parasitics and interaction between high-side switch and lowside switch in a phase-leg configuration, known as crosstalk effect. This article proposes an isolated voltage source gate driver with crosstalk suppression capability to take full advantage of the inherent high switching speed ability of silicon-carbide devices. By applying variable gate voltage through the auxiliary circuit, the crosstalk problem can be mitigated. Using the original gate-source voltage as auxiliary circuit driving signal, the gate driver does not introduce any extra control signals, which avoids additional signal/power isolations and makes the auxiliary circuit very convenient to be implemented on the existing commercial gate driver. The auxiliary circuit makes the gate voltage rise from 0 V other than -5 V when the switch turns on, leading to faster switching speed and lower switching loss compared with a traditional gate driver. LTSPICE simulation and double pulse test experiment based on 1.2-kV/60-A silicon-carbide MOSFETs are conducted to evaluate the crosstalk suppression capability of the proposed gate driver.

A Dual-Switch Discontinuous Current-Source Gate Driver Overcoming the Current Diversion Problem for a Buck VRM

In this article, a novel dual-switch discontinuous current-source gate driver (CSD) suitable for driving the high-side mosfet (HS mosfet ) of buck voltage regulator module (VRM) is presented. The proposed gate driver completely solves the gate current diversion problem, which most of the previous CSDs suffer from, during turn- off transition. Thus, in comparison to most of the previous CSDs, the proposed gate driver achieves to turn- off the power mosfet considerably faster and with much higher effective gate current, which leads to significant reduction of turn- off losses. Whereas, turn- on losses of buck VRM HS mosfet driven by the proposed CSD and the previous CSDs are equal. Furthermore, the introduced gate driver consists of the minimum number of control switches and circuit elements, compared to previous CSDs. The proposed gate driver is analyzed and a prototype of the driver operating at 1 MHz is implemented in order to validate the theoretical analysis.