Programmable Look-up Table Research Articles

Improving Characteristics of FPGA-Based FSMs Representing Sequential Blocks of Cyber-Physical Systems

This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. The FSMs with twofold state assignment and encoding of output collections are discussed. The method is based on using two LUT-based cores to implement systems of partial Boolean functions. One of the cores uses only maximum binary codes, while the second core is based on the use of extended state codes. The hardware reduction is based on diminishing the number of transformed maximum binary codes. This leads to FPGA-based FSM circuits with three levels of logic blocks. Each logic block has a single level of LUTs. As a result, partial functions are represented by single-LUT circuits. The article shows a step-by-step procedure for the transition from the initial form of the FSM representation to its logical circuit (a network of programmable look-up table elements, flip-flops, and interconnects). The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based FSM circuits with significantly better area characteristics than for circuits produced by such methods as Auto and One-Hot of Vivado, JEDI, and twofold state assignment. Compared to these methods, the number of LUTs is reduced from 9.44% to 69.98%. Additionally, the proposed method leads to the following phenomenon: the maximum operating frequency is slightly improved as compared with FSM circuits based on twofold state assignment (up to 0.6%). The negative effect of these improvements is an increase in power consumption. However, it is extremely insignificant (up to 1.56%). As the values of the FSM’s main characteristics grow, there is an increase in the gain from the application of the proposed method. The conditions for applying the proposed method are determined. A generalized architecture consisting of three blocks of partial functions and a method for synthesizing an FSM with this architecture are proposed. A method for selecting one of the seven architectures generated by the generalized architecture is proposed.

Compact PUF Design With Systematic Biases Mitigation on Xilinx FPGAs

Physical unclonable functions (PUFs) are a strong and secure root source for identification and authentication applications. PUFs are especially valuable in FPGA-based systems because FPGA designs are vulnerable to intellectual property (IP) thefts and cloning, which PUFs protect against by generating random but device-specific bitstrings. Theoretically, the randomness of PUFs originates from variations in the manufacturing process. PUFs should be free of deterministic variation owing to the systematic bias among all chips of the same model. Correspondingly, one of the major challenges for FPGA-based PUFs is the difficulty of avoiding systematic bias between nominally matched delays in competing paths. In this paper, a deep investigation into the LUT structure on a Xilinx FPGA was conducted. Based on the investigation findings, a compact PUF design based on programmable look-up table paths is proposed. The proposed intertwined structure and the novel 2-phase, 2-pass scheme significantly reduced the impact of systematic biases in the Xilinx FPGA LUT. The proposed PUFs exploit random variations in LUTs, thus exhibiting very good uniformity and uniqueness among the generated bitstrings.

Low-Power Built-in Jitter Injection Using Linearized Phase Interpolator

Low-power circuits built in optical transceivers that can be used in characterizing phase interpolators (PIs) and injecting jitter to test the tolerance of clock-data recovery (CDR) are presented. The novelty is in digitally controlling a precompensated PI in the feedback path of a phase lock loop. The latter is driving the sampling clock of the digital-to-analog converter at the transmitter. To improve the accuracy of jitter mask measurements at the receiver, the nonlinearity of used PI is compensated by the mean of a programmable lookup table (LUT), which is populated using a built-in test circuitry. As well, the LUT can serve to allow for generating jitter frequencies that are out of phase-locked loop bandwidth. Both linearization and jitter injection methods are generic and can be applied to any wireline transceivers at both client and modem interface sides.

Feedback Circuit Module in Frequency-Nondegenerate Entanglement Swapping Experiment

In this paper, a dedicated feedback circuit module is designed for an experiment of entanglement swapping with frequency-nondegenerate photons. This experiment, aiming to entangle two frequency-nondegerate photons without prior interaction, is an advanced strategy for quantum communication. The key point of the experiment is to actively compensate a random phase shift originating from the frequency difference. The feedback circuit module has functions of measuring the time intervals, converting the time information to control level codes, and outputting control levels to an electro-optic modulator (EOM). A precision TDC is implemented in a field programmable gate array (FPGA) with 40 ps per LSB ( σRMS is less than 30 ps). A programmable look-up table is used as computing unit. The propagation delay time of the whole circuit module is less than 110 ns.

Sagnac-interferometer-based characterization of spatial light modulators

A method for characterizing the phase response of spatial light modulators (SLMs) by using a Sagnac interferometer is proposed and demonstrated. The method represents an improvement over conventional diffraction-based or interferometric techniques by providing a simple and accurate phase measurement while taking advantage of the inherent phase stability of a Sagnac interferometer. As a demonstration, the phase response of a commercial liquid crystal on a silicon SLM is characterized and then linearized by using a programmable lookup table. The transverse phase profile over the SLM surface is also measured.

The ATLAS level-1 central trigger processor core module (CTP/spl I.bar/CORE)

ATLAS is a detector at CERN's Large Hadron Collider where bunches of protons in counter-rotating beams will cross every 25 ns producing, on average, about 25 collisions for a total interaction rate of 1 GHz. A three-level trigger system selects bunch crossings potentially containing interesting processes. The Level-1 trigger, implemented in electronics and firmware, makes an initial selection in under 2.5 /spl mu/s with an output rate of less than 100 kHz. A key element of this is the core module of the Central Trigger Processor which combines trigger information from the calorimeter and muon trigger processors to make the final Level-1 accept decision in under 75 ns. The event-selection algorithm used by the core module is based on lists of selection criteria, i.e., trigger menus, and is implemented in fully programmable look-up tables and content-addressable memories. In addition to the event selection, the core module generates dead-time in order to limit the frequency of Level-1 accepts to a rate that the sub-detector front-end electronics can support. The core module further provides trigger-summary information to the Level-2 trigger and to the data acquisition system. The design of the core module is presented, and results from recent laboratory tests and from tests with the calorimeter and muon trigger processors connected to detectors in a particle beam are shown.

Design, fabrication and evaluation of a high-performance XGA VAN-LCOS microdisplay

The design, fabrication and evaluation of a high-performance 0.9 in. diagonal XGA microdisplay is described. The DRAM type active matrix comprises square pixels with a 17.6 μm pitch. Bi-directional row and column drivers are integrated on-chip. A 4-metal 0.35 μm CMOS technology enabled the design of a very effective light shield. The peripheral interface electronics supports a programmable look-up table with 10-bit voltage values, as well as programmable threshold voltage and steepness settings, all accessible through a graphic user interface. A vertically aligned nematic liquid crystal mode with an inorganic SiO 2 homeotropic alignment layer yields contrast ratios exceeding 1900:1 and video-compatible response times.

A 40 MHz pipelined trigger for K/sup 0//spl rarr/2/spl pi//sup 0/ decays for the CERN NA48 experiment

A first level trigger system based on a 40 MHz digital pipeline has been developed for the CERN NA48 experiment, aiming at measuring CP violation in K/sup 0//spl rarr/2/spl pi/ decays. The outputs of the 13340 cells of the 10 m/sup 3/ liquid krypton calorimeter are summed into 64 X and 64 Y projection strips and continuously digitised with 40 MHz FADCs. This information is used to reconstruct at each clock cycle and for the two calorimeter projections, the number of clusters, the impact time of each of them (with a precision of about 3 ns), their total energy and the first and second moments of the energy distribution. Based on the quantities listed above, a programmable look-up table system subsequently computes online the longitudinal position of the kaon decay vertex and performs an event selection. The system is described.

A microcomputer based digital imaging system for ion microanalysis

SUMMARYA microcomputer based digital imaging system was developed for a Cameca IMS‐3f ion microscope permitting real‐time digital acquisition of secondary ion images. Image signal‐to‐noise enhancement results from random noise reduction by real‐time ensemble averaging and from a reduction of pattern noise in the charge injection device (CID) array by subtraction of blank frames. Acquired images comprise 244times248 pixel arrays with 8‐bit intensity resolution. Images are displayed on a colour monitor in a grey scale or pseudo‐colour using one of four programmable lookup tables. Image processing software permits off‐line ion image enhancement and manipulation as well as multitechnique digital image correlations. System capability is illustrated by a biological example involving digital imaging studies of Al distribution in osteomalacic bone tissue, including correlative light microscopy and ion microanalysis.