Semiconductor Wafer Processing Research Articles

An Alternative Integrated-Circuit Yield Model

This paper develops a model to predict the number of good integrated circuits (the yield) from a semiconductor wafer processing line. The model is different from other published models and predicts observed outcomes better. Many models tend to predict lower yields than those actually achieved because those models are inherently incapable of predicting the average number of good chips per wafer. The model developed in this paper is based on combinatorial analysis and considers the number of die sites on the wafer and the total number of yield detracting defects on the wafer. In contrast the other models referenced require at least two parameters as input data: the area of one die site or chip and the average defect density. A third parameter, the Cdf of the defect density is often implied by the selection of the model.

The Preparation of Semiconductor Devices by Lapping and Diffusion Techniques

A new approach to the fabrication of semiconductor devices has been investigated. This approach allows the processing of large semiconductor wafers to a point where they can be diced into numerous and identical devices. Lapping, instead of etching, is employed for all shaping of the units, and the high degree of precision built into the lapping apparatus is passed on to all of the devices prepared. The approach is applicable to the fabrication of a great variety of semiconductor devices. Unipolar, photo-unipolar, as well as bipolar transistors and negative resistance devices, have been fabricated. These devices exhibit superior electrical characteristics. Silicon power transistors have current transfer ratios in the 20 to 40 range and power gains from 30 to 40 db. Silicon unipolar transistors have transconductances in the neighborhood of 500 ?mhos and input resistance of about 100 megohms. Silicon photo-unipolar transistors show a dc photo response of 2 to 20 a per 1m.

The preparation of semiconductor devices by lapping and diffusion techniques

A new approach to the fabrication of semiconductor devices has been investigated. This approach allows the processing of large semiconductor wafers to a point where they can be diced into numerous and identical devices. Lapping, instead of etching, is employed for all shaping of the units and the high degree of precision built into the lapping apparatus is passed on to all of the devices prepared. The approach is applicable to the fabrication of a great variety of semiconductor devices. Unipolar photounipolar as well as bipolar transistors and negative resistance devices have been fabricated. These devices exhibit superior electrical characteristics. Silicon power transistors have current transfer ratios in the 20-40 range and power gains from 30-40 db. Silicon unipolar transistors have transconductances in the neighborhood of 500 µmhos and input resistances of about 100 megohms, Silicon photounipolar transistors show a dc photo response of 2-20 amperes per lumen.