Semiconductor Device Processing Research Articles

Suspended single-crystalline oxide structures on silicon through wet-etch techniques: Effects of oxygen vacancies and dislocations on etch rates

Wet-etch techniques to realize suspended microscale structures of single-crystalline SrTiO3 and BaTiO3 grown on Si are explored. The authors examine the effects of oxygen vacancies and dislocations on etch rates. Both oxygen vacancies and dislocations enhance etching, yielding rates that are sufficiently high to enable conventional photoresist to serve as a mask layer. Suspended bridge structures are realized by etching the underlying Si substrate using a potassium hydroxide solution. The ability to realize suspended microscale structures using wet-etch techniques that are compatible with standard semiconductor device processing opens a pathway to integrate multifunctional oxides in microelectromechanical systems.

Coherent light matter interactions in nanostructure based active semiconductor waveguides operating at room temperature

Light matter coherent interactions require that the coherent state induced in the matter be maintained for the duration of the observation. The only way to induce and observe such interactions in room temperature semiconductors, where the coherence time is of the order of a few hundred femtoseconds, is to use ultrashort pulse excitations and an ultrafast characterization technique. For media comprising an ensemble of nanostructure semiconductors such as self-assembled quantum dots, the gain broadening inhomogeneity also affects the interaction. Moreover, when gain media in the form of an active waveguide, such as optical amplifiers, are used, the interaction is distributed and includes nonresonant incoherent phenomena that occur simultaneously with the coherent effects. Such a complex system can exhibit, nevertheless, clear coherent interactions even at room temperature. Using InAs/InP quantum dot and wirelike quantum dash amplifiers, Rabi oscillations, self-induced transparency, coherent control using spectral pulse shaping, Ramsey interference, and photon echo have been demonstrated. The characterization employed cross frequency resolved optical gating, and the experiments were accompanied by a comprehensive finite difference time domain model that solves the Maxwell and Lindblad equations. This work has major implications on the understanding of the details of dynamical processes in active semiconductor devices, on short pulse generation from semiconductor lasers, and on various future quantum devices.

(Invited) Low-Energy Plasma Enhanced Chemical Vapor Deposition and In-Situ Doping for Junction Formation in Group-IV Semiconductor Devices

In novel semiconductor devices, such as a tunnel field-effect transistor (TFET) [1,2], a resonant-tunneling device [3-5] and a semiconductor spin qubit [6], energy-band modulation in group -IV semiconductors using nanometer-scale heterostructure and local doping [7] with suppressed intermixing is a key technology. Additionally, 2-dimensional (2D) nanosheet semiconductor materials (e.g. graphene, silicene, tungsten disulfide and so on) are aggressively investigated [8]. In such a trend, as well as conventional low-temperature thermal processes, utilizing a low-energy plasma process has been explored. We have clarified that low-energy Ar plasma irradiation effectively induces surface reaction and epitaxy of Si-based group-IV semiconductor on Si(100) [9-19]. Our efforts in development of such material processing utilizing low-energy Ar plasma process will be presented. Without substrate heating, low-energy electron-cyclotron-resonance (ECR) Ar plasma chemical-vapor deposition (CVD) process has enabled epitaxy of strained/unstrained films of group-IV materials (Si, Ge, Si-Ge alloy and Si-C alloy) with in-situ doping and an atomic-layer (AL) doped structure (Fig. 1) [9-19]. Especially in the TFET, sub-nanometer-order (atomic-order) abrupt profile control of impurities (B or P) concentration will be examined in epitaxy and in-situ doping. As a typical issue in our plasma CVD, it is considered that surface segregation of impurity during Si deposition occurs and degrades the profile abruptness near the interface. However, it has been demonstrated that the abruptness can be improved by atomic-layer doping technique [14,18]. Additionally, it is found that electrical activity of B doped in Si tends to be lowered especially at higher concentration than 1019 cm-3, while higher-energy plasma irradiation effectively improves the activity. These imply that semiconductor device process can be performed at lower temperatures where unexpected thermal diffusion and reactions are effectively suppressed. Our recent challenge is penta-silicene formation from epitaxial Si nanosheet. We believe that 2D materials as a novel semiconductor will be obtained not only by atomically-controlled epitaxy of heterostructures but also by reconstruction of atomic arrangement at surface. Here, our target is penta-silicene transformed from a 3-atomic-layer-thick Si nanosheet, which is different from the diamond structure. Our concept is crystal structure transformation in the Si nanosheet, and this is based on long-range coordinated and double-sided surface reconstruction on Si(100) to form the penta-silicene (Fig. 2) [15]. Because penta-silicene has a 3-dimensional structure composed of 3 atomic layers (similar to tungsten disulfide), it is expected to be more stiff and stable physically than monolayer of hexa-silicene. Realization methods of the penta-silicene on Si wafer for large-scale integration of the penta-silicene devices are now in progress. After formation of penta-silicene, control of interface structure between the penta-silicene and gate insulator will be one of the important issues to control interface structure. From the view-point of material science and control of the interfaces in semiconductor, development of process technology must be proceeded further. Such efforts will encourage smart electronic devices for enabling artificial intelligence and higher security in the next-generation information society. Acknowledgements This work was partly supported by Grant-in-Aid for Challenging Exploratory Research (No. 18K18987) from the JSPS in Japan and the Cooperative Research Project Program of the Research Institute of Electrical Communication, Tohoku University.

Fabrication of a Bilayer Structure of Cu and Polyimide To Realize Circuit Microminiaturization and High Interfacial Adhesion in Flexible Electronic Devices.

With commercialization of the fifth-generation mobile communication system and the further spread of the Internet of Things, industrial innovation is arriving with new business fields related to concepts such as high-speed communication, self-driving vehicles, and remote medicine. One of the challenges is the realization of flexible devices with high-definition circuits, which requires new fabrication techniques for Cu films on polymer substrates to meet demands and an understanding of Cu/polymer interfacial nanostructure to assure product quality. We have developed a promising technique for the fabrication of Cu film on polyimide (PI), which consists mainly of very simple semiconductor device processes. This technique allows for control of the Cu thickness with nanometer precision to form miniaturized Cu circuits with potential advantages in terms of interfacial adhesion and material/production costs. The Cu/PI interfaces fabricated by conventional vapor deposition and the new technique are systematically analyzed using synchrotron hard X-ray photoelectron spectroscopy, scanning transmission electron microscopy, and time-of-flight secondary ion mass spectroscopy. With conventional vapor deposition, it was discovered that evaporated Cu atoms decompose the PI and an oxidation layer with a thickness of several nanometers that deteriorates the interfacial adhesion could be visualized at the Cu/PI interface. With the new technique, the decomposition of PI and interfacial oxidation are significantly suppressed. Furthermore, the proposed technique can be broadly applied to the investigation of metal/polymer interfaces fabricated by polymer coating on a metal substrate, which has so far been impossible.

Characteristic Change of GeO2 / Ge Interface By Hf-Post Metallization Annealing

Si has been widely used as primary semiconductor materials for electronic device fabrication. Due to the limitation of its electrical properties such as electron and hole mobilities, however, Ge would be one of the candidates for future electronic device materials because of its higher mobilities of both carieers. In addition, since Ge is the same Group IV semiconductor as Si, and physical as well as chemical properties are very similar, it can be considered that the manufacturing process of Si semiconductor devices can be followed, and the introduction cost can be suppressed. However, since GeO2 which composed of Ge-O chemical bonds is known to have water solubility and it reacts with Ge substrates at high temperature, it is well known that GeO desorption occurs at GeO2/Ge interface during higher temperature annealing process as well as during oxidation process itself, which causes deterioration of device characteristics. In this research, we attempted to improve interface characteristics by depositing Hf on the GeO2/Ge structure and applying heat treatment (PMA: Post Metallization Annealing). P-type and n-type Ge (100) substrates were cleaned with acetone and ethanol, and native oxide films were removed with dilute-HF dip. GeO2/Ge structure with film thickness of about 20 nm was prepared by thermal oxidation at 500 °C for 30 minutes. A thin metal Hf film was deposited by the sputtering method, and heat treatment was performed at 300 °C for 20 minutes. As the electrode for electrical characteristics measurements, Al films were deposited by vapor deposition, and the interface characteristics and insulating property was evaluated by C-V, TDS and I-V measurement. From C-V characteristics of GeO2 on both n-type and p-type Ge substrates with the measurement frequency of 1MHz, the injection type hysteresis, which means the existence of hole trap site in the GeO2 films adjacent to the GeO2/Ge interface, was observed in samples without PMA. By applying Hf-PMA, the hysteresis width has been drastically decreased. For C-V characteristics with changing the frequency of small AC signal during the measurements, on the other hand, less frequency dispersion can be seen from GeO2/n-Ge structure than that from GeO2/p-Ge samples. The difference of the calculated values of Dit distribution between GeO2/n-Ge and GeO2/p-Ge would be mainly due to the asymmetry of the Dit distribution in the bandgap of Ge, which is caused by the GeO desorption during the thermal oxidation at the GeO2/Ge interface. In fact, it is clearly shown that the decrease ratio in Dit value by the PMA process are almost the same between GeO2/n-Ge and GeO2/p-Ge. From the TDS measurement, GeO desorption starts below 500 °C in samples without PMA, whereas two steps desorption can been seen in that with PMA. Especially, the desorption with higher temperature range start above 600 °C This indicates that it took more energy to release GeO, a slight amount of Hf buried the GeO2 film desorpted GeO by Hf-PMA and the bonding of Ge-O became stronger. From the I-V measurement, we found that the leakage current was reduced and insulating property was improved by applying PMA. The insulating characteristics are more improved at positive bias for p-type and negative bias for n-type. This cause the band barrier of Metal/Oxide was more strengthened, the electron and the hole could not exceed the band barrier. Strengthening the Ge-O bond by applying PMA, the band barrier is also strengthened, and we consider that the leakage current is reduced. It was confirmed that Hf-PMA is effective for both types of Ge substrate as a solution to reduce the Dit values due to the GeO desorption during the oxidation process at the GeO2/Ge interface. For further thinning in the future, it is necessary to optimize the deposition amount of Hf and the PMA temperature and time.

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

With the increase in the complexity of the semiconductor device processes and increase in the challenge to satisfy high market demands, enhancement in yield has become a crucial factor. Discovering and reacting to yield problems emerging at the end of the production line may cause unbearable yield loss leading to larger times to market. Thus, time and cost involved in fault isolation may be significantly shortened by effectively utilizing the fault diagnosis technology and supporting yield improvements. Hence for yield analysis, a highly integrated data network with software analysis tools have been established to reduce the fault analysis time. Synopsys Avalon, a product used for fault localization is described in this paper which aids in achieving better integrated circuit yields. This paper also illustrates various fault localization techniques for faster problem identification and discusses a few analytical tools like photon emission microscope and transmission emission microscope for faster determination of device failures.

Radiation induced parasitic effect in silicon-on-insulator metal-oxide-semiconductor field-effect transistor

In this paper, we investigate the total ionizing dose (TID) effects of silicon-on-isolator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) with different sizes by using 60Co γ-ray. The SOI MOSFET contains a shallow trench isolation (STI) edge parasitic transistor and back gate parasitic transistor, in which STI oxide and buried oxide (BOX) are used as gate oxide, respectively. Although these parasitic effects are minimized by semiconductor device process, the radiation-induced trapped-charge can lead these parasitic effects to strengthen, thereby affecting the electrical characteristics of the main transistor. Since both the STI and BOX are sensitive to the TID effect, we try to distinguish their different influences on SOI devices in this work.The experimental results show that the characteristic degradation of device originates from the radiation-enhanced parasitic effect. The turning-on of the STI parasitic transistor leads the off-state leakage current to exponentially increase with total dose increasing until the off-state leakage reaches a saturation level. The threshold voltage shift observed in the narrow channel device results from the charge sharing in the STI, while the back gate coupling is a dominant contributor to the threshold voltage shift in short channel device. These results are explained by two simple models. The experimental data are consistent with the model calculation results. We can conclude that the smaller size device is more sensitive to TID effect in the same process.Furthermore, the influence of the negative bias at back gate and body on the radiation effect are also studied. The negative bias at back gate will partially neutralize the effect of positive trapped-charge in STI and that in BOX, thus suppressing the turning-on of STI parasitic transistor and the back gate coupling. The parasitic transistors share a common body region with the main transistor. So exerting body negative bias can increase the threshold voltage of the parasitic transistor, thereby restraining the TID effect. The experimental and simulation results show that the adjustment of the threshold voltage of parasitic transistor by body negative bias is limited due to the thin body region. The modulation of body negative bias in depletion region is more obvious in back gate parasitic transistor than in STI parasitic transistor. The weakening of parasitic conduction in the back channel is more noticeable than at STI sidewall under a body negative bias.

Defect-induced Stress Imaging in Single and Multi-crystalline Semiconductor Materials

Residual stress is a key feature which has to be taken into account in all steps of fabrication and processing of semiconductor materials and devices. The photo-elastic microscope SIREX (Scanning Infrared Stress Explorer) measures the depolarization of the light of an infrared laser probe caused by stress-induced birefringence in the sample. Subsequently, a map visualizes the in-plane optical anisotropy induced by stress. Hence, the system is applied as non-destructive tool to map stress distributions with high lateral resolution (3µm) and highest possible stress sensitivity (0.1 kPa). The so-called multi-polarization analysis results in maps of the in-plane maximum shear stress magnitude Δσ and the direction of the principal stress components. These maps can reveal the local stress fields of buried defects and their alignment in distinctive crystallographic directions. The fields are usually at least one order of magnitude larger in extension than the related defects themselves. Examples of extended defect structures in different crystalline semiconductor materials are presented in this paper. The emphasis has been put on line-shaped structures such as slip lines and twins which are partly accompanied by either tensile or compressive point-like stress sources. These structures are showing model characteristics for developing formal procedures of data and image processing under industrial conditions.

Statistical Leakage Analysis Using Gaussian Mixture Model

In the design process of advanced semiconductor devices, statistical leakage analysis has emerged as a major step due to uncertainties in the leakage current caused by the process variations. In this paper, a novel statistical leakage analysis which uses Gaussian mixture model (GMM) as the density function of leakage current is proposed. To estimate the probability density function, our proposed method clusters the rapidly converged leakage data using the GMM. The GMM can represent any distributions, so it is suitable to estimate the leakage distribution, which varies as the technology node or operating condition changes. In addition, our proposed method (SLA-GMM) defines a terminating condition that guarantees the convergence of the leakage data and prevents the underfitting or overfitting in the GMM modeling process. With sequential addition, SLA-GMM significantly reduced the error that can occur during the addition process. In studies with a goodness-of-fit test, SLA-GMM achieved up to 98% and 94% improvements in the Chi-square static and the K-S static compared with the previous method based on an analytic model.

New Compact Electron Cyclotron Resonance Plasma Source for Silicon Nitride Film Formation in Minimal Fab System

A compact magnetic-mirror confined electron cyclotron resonance plasma source for low-damage plasma processings was developed, especially aiming for the realization of high-quality silicon nitride film formation for the sub-micron complementary metal-oxide semiconductor device processes in the minimal fab system. The developed plasma source was installed in the minimal tool, and deposition of silicon nitride film was performed. The magnetic mirror confinement method worked well to excite the high-density plasma with low plasma excitation power of 10 W or less. By adopting the substrate position slightly apart from the core plasma region with the pressure range of 25 Pa, the silicon nitride film having the similar N/Si ratio to the ideal value of Si3N4 could be obtained in the room-temperature deposition. Under this condition, impurity concentration of oxygen in the film could be suppressed less than 1%, which was even smaller than that in the controlled low-pressure chemical-vapor deposited film at 750 °C.

Efficient Band-to-Trap Tunneling Model Including Heterojunction Band Offset

It is well-known that band-to-trap tunneling processes in semiconductor devices cause a significant increase in terminal currents under high electric fields [1-3]. Standard band-to-trap tunneling models such as those by Schenk [1-2] and Hurkx [3] are widely incorporated in TCAD device simulation tools [4]. However, these models were developed for silicon devices, so they did not include the effect of band offsets in heterojunction devices, though they are routinely used in simulating the latter. As shown recently by Myers [5], the band offsets at the emitter-base (E-B) junction in heterojunction bipolar transistors (HBTs) can greatly enhance the band-to-trap tunneling near the E-B junction and consequently exacerbate the degradation of gain due to radiation damage. In this paper, we propose an improved band-to-trap tunneling model based on Schenk’s approach, which includes heterojunction band offsets and can be easily implemented into device simulators. Within Schenk’s approach, the band-to-trap tunneling is modeled [1] as the Shockley-Read-Hall recombination with the field-dependent carrier lifetime τ(T, F) given by Fig. 1(a), where T and F denote temperature and electric field respectively, Et is the trap binding energy measured from the band edge, and I(z) denotes the modified Bessel function. Characteristics of band profile, including the effect of electric field, affect the field enhancement factor g(T, F) through the 3D tunneling density of states (DOS) ρF(E). Schenk used the constant field DOS expression in his original model, which is a reasonable approximation for homojunction devices. However, detailed calculations in Ref. [5] show that the E-B junction band offsets in HBTs can significantly increase the DOS near the junction. Myers [5] computes the DOS by numerically solving the Schrodinger equation for the actual potential profile in a NPN HBT. Different from Ref. [5], we approximate the actual potential (e.g., black curve in Fig. 1b) by a linear potential with band offset (red curve in Fig. 1b), and develop an analytic DOS model that includes the band offset, for efficiency and easy implementation in device simulation. The new DOS model is obtained through the following steps: (i) separate the plane parallel to the heterojunction from the direction perpendicular to the junction and use the zero-field 2D DOS for the parallel plane; (ii) approximate the 1D potential along the perpendicular direction using a piece-wise linear profile with band offsets and analytically solve for the wave function in each region with open boundaries at the two outmost ends; (iii) normalize the 1D wave functions according to the Dirac Delta normalization condition [6]; (iv) compute the 3D tunneling DOS that goes into the Schenk model from the zero-field 2D DOS and the normalized 1D wave functions. Figure 1(c) shows a comparison of the 3D tunneling DOS versus carrier energies, computed by several methods, for the red potential in Fig. 1(b). The constant field DOS expression depends only on the field strength, not on the spatial location, as shown by the black solid curve. The color solid curves were obtained using the Fortran code provided by Myers [5] that numerically solves the Schrodinger equation and computes the DOS for the red potential. The color dashed curves were computed using the analytic DOS model proposed in this work. As expected, our analytic model produces the same DOS as those of the numerical method for the given potential. It is clearly seen that, when taking account of the heterojunction band offset, the DOS can be much higher than that of the constant field approximation. In particular, the closer the trap is located to the heterojunction, the higher the DOS is than the constant field value. For example, at 5 nm from the junction, the computed DOS using our model is more than ten orders of magnitude higher than that of the constant field expression for energies of 0.25 eV below the band edge. The substantially increased DOS near the heterojunction is expected to significantly enhance the band-to-trap tunneling in the vicinity of the junction. It turns out that the proposed DOS model can be generalized to arbitrary piece-wise linear 1D potentials. The band-to-trap tunneling model with the new DOS is being implemented in CHARON, an open-source multi-dimensional parallel TCAD code developed at Sandia National Laboratories. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the United States Department of Energy's National Nuclear Security Administration under Contract DE-AC04-94AL85000. Figure 1

Simulation of SiO2 etching in an inductively coupled CF4 plasma

Plasma etching technology is an indispensable processing method in the manufacturing process of semiconductor devices. Because of the high fluorine/carbon ratio of CF4, the CF4 gas is often used for etching SiO2. A commercial software ESI-CFD is used to simulate the process of plasma etching with an inductively coupled plasma model. For the simulation part, CFD-ACE is used to simulate the chamber, and CFD-TOPO is used to simulate the surface of the sample. The effects of chamber pressure, bias voltage and ICP power on the reactant particles were investigated, and the etching profiles of SiO2 were obtained. Simulation can be used to predict the effects of reaction conditions on the density, energy and angular distributions of reactant particles, which can play a good role in guiding the etching process.

Effect of isopropanol on gold assisted chemical etching of silicon microstructures

Wet etching is an essential and complex step in semiconductor device processing. Metal-Assisted Chemical Etching (MacEtch) is fundamentally a wet but anisotropic etching method. In the MacEtch technique, there are still a number of unresolved challenges preventing the optimal fabrication of high-aspect-ratio semiconductor micro- and nanostructures, such as undesired etching, uncontrolled catalyst movement, non-uniformity and micro-porosity in the metal-free areas. Here, an optimized MacEtch process using a nanostructured Au catalyst is proposed for fabrication of Si high aspect ratio microstructures. The addition of isopropanol as surfactant in the HF-H2O2 water solution improves the uniformity and the control of the H2 gas release. An additional KOH etching removes eventually the unwanted nanowires left by the MacEtch through the nanoporous catalyst film. We demonstrate the benefits of the isopropanol addition for reducing the etching rate and the nanoporosity of etched structures with a monotonic decrease as a function of the isopropanol concentration.

Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing

Advanced wafer-level packaging (WLP) techniques, mainly driven by high-performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology have been widely studied and developed over the last decade for use in various WLP technologies, such as package on package, fan-out integration, and 2.5-D and 3-D integration using through-silicon-via. Temporary bonding technology enables handling of thinned substrates (<100 μm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics was developed for temporary wafer bonding applications. These materials target high-temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (<5 μm) after grinding and have successfully passed a 200°C plasma-enhanced chemical vapor deposition (PECVD) process without any delamination during grinding and PECVD processes.

Solution Processable Metal Oxide Thin Film Deposition and Material Growth for Electronic and Photonic Devices

A comprehensive review of recent advances in solution processing and growth of metal‐oxide thin films for electronic and photonic devices is presented, with specific focus on precise solution‐based technological coatings for electronics and optics, and new concepts for oxide material growth for electrochemical, catalytic, energy storage and conversion systems, information technology, semiconductor device processing and related devices. Throughout, the nature of the soluble precursors solutions and their relationship to film formation process by various solution coating techniques are collated and compared, highlighting advantages in precursor design for creating complex oxides for devices. Because of the versatility of solution‐processable oxides and functional material coating, it is important to capture the advances made in oxide deposition for plastic electronics, see‐through and wearable devices, and high‐fidelity thin film transistors on curved or flexible displays. Solution processing, even for oxides, allows control over composition, thickness, optical constants, porosity, doping, tunable optical absorbance/transmission, band structure engineering, 3D‐substrate coating, complex composite oxide formation and multi‐layered oxide systems that are more difficult to achieve using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. We also discuss limitations of solution processing for some technologies and comment on the future of solution‐based processing of metal‐oxide materials for electronics, photonics and other technologies.

Fabrication, Testing, and Simulation of All-Solid-State Three-Dimensional Li-Ion Batteries.

Demonstration of three-dimensional all-solid-state Li-ion batteries (3D SSLIBs) has been a long-standing goal for numerous researchers in the battery community interested in developing high power and high areal energy density storage solutions for a variety of applications. Ideally, the 3D geometry maximizes the volume of active material per unit area, while keeping its thickness small to allow for fast Li diffusion. In this paper, we describe experimental testing and simulation of 3D SSLIBs fabricated using materials and thin-film deposition methods compatible with semiconductor device processing. These 3D SSLIBs consist of Si microcolumns onto which the battery layers are sequentially deposited using physical vapor deposition. The power performance of the 3D SSLIBs lags significantly behind that of similarly prepared planar SSLIBs. Analysis of the experimental results using finite element modeling indicates that the origin of the poor power performance is the structural inhomogeneity of the 3D SSLIB, coupled with low electrolyte ionic conductivity and diffusion rate in the cathode, which lead to highly nonuniform internal current density distribution and poor cathode utilization.

Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing

Abstract Advanced wafer-level packaging (WLP) techniques, mainly driven by high performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology has been widely studied and developed over the last decade for use in various WLP technologies, such as package-on-package (PoP), fan-out integration, and 2.5-D and 3-D integration using through-silicon-via (TSV). Temporary bonding technology enables handling of thinned substrates (<100 μm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics were developed for temporary wafer bonding applications. These materials target high temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All of these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (TTV < 5 μm) after grinding and have successfully passed a 200°C PECVD process without any delamination during grinding and PECVD processes.

Nonradiative Charge-Transfer Exciton Recombination at Organic Heterojunctions

Nonradiative recombination is one of the key electronic processes in semiconductor devices. In this study, we demonstrate that nonradiative recombination rate of intermolecular charge-transfer (CT) exciton at organic heterojunction increases exponentially with decreasing energy difference between the LUMO of acceptor and the HOMO of donor. In addition, the effect of orbital overlap between the acceptor LUMOs and donor HOMOs on nonradiative recombination is studied using a wide bandgap organic spacer layer. It is found that the rate for nonradiative CT exciton recombination decreases exponentially as the donor–acceptor separation distance increases. Nonradiative CT exciton recombination is an important consideration in selecting materials for organic devices such as organic solar cells, organic light-emitting diodes, and so on.

A Novel Sol–Gel $\gamma $ -Al2O3 Thin-Film-Based Rapid SAW Humidity Sensor

In this paper, we are proposing a novel rapid sol–gel thin-film porous metal–oxide-based surface acoustic wave (SAW) humidity sensor. For the SAW sensor, the center frequency of 433.92 MHz has been selected, and the device has been configured in a high-frequency oscillator circuit to explore the frequency response in the presence of water vapor. The sensitive thin film of sol–gel $\gamma $ -Al2O3 coated with a drop dry method offers very high surface-to-volume ratio with the distribution of micropores making the sensor highly sensitive for moisture detection. Pore morphologies of the film have been studied by field emission scanning electron microscope and atomic force microscopy. The $\gamma $ phase of alumina of the film has been characterized with X-ray diffraction. The sensor has been tested from 3% relative humidity (RH) to 85% RH. The proposed sensor has very fast ( $T_{r}= 1$ s) response time and excellent yield ratio in comparison with the conventional commercial capacitive aluminum oxide sensor. The sensitivity (3%–20% RH) and the hysteresis (3%–85% RH) are found to be 120-Hz/% RH and 0.3%, respectively. The sensor can be useful for different applications, including moisture dispersion inside electronic gadgets, dryers, ovens, textile production, semiconductor device processing, food processing, medicine, and sealed packages.

Piezoelectric Size Effects in a Zinc Oxide Micropillar.

In this work, the dependence of piezoelectric coefficients (PE) on the size of artificial fabricated ZnO micropillars on Si substrate is investigated. ZnO full film is grown with c-axis orientation and an average grain size of 20 nm at a substrate temperature of 500 °C by pulsed laser ablation. The micropillars with the size range of 1.5 to 7 μm are formed by top-down semiconductor device processing. The PE, characterized by piezoelectric force microscopy (PFM), is found to increase from 18.2 to 46.9 pm/V, when the ZnO pillar size is reduced from 7 to 1.5 μm. The strong PE dependence on ZnO pillar size can be explained by local changes in polarization and reduction of unit cell volume with respect to bulk values. These results have strong implications in the field of energy harvesting, as piezoelectric voltage output scales with the piezoelectric coefficient.