Printed Circuit Board Routing Research Articles

GPCB Routing: Generative Pre-Trained Transformers Based Printed Circuit Board Routing Method

GPCB Routing: Generative Pre-Trained Transformers Based Printed Circuit Board Routing Method

FanoutNet: A Neuralized PCB Fanout Automation Method Using Deep Reinforcement Learning

In modern electronic manufacturing processes, multi-layer Printed Circuit Board (PCB) routing requires connecting more than hundreds of nets with perplexing topology under complex routing constraints and highly limited resources, so that takes intense effort and time of human engineers. PCB fanout as a pre-design of PCB routing has been proved to be an ideal technique to reduce the complexity of PCB routing by pre-allocating resources and pre-routing. However, current PCB fanout design heavily relies on the experience of human engineers, and there is no existing solution for PCB fanout automation in industry, which limits the quality of PCB routing automation. To address the problem, we propose a neuralized PCB fanout method by deep reinforcement learning. To the best of our knowledge, we are the first in the literature to propose the automation method for PCB fanout. We combine with Convolution Neural Network (CNN) and attention-based network to train our fanout policy model and value model. The models learn representations of PCB layout and netlist to make decisions and evaluations in place of human engineers. We employ Proximal Policy Optimization (PPO) to update the parameters of the models. In addition, we apply our PCB fanout method to a PCB router to improve the quality of PCB routing. Extensive experimental results on real-world industrial PCB benchmarks demonstrate that our approach achieves 100% routability in all industrial cases and improves wire length by an average of 6.8%, which makes a significant improvement compared with the state-of-the-art methods.

Mobility based Net Ordering for Simultaneous Escape Routing

With the advancement in electronics technology, number of pins under the ball grid array (BGA) are increasing on reduced size components. In small size components, a challenging task is to solve the escape routing problem where BGA pins escape towards the component boundary. It is often desirable to perform ordered simultaneous escape routing (SER) to facilitate area routing and produce elegant Printed Circuit Board (PCB) design. Some heuristic techniques help in finding the PCB routing solution for SER but for larger problems these are time consuming and produce sub-optimal results. This work propose solution which divides the problem into two parts. First, a novel net ordering algorithm for SER using network theoretic approach and then linear optimization model for single component ordered escape routing has been proposed. The model routes maximum possible nets between two components of the PCB by considering the design rules based on the given net ordering. Comparative analysis shows that the proposed net ordering algorithm and optimization model performs better than the existing routing algorithms for SER in terms of number of nets routed. Also the running time using proposed algorithm reduces to O(2NE=2) + O(2NE=2) for ordered escape routing of both components. This time is much lesser than O(2NE) due to exponential reduction.

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design

With the increasing complexity of circuit design in recent years, the pin assignment and escape routing problems for field-programmable gate array (FPGA) on a printed circuit board (PCB) have become greatly difficult due to the fast increase in pin count and density. Most existing works only focus on either the FPGA pin assignment problem or the PCB escape routing problem independently, but cannot handle them simultaneously. In this paper, we propose an integer linear programming based method to simultaneously solve the problem of pin assignment and escape routing for FPGA-PCB co-design. Moreover, differential pairs and single-ended signals are handled together optimally to minimize the total wirelength in escape routing. Encouraging experimental results are shown to support our approach showing reduction in the number of PCB routing layers and/or wirelength.

Characterization of PCB routing process and optimization of tool design based on the investigation of routing temperature

Purpose – The purpose of this paper is to provide the method and system to conduct online measurement and the characterization of temperature during printed circuit board (PCB) routing process as well as the optimization of router design based on the investigation of routing temperature. Design/methodology/approach – The background of this research is introduced first. Then the method to measure the routing temperature on-line by using an infrared camera is presented. The routing process is characterized by investigating the routing temperature. Tool design optimization is conducted based on the temperature in processing PCB with aluminum substrate. Finally the concluding remarks of this research are presented. Findings – The routing temperature can be accurately measured by an infrared camera. Routing temperature is sensitive to properties of PCB, types of router and routing parameters. Very high temperature is experienced if non-appropriate routers are used to process board with aluminum substrate. It is demonstrated by the experiments that two fluted tool, three fluted tool and coated tool with three flutes are suitable for aluminum substrate processing by considering the low temperature and the nice surface finish. Originality/value – The paper highlights the key points to measure the routing temperature on-line by an infrared camera and characterize the routing process and optimize the tool design by investigating the measured temperature as well.

Escape Routing for Staggered-Pin-Array PCBs

To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. A linear programming/integer linear programming-based algorithm is presented to solve the staggered-pin-array escape routing problem. Experimental results show that our approach successfully routes all test cases efficiently and effectively.

NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing

In this paper, we introduce and study the rectangle escape problem (REP), which is motivated by printed circuit board (PCB) bus escape routing. Given a rectangular region R and a set S of rectangles within R, the REP is to choose a direction for each rectangle to escape to the boundary of R, such that the resultant maximum density over R is minimized. We prove that the REP is NP-complete, and show that it can be formulated as an integer linear programming (ILP). A provably good approximation algorithm for the REP is developed by applying linear programming (LP) relaxation and a special rounding technique to the ILP. In addition, an iterative refinement procedure is proposed as a postprocessing step to further improve the results. Our approximation algorithm is also shown to work for more general versions of REP: weighted REP and simultaneous REP. Our approach is tested on a set of industrial PCB bus escape routing problems. Experimental results show that the optimal solution can be obtained within several seconds for each of the test cases.

BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology

Length-constrained routing is a very important issue for printed circuit board (PCB) routing. Previous length-constrained routers all have assumptions on the routing topology, whereas practical designs may be free of any topological constraint. In this paper, we propose a routing scheme that deals with general topology. Unlike previous works, our approach does not impose any restriction on the routing topology. Moreover, our routing scheme is gridless. Its performance does not depend on the routing grid size of the input while the routers in the papers of Ozdal and Wong and Kubo do. This is a big advantage because modern PCB routing configurations usually imply huge routing grids. The novelty of this work is that we view the length-constrained routing problem as an area assignment problem and use a placement structure, which is the bounded-sliceline grid, to help transform the area assignment problem into a mathematical programming problem. We then use an iterative approach to solve this mathematical programming problem. Experimental results show that our routing scheme can handle practical designs that previous routers cannot handle. For designs that they could handle, our router runs much faster. For example, in one of our data, we obtain the result in 88 s while the Lagrangian relaxation based router by Ozdal and Wong takes more than one day.

Algorithms for simultaneous escape routing and Layer assignment of dense PCBs

As die sizes are shrinking, and circuit complexities are increasing, the printed circuit board routing problem becomes more and more challenging. Traditional routing algorithms cannot handle these challenges effectively, and many high-end designs in the industry require manual routing efforts. This paper proposes a problem decomposition that distinguishes routing under dense components from routing in the intermediate area. In particular, it proposes an effective methodology to find the escape routing solution for multiple components simultaneously such that the number of crossings in the intermediate area is minimized. For this, the problem is modeled as a longest path with forbidden pairs problem, and two algorithms are proposed for it. The first is an exact polynomial-time algorithm that is guaranteed to find the maximal planar routing solution on one layer. The second is a randomized algorithm that has good scalability characteristics for large circuits. Then, these algorithms are used to assign the maximal subset of planar nets to each layer, and then the remaining nets are distributed at the end. This paper demonstrates the effectiveness of these algorithms through experiments on industrial circuits.

Robust methods for EMC-driven routing

Due to the application of fast device technologies and the increasing complexity of printed-circuit boards, electromagnetic phenomena, e.g. reflections and crosstalk, gain more and more importance and may even disturb the function of a circuit. In the future, it will be indispensable to already consider phenomena of electromagnetic compatibility (EMC) during layout synthesis. In this paper, robust methods are presented that make it possible for the first time to incorporate complex EMC constraints and cost criteria into printed-circuit board routing. This includes both concepts for the development and specification of EMC design models and robust and efficient algorithms for EMC-driven routing that can handle these models. >

Efficient routing algorithm

The line expansion algorithm provided by Heynes was a new kind of routing algorithm that took advantage of both Lee's algorithm and linear expansion algorithms, and hence was more efficient. However, it was less efficient in two layer routing situations. In this paper, this problem is analysed and several ways of solving it are proposed. Three criteria are provided in the paper, and these are used in the development of a modified line expansion algorithm. The modified algorithm is not only fast but also consumes less memory in two layer routing situations. Based on this algorithm, a Fortran printed circuit board routing system is built that can solve two layer routing problems with up to 2600 connection lines on a microcomputer with 64 kbyte RAM.

An Approximation Problem for the Multi-Via Assignment Problem

We consider the multi-via assignment problem for multilayered printed circuit board routing. An efficient approximation algorithm for this problem is presented. The algorithm is of (low) polynomial time complexity and guarantees solutions with no more than 3 * OPT via columns, where OPT is the number of via columns in an optimal solution. Several issues relating to the computational complexity of via and multi-via assignment problems are also discussed.

Printed Circuit Board Routing: A Survey

The circuit layout problem is an important and difficult problem of computer system design and is encountered in laying out subpackages (e.g. PCBs and integrated circuit masks), where the terminals of a set of components placed on a subpackage are to be interconnected by laying printed wires. The specific set of pins (i.e. terminals) to be made electrically common by printed wire constitutes a single net. Realization of multiple nets on the surface of the PCB is classically termed as ‘Interconnection Problem’ by Hightower (1974) which consists of five sub problems—(i) pin assignment, (ii) Steiner-tree identification for a net, (iii) layering of the wires, (iv) ordering and (v) physical identification of wire path on a PCB. An exhaustive survey on all these subproblems is available in the book edited by Breuer (1972) and survey papers of Hightower (1974), Bose (1977). In this paper, we concentrate on an up-to-date survey of the last sub problem (i.e. wire routing of PCBs). We group together the wire-routin...