Printed Circuit Board Level Research Articles

Validation of IC Conducted Emission and Immunity Models Including Aging and Thermal Stress

Environmental factors, such as aging and thermal stress, can seriously impact the electromagnetic compatibility behavior of an integrated circuit (IC). The standardized IC emission model for conducted emission (ICEM-CE) and IC immunity model for conducted immunity (ICIM-CI) can be used in industry to predict electromagnetic behavior at the IC and the printed circuit board level. However, these do not take into account the effect of aging and extreme temperature variations. In this article, a custom IC designed in silicon-on-insulator technology, containing several independent analog blocks, is used to characterize the influence of aging and temperature on conducted emission and immunity through measurements and transistor-level simulations. The highly accelerated temperature and humidity stress test (HAST) was performed to evaluate aging and its influence on IC parameters. The results show that the passive distribution network is only influenced by thermal stress and not HAST aging. The latter mainly affects the active elements in the IC and reduces the conducted emission and immunity levels through intrinsic permanent degradation mechanisms. Furthermore, thermal stress mainly causes drifts in the transistor characteristics (such as threshold voltage and effective mobility), which affect the conducted emission and immunity levels and resulting in soft failures. All drifts/tolerances collected from measurements and simulations are characterized in a way that makes it possible to include them in potential future versions of the ICEM-CE and ICIM-CI standards.

On the Correlation Between Near-Field Scan Immunity and Radiated Immunity at Printed Circuit Board Level – Part II

The work presented in this two-part paper focuses on a prediction method of the radiated susceptibility of integrated circuit and printed circuit board from near-field scan injection, in order to anticipate risks of noncompliance due to design weakness. In Part I, a worst-case estimator of the far-field induced voltage on a PCB trace was proposed. Based on it, an estimator of the radiated susceptibility of a printed circuit board based on near-field scan results is derived and validated through two validation case studies.

On the Correlation Between Near-Field Scan Immunity and Radiated Immunity at Printed Circuit Board Level – Part I

Near-field (NF) scan immunity is a powerful technique to identify the root-cause of failures produced during radiated immunity (RI) tests at the integrated circuit and printed circuit board (PCB) levels. However, a prediction method of the RI level from NF scan immunity results is still lacking. This type of method would help board designers to anticipate risks of RI noncompliance related to PCB directly after an NF scan campaign. This two-part article addresses this issue. In the first part, the equivalence between far-field (FF) and NF coupling on a microstrip line is discussed in order to derive an estimator of the FF induced voltage from NF scan results.

Evaluation of Cost-Effective Flexible High-Speed Data Exchange Links for Heterogeneously Integrated Multi-Chip Modules and Boards

With increasing complexity and heterogeneity, miniaturized integrated system on both multi-chip module and printed circuit board levels relies more and more on high-speed point-to-point serial signal transmission links as the backbone of inter-chip data signal exchange network, which are inevitably accompanied by signal integrity problems such as loss, reflection, and crosstalk. The difficulties in the physical design phase of interconnect routing for high-speed link on densely occupied package interposers or printed circuit boards and the associated planar area overhead (keep-out zone for the crosstalk prevention and impedance matching, etc.), as well as the relevant cost in manufacturing, performance analysis and actual measurement or evaluation, are also sharply increasing; furthermore, the interconnects implemented on interposer or printed circuit board substrate are physically inflexible, and the corresponding microsystems are not suitable for emerging applications that generally demand good deformability and good conformality to 3-dimensionally shaped mounting surface. How to simultaneously elevate the cost-effectiveness, signal transmission performance and physical flexibility of the high-speed link, while keeping low profile of the whole module, has become one of the major challenges in the evolution of micro/nano system technology. Accordingly, this paper proposes a cable-based point-to-point link method, which adopts physically flexible and widely available off-the-shell cables that can be assembled onto the surface of the interposers or boards as a potential cost-effective solution to the challenge mentioned above. Universal Serial Bus, micro-coaxial cables, and Twinax cables are explored as candidates. The full links for each cable, from one of the paired connectors to another, are physically modeled and validated by an electromagnetic full-wave structural simulation tool, with key components of each type of link taken into considerations. The simulated results and the measured results from vector network analyzers are compared, which verifies the effectiveness of our proposal.

On the use of Magnetically Coupled Resonant Snubbers to Mitigate the Electromagnetic Emission of Power Switching Circuits

This letter presents a novel solution to attenuate the electromagnetic emission of power switching circuits due to the resonance of the loop parasitic inductances with the parasitic capacitances of the power devices. A resonant snubber based on the magnetic coupling of a power parasitic loop causing unwanted oscillations with another one inserted at the printed circuit board level purposely and loaded by a dissipative element, is presented. A design method is proposed and used to damp the unwanted oscillations affecting the switching voltage and current in a prototype, which was specifically designed and fabricated to validate the proposed solution. The conducted emission delivered by such a prototype equipped with the resonant snubber, with an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber, and without any snubber are compared.

A two‐turn loop active magnetic field probe design for high sensitivity near‐field measurement

This paper develops an active magnetic near field probe (H-field probe) by using a four-layer printed circuit board (PCB) technique. Two-turn detection structure and a low noise amplifier are used to improve probe's frequency response. The two-turn detection structure can maximize the use of PCB stack resources, and a 14.5 dB gain amplifier can increase signal output capability. The probe can then be used for electromagnetic compatibility (EMC) test from 150 kHz to 3 GHz. Compared with traditional active shielded-loop H-field probe (TAHP) with loop area of 500 μm 2 , the frequency response of the proposed probe can improve 20 dB at 0.5 GHz. Different from the method of comparing the sensitivity of the probe only through the frequency response, this paper measures and analyzes the real sensitivity of the probing device composed of the proposed probe. Under the condition of the same receiver parameter setting, the sensitivity at 0.5 GHz is increased by 11.7 dB compared with commercial passive probing device and 20.2 dB at 0.5 GHz compared with the probing device with TAHP device. It reaches −32.4 dB μA. In addition, the proposed probe has acceptable spatial resolution of 1.28 mm at 1 GHz, which is more suitable for printed circuit board level EMI analysis.

SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure

A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermeasures at the PCB level are scarce. These approaches either suffer from significant overhead issues, or opportunistic counterfeiters can breach them like clockwork. Besides, they cannot be extended to system-level (both chip and PCB together), and their applications are also limited to a specific purpose (i.e., either counterfeiting or tampering). In this article, we introduce SILVerIn , a novel systematic approach to verify the authenticity of all chips used in a PCB as well as the board for combating attacks such as counterfeiting, cloning, and in-field malicious modifications. We develop this approach by utilizing the existing boundary scan architecture (BSA) of modern ICs and PCBs. As a result, its implementation comes at a negligible (∼0.5%) hardware overhead. SILVerIn is integrated into a PCB design during the manufacturing phase. We implement our technique on a custom hardware platform consisting of an FPGA and a microcontroller. We incorporate the industry-standard JTAG (Joint Test Action Group) interface to transmit test data into the BSA and perform hands-on measurement of supply current at both chip and PCB levels on 20 boards. We reconstruct these current values to digital signatures that exhibit high uniqueness, robustness, and randomness features. Our approach manifests strong reproducibility of signatures at different supply voltage levels, even with a low-resolution measurement setup. SILVerIn also demonstrates a high resilience against machine learning-based modeling attacks, with an average prediction accuracy of ∼51%. Finally, we conduct intentional alteration experiments by replacing the on-board FPGA to replicate the scenario of PCB tampering, and the results indicate successful detection of in-field modifications in a PCB.

Frequency response mismatch calibration in 2-channel time-interleaved oscilloscopes.

The time-interleaved (TI) structure has been widely implemented in high speed, wideband data acquisition systems to increase the system sampling rate. However, the frequency responses of each sub-sampling path are not identical. This is named frequency response mismatches (FRMs). In TI-based printed circuit board level systems, due to the impact of the parasitic parameters, the FRMs are more complicated than the mismatches in TI analog-to-digital converters (TIADCs), which degrade the system performance severely. Therefore, the FRM calibration in 2-channel TI acquisition systems with two features is researched. The first one is that the TI system has a larger mismatch range than in most previous research. The second one is that the channel frequency response uses the general model. The calibration structure is established by the analysis of the digital TI model, which implements the TI operation in the digital domain to reconstruct the mismatches in the time domain. Furthermore, the problem of designing an arbitrary frequency response filter is transformed to the question of designing a three-stage cascaded filter group, which gives a method to realize the arbitrary frequency response in a real system. An oscilloscope prototype is proposed to verify the calibration performance. The simulation and experiment show the following: (i) Even though it uses the general frequency response and the FRMs are significant, the proposed method is still effective. (ii) The mismatch range of magnitude and phase responses is highly suppressed, and the spurious-free dynamic range is improved by 16.26 dB after calibration of the prototype.

Measurement and Analysis of Electromagnetic Information Leakage From Printed Circuit Board Power Delivery Network of Cryptographic Devices

This article presents a novel measurement and analysis of electromagnetic (EM) information leakage from printed circuit board (PCB) power delivery network (PDN) of cryptographic devices. We propose an accurate EM information leakage analysis method based on a correlation electromagnetic analysis (CEMA) considering advanced encryption standard (AES) operation cycles and clock frequency. We measure field distribution on the PCB level AES core PDN and conduct the proposed analysis method to derive the information leakage maps. For the first time, we verified that the EM information leakage depends on the intensity of dominant field distribution on the PCB PDN using the proposed method. We validated that the whole secret key information can be extracted from locations in the PCB PDN distant from the cryptographic integrated circuit where a specific field is dominant due to the physical structure of the PCB PDN. Based on the measurement and analysis results, we discuss an efficient EM information leakage evaluation method based on the dominant field radiation. We evaluate the EM information leakage from the decoupling capacitor in the backside of the PCB. Finally, we propose a design methodology to suppress the EM information leakage from the PCB PDN.

Physics of Failure (PoF) Based Lifetime Prediction of Power Electronics at the Printed Circuit Board Level

This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a life-cycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.

IEEE Standard P2716 Update: Characterization of the Effectiveness of Printed Circuit Board Level Shielding

At the IEEE EMC and EMC Europe Symposia in 2013, the idea was raised to continue the work that had been started by IEEE 299 and IEEE 299.1 around the characterization of the shielding effectiveness (SE) of enclosures. IEEE 299–2006 (“IEEE Standard Method for Measuring the Effectiveness of Electromagnetic Shielding Enclosures”) covers enclosures having all dimensions greater than or equal to 2.0m. IEEE 299.1 (“IEEE Standard Method for Measuring the Effectiveness of Electromagnetic Shielding Enclosures”) covers enclosures and boxes having all dimensions between 0.1 m and 2 m. The question raised in 2013 was if there was interest in and need for an IEEE standard on the characterization of the effectiveness of shielding enclosures with even smaller sizes. As a side effect, the question on whether an IEEE standard around the characterization of the SE of planar materials was needed as no such guidance document was available at the time.

Analysis and Design of a Low-Cost Well-Performance and Easy-to-Design Current Sensing Circuit Suitable for SiC mosfets

Current sense resistor (CSR) is widely used due to cost and integration considerations in industrial applications. However, when CSRs are used to sense transient currents caused by power device switching, especially fast-switching silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (mosfets) with high di/dt, even a tiny parasitic inductance in CSRs bring a significant impact on its sensing performance. This article proposes a low-cost well-performance and easy-to-design current sensing circuit that uses the CSRs and an LR compensation network (LRCN) to compensate for the effect of parasitic inductance on transient current sensing. In order to support the parameter selection of the LR network, the effects of parameters such as parasitic capacitance, parasitic inductance, and loads on the performance of the proposed current sensing circuit are analyzed in detail. Meanwhile, a parasitic inductance measurement method that only needs passive probes is proposed to measure and calculate the parasitic inductance of CSRs. This circuit can not only sense the transient current on the printed circuit board level but also observe the transient current on the oscilloscope through a coaxial cable connection. Finally, experimental studies under an inductive load double pulse test setup with SiC mosfets are carried out to verify the validity and feasibility of the proposed transient current sensing circuit. Only a high self-resonant frequency inductor and a surface mounted device resistor are needed to form the LR network to fully compensate the effect of parasitic inductance on CSRs.

Surviving the Heat Wave – A presentation on thermally induced failures and reliability risks created by advancements in electronics technologies

Abstract Since the advent of surface mount technology back in the 1970's we, as an industry, have continually worked to miniaturize our products. This evolution of product design has impacted us at the semiconductor, package, circuit board and system levels. So, the question is, Why do Electronics Fail Under Thermal Cycling? At the semiconductor level, you can have issues with delamination, IC complexity, degradation mechanisms, associated ceramic capacitor wearout, and electrical overstress (EOS). At the package level issues with bond wires and stacked die add to the reliability impact. At the printed circuit board level issues with solder wearout, solder phase coarsening, PWB laminates and glass materials, plated through hole (PTH) fatigue, and the impact of potting can also affect reliability while at the system level, heat sinks and other methods of heat removal can improve the situation. What drives these issues is that we use a variety of materials e.g. semiconductors, ceramics, metals and polymers. We then bond them together with other materials like solder and adhesives. Each of these materials has a Coefficient of Thermal Expansion (CTE) that is unique and therefore expands and contracts at different rates.

Finite element modeling technique for avionics PCB with electronic components in random vibration environment

Electronic components normally experience functional failure due to vibration loads. To envisage the episode of this failure, it is necessary to estimate the vibration response of electronic components mounted on the printed circuit board (PCB). As a continuation to the research work which commenced with PCB level that unravelled the modeling mysteries concerned with accurate modeling of PCBs and their appropriate boundary conditions, the present work addressed the modeling issues allied to PCB with various electronic components having distinguished mounting configurations and are brought to reality with the abetment of Finite Element Analysis (FEA) and experimentation. Modeling approaches used in practice to address modeling part with regard to electronic components limit their scope to the extent of modal analysis. Unfortunately, information about a modeling option which yields to accurate prediction of vibration experienced by the electronic components is not available. Hence, objective of the current research work is to identify accurate & appropriate modeling approach for electronic components with the aid of FEA and experimentation. Comparison of frequencies and vibration response results is made for different modeling methodologies, including their ability of fetching the results swiftly and consistently in assortment with different component mounting configurations.

High-Efficiency PCB- and Package-Level Wireless Power Transfer Interconnection Scheme Using Magnetic Field Resonance Coupling

As technology develops, the number of chips increases while the thickness of mobile products continuously decreases, which leads to the need for high-density packaging techniques with high numbers of power and signal lines. By applying wireless power transfer technology at the printed circuit board (PCB) and package levels, the number of power pins can be greatly reduced to produce more space for signal pins and other components in the system. For the first time, in this paper, we propose and demonstrate a high-efficiency PCB- and package-level wireless power transfer interconnection scheme. We enhance the efficiency by applying magnetic field resonance coupling using a matching capacitor. The proposed scheme can replace a high number of power interconnections with rectangular spiral coils to wirelessly transfer power from the source to the receiver at the PCB and package levels. The equivalent circuit model is suggested with analytic equations, which is then analyzed to optimize the test vehicle design. For the experimental verification of the suggested model, the $Z$ -parameter results obtained from the model-based equation and measurement of the designed and fabricated test vehicles are compared at up to 1 GHz. The power transfer efficiency from the source coil to the receiver coil in this scheme is able to reach 85.6%. Finally, we designed and fabricated a CMOS full-bridge rectifier and mounted it on the receiver board to convert the transferred voltage from ac voltage to dc voltage. A measured dc voltage of 2.0 V is sufficient to operate the circuit, which generally consists of 1.5 V devices.

System-level simulation and implementation for a high Q capacitive accelerometer with PD feedback compensation

Based on the challenge of high-Q capacitive accelerometer, the analysis of the structure and the dynamic response of an all-silicon sandwich accelerometer are conducted. An analog closed-loop interface circuit based on proportional-differential feedback compensation is designed and simulated by SIMULINK/SIMSCAPE in order to stabilize the sensor and increase the closed-loop damping. Based on the design, a printed circuit board level circuit and an ASIC circuit are made for the test. Simulation and measurement are provided to support the design. Measurement results show that the circuit effectively improves the dynamic response time of the system. The accelerometer with ASIC circuit has the scale factor of 0.9976 V/g and the second order non-linearity of Â?400 ppm g/g2 in the range of ±1 g, the average noise floor is 2 μg/Â?Hz (0---200 Hz).

Analyzing and Mitigating the Near-field Radiations from PCB of GPS-based Vehicle Tracking System

The EMI/electromagnetic compatibility (EMC) analysis is becoming very important in today’s world of dense EMI environment. As we go toward accuracy and stability of any electronic product in dense EMI field, it is necessary to test it at printed circuit board (PCB) level. This paper describes the measurement technique of scanning of PCB using EMC Precision Scan Tool. The result of near-field measurement indicates the intensity of radiation of each component on PCB. This study is proposed to estimate the radiation field at component level. The near-field based techniques have been widely used in EMC studies because of the high accuracy and reliability. With appropriate model extraction and simulation tools, near-field scanning can be used to predict electromagnetic emissions. With proper shielding, the near-field radiations can be reduced. The near-field radiations can be used to predict far-field radiations from the system, before practically testing in EMI/EMC Laboratory or getting installed at end-user applications. Two models for global positioning system (GPS)-based vehicle tracking system used in research work have been proposed in this article. One is GPRS based and the other is SMS based, intended to be used in stringent environment and ground-based army vehicle. The near-field radiations have been taken at PCB level in dB ¼V for a range of 100 kHz-2.5 GHz frequency band. Maximum radiations of around 90–130 dB ¼V were found. The paper proposes Mu-metal and HE-30 shielding materials for mitigating low- and high-frequency radiations. The GPS VTS GPRS based board and GPS VTS SMS Tx board with HE-30 enclosures had been tested in national EMI Test Laboratory, Automotive Research Association of India (ARAI), for the frequency bands 100 KHz-2.5 GHz. The results had been compared with MIL-461E EMI/EMC standard, and had been found to be satisfactory. The low-frequency radiation level was found to be just within the acceptable limits as per the standard.

Efficient Evaluation of EM Radiation Associated With Information Leakage From Cryptographic Devices

This paper presents an efficient map generation technique for evaluating the intensity of electromagnetic (EM) radiation associated with information leakage for cryptographic devices at the printed circuit board level. First, we investigate the relation between the intensity of the overall EM radiation and the intensity of EM information leakage on a cryptographic device. For this purpose, we prepare a map of the magnetic field on the device by using an EM scanning system, after which we perform correlation electromagnetic analysis (CEMA) at all measurement points on the device, including points above the cryptographic module. The examined device is a standard evaluation board for cryptographic modules (side-channel attack standard evaluation board), where a cryptographic circuit is implemented on one of the field-programmable gate arrays on the board. With this experiment, we demonstrate that both an EM radiation map and an information leakage map can be generated simultaneously by scanning the board only once. We also confirm that the generated map is in good agreement with the corresponding map obtained from exhaustive CEMAs.

Chip-Level Design Constraints to Comply With Conducted Electromagnetic Emission Specifications

This paper deals with the reduction of the conducted electromagnetic emissions of microcontrollers caused by the core block switching. The relationship between the conducted emission at the printed circuit board level and the sources of switching noise at the chip level is evaluated through the analysis of an equivalent circuit that comprises an electric model of the internal building blocks of a microcontroller, the model of its package, and that of the board. The model of the integrated circuit is derived on the basis of functional specifications and technology parameters so that it can be extracted before chip manufacturing. By using this model, and knowing the electromagnetic emission limits to be met, the upper bound of the power supply current spectra of the core logic blocks is evaluated and the effectiveness of common spectrum shaping techniques, like the clock-skewing method or the spread-spectrum clock modulation, is discussed.

Numerical investigation on the thermal reliability and layout optimisation of printed circuit board level

The reliability of printed circuit board level is investigated through the optimisation of layout, power and heat dissipating. Different models of AMD HD5550 circuit module are built with different parameters combination based on computational fluid dynamics (CFD) theory. The thermal structures of these models are simulated by FLOTHERM. The result shows that thermal layout has a significant effect on the thermal reliability of the modules. The thickness of heat sink substrate also affects the temperature distribution of the board. The method and result supply a theoretical reference value for thermal design of the printed circuit board level.