Prefix Adders Research Articles

The Design of Digital System with CSA

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and ORAND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode

In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder structures is to present an accuracy configurable adder structure whose delay in the exact mode is almost the same as an exact adder. The efficacies of the proposed accuracy configurable adders are compared with some state-of-the-art adder structures using a 15nm CMOS technology. In addition, their efficacies are evaluated in two error-resilient applications. These studies show that the proposed carry-propagate adder has 22% (51%) lower energy consumption (error rate) compared to the best prior works. Also, the proposed parallel prefix adder provides, on average, 20% lower energy consumption compared to the exact parallel prefix adders.

VLSI Implementation of Ternary Operand Binary Addition Using Parallel Prefix Adder for Area Efficiency

Cryptographic applications and pseudo random generator perform modular arithmetic three operand is the basic fundamental unit used in all these applications. For performing three operand additions, CSA (carry save adder) is one of the most widely used adders[5]. But in CSA in the final stage, carry is propagated which impacts the delay. Prefix parallel adders are therefore employed to get around this. The parallel prefix adders use more space even though performance in terms of latency is improved. Parallel prefix adders can also be used to build three operand adders. A brand-new, high-speed, and hardware-efficient adder technique is used to boost performance in terms of latency and area. This adder approach uses four stages to achieve three operand addition. Since Han Carlson adder is used in third stage, the suggested adder is not area efficient. To overcome this, in this paper we are replacing the Han Carlson parallel prefix adder with sklansky adder.

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

The primary motive of this paper is to give the design and implementation of RNS (Residue Number System) based Area efficient and excessive-overall performance FIR filter of 4-tap, eight-tap, 16-tap of input eight bit. Additionally, RNS mathematics is a treasured device for theoretical research of the limits of fast mathematics. These proposed strategies additionally have a few additions operation, through the use of convention adder will decrease the speed of operation and additionally increase the number of logic gates. So, to conquer the one's issues we are using Ladner Fischer parallel prefix adder to lower the delay and area. First, the multiplier is designed through the use of RNS approach. In which the delay is decreased through 78.57% and power dissipation is likewise reduced to 64.65% for the RNS_PPA multiplier. A combination of those algorithms generates a brand-new structure of excessive speed and low implementation area in a single multiplier for FIR filter using Xilinx 14.7.

High Speed Approximate Carry Speculative Adder in Error Tolerance Applications

Approximate adders were proposed as feasible solution in error-tolerant applications to provide a proper trade-off with accuracy over other circuit-based metrics like energy, area, and delay. State of art of approximate adders are shown in this work to improve the operational features significantly. To acquire a most benefits of approximation, in this paper approximation at lower echelons is presented. Two speculative adders are proposed, one with approximate adder cell and other with Parallel prefix Adder cell. Gate level implementation of proposed model are designed and implemented. The cost functions are compared against various FPGA standard architectures. Results of proposed approach indicate an average of 46% improvement in Area Delay Product (ADP) and compared with existing approximate adders.

Early RTL delay prediction using neural networks

Nowadays, the digital chip design flow starts with formal specifications, which are mapped to Register Transfer Level (RTL) models using different underlying (micro-) architectures. By doing so, a hardware designer predicts and resolves time-critical parts to achieve an RTL-design that meets all constraints after synthesis. However, wrong predictions can be detected only later in the design flow, thus leading to long design iterations. Classical methods estimating delay in early design stages are constrained to the type of components or are computationally expensive for larger designs. This paper proposes a machine learning-based approach to estimate pin-to-pin delays for RTL combinational circuits. To improve the quality of the predictions we combine slew and delay estimation. To that end, training data are built using features of components generated by a model-driven hardware generator framework. Ground truth labels for delays, slews, and their interdependencies are extracted using open-source tools for logic synthesis and static timing analysis. Two different datasets are built: one targeting logic gates and multiplexers and an enlarged one, which generalizes to more RTL primitives A model trained using the former dataset achieves, on average, a coefficient of determination R2 of 87% when evaluating over 4-bit prefix adders. Using the enlarged dataset, the best model reaches an R2 of 77%. On average, our models are 8.4× faster w.r.t the time required to run synthesis and timing analysis. Results show that generalizing to more primitives decreases the models’ performance, but the runtime benefit is maintained. Based on the delay estimation, critical areas of the design can be detected and proper microarchitecture decisions can be taken earlier and faster in the design flow.

Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make C in = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques.

High-Speed Adder Design Space Exploration via Graph Neural Processes

Adders are the primary components in the data-path logic of a microprocessor, and thus, adder design has been always a critical issue in the very large-scale integration (VLSI) industry. However, it is infeasible for designers to obtain optimal adder architecture by exhaustively running EDA flow due to the extremely large design space. Previous arts have proposed the machine learning-based framework to explore the design space. Nevertheless, they fall into suboptimality due to a two-stage flow of the learning process and less efficient nor effective feature representations of prefix adder structures. In this article, we first integrate a variational graph autoencoder and a neural process (NP) into an end-to-end, multibranch framework, which is termed the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">graph neural process</i> . The former performs automatic feature learning of prefix adder structures, whilst the latter one is designed as an alternative to the Gaussian process. Then, we propose a sequential optimization framework with the graph NP as the surrogate model to explore the Pareto-optimal prefix adder structures with tradeoff among Quality-of-Result (QoR) metrics, such as power, area, and delay. The experimental results show that compared with state-of-the-art methodologies, our framework can achieve a much better Pareto frontier in multiple QoR metric spaces with fewer design-flow evaluations.

An Area Energy-Efficient VLSI Architecture using Hybrid Wide-Operand adder

Consumer electronics markets have raised demand for high-speed, low- power adders with big operands for use in new portable systems. Traditional fast adder architectures, such as parallelprefix adders, consume a lot of power when I have a lot of operands. One of the most promising ways for achieving a trade-off between delay and power consumption for the addition of big operands is the hybrid design. This reduces the area of the summation blocks at the significant positions without sacrificing speed. Furthermore, My provides a new hybrid adder architecture for large operands, based on the conceptthat in large parallel- prefix adders, the least significant carriers are produced considerably sooner than the most significant ones. As a result, the authors avoid incorporating fast architectures associated with the application of carries to the final summing leastsignificant bits, which has no effect on the critical path. of the carries is generated and propagated within the proposed adder's carry network to reduce delay. VLSI implementation results using 45- nm-TSMC technology reveal that the suggested adder saves more than 12% of energy and reduces the area-delay-product by more than 5% when compared to state-of-the-art other operand adders. The post- synthesis results of the proposed adder reported is much fasterthan the CS3A for 32-,64- and 128- bit architecture respectively. Moreover, it has a lesser area, lower power dissipation and smaller delay than the adder. Also, the proposed adder achieves the lowest ADP and PDP than the existing adder techniques.

Heuristic Analysis of Multiplierless Desensitized Half-Band Decimation Filter for Wireless Applications

This paper elucidates the half-band FIR filter, which plays an important role when applying decimation by a factor of two. When the down-conversion is applied in sampling rate, this digital filter is frequently employed in conjunction with down-samplers. Despite the fact that numerous approaches have been proposed for designing half-band FIR filters, this paper proposes an utterly unique method for designing and implementing multiplierless half-band FIR filters, which minimizes the coefficient sensitivity and also reduces hardware complexity of the conventional half-band FIR filter. The proposed desensitized and further desensitized multiplierless half-band FIR filters are analyzed with four high-speed parallel prefix adders in Xilinx Vivado development tool and built on Kintex 7 FPGA for exploring power consumption, number of LUTs and delay. The proposed half-band structure is compared with the classical half-band architecture with respect to power consumption, path delay and number of LUTs. Based on the attained results on Kintex 7 FPGA, the proposed low-sensitivity filter structure outperforms with a 41.09% reduction in the number of LUTs, a 11.91% reduction in delay and a 38.35% reduction in power consumption in contrast to the existing desensitized half-band filter. Subsequently, the proposed further desensitized filter provides a 4.87% reduction in stopband ripple than the desensitized structure and an 8.84% reduction than the existing half-band decimation filter.

High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic

Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.

Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the preprocessing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2n +1) adder design shows a 24.5% saving in area-delay-product (ADP).

A novel generic modulo‐2 graph with full set taxonomical conversion to parallel prefix adders

AbstractThis paper proposes a novel generic modulo‐2 graph that can be converted to parallel prefix adders (PPA). Also, a conversion algorithm for converting the proposed graph to PPAs is proposed in this paper. The conversation algorithm can be applied on N‐bit Generic modulo‐2 graph, and this graph is converted to N‐bit PPAs. When the proposed conversion algorithm is applied to generic modulo‐2 graph, this graph is converted to Brent‐Kung, Sklansky, Kogge‐Stone, Harris, Ladner‐Fischer, Han‐Carlson, and Knowles adders. Moreover, PPAs are shown in trilinear coordinates to represent the final PPAs, which generic graph converted to them. Furthermore, the add operation is done by generic graph and also the correctness of add function of this graph is investigated by “Boolean decision diagram.”

Probability-Driven Evaluation of Lower-Part Approximation Adders

Parallel prefix adder topologies suffer from carry chains forming critical paths, limiting the performance and therefore the efficiency. We study approximation methods that offload the lower-part of calculation to an approximate unit and shorten the carry chain. We derive their accuracy models using probability theory. These models can replace Monte Carlo simulations. Furthermore, they can reveal better accuracy trade-offs without going through the RTL design, synthesis, and simulation of each unit and approximation level individually. Thus, they can eliminate the required design and simulation time and effort. After analyzing area-wise comparisons at varying number of approximated bits, we show that choosing a design that outperforms the others probabilistically also outperforms them in terms of accuracy, power, and performance trade-offs.

Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders

In this paper a scheme for concurrent error detection (CED) in Ling parallel prefix adders is put forth leveraging the even-odd independence inherent in this class of adders. The proposed technique is based on the simplest form of fault detection i.e. duplicating and comparing results. This is achieved utilizing the unique even-odd independence feature in the Ling prefix structure. This feature is exploited to implement the fault tolerant Ling prefix adder with minimum overhead.The area and power overhead for CED are examined and results show that they reduce as the word size increases with the area overhead going down to less than 10% and power overhead to about 13% for a 64-bit adder. Delay is extraneous as the normal adder operation is not affected due to CED. The proposed fault tolerant adder design is compared with earlier schemes and results show that the proposed design gives an improvement of about 30% in area, 10% in PDP and about 40% in the ADP. Cadence Incisive Unified Simulator v6.1 is used for the functional simulation. Detailed analysis of the performance has been carried out at TSMC 180 nm process node (slow-normal library) using Cadence RTL compiler v7.1. Hardware synthesis has been performed to compute the metrics area, power and delay.

LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION

Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

PurposeDigital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.Design/methodology/approachThe distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.FindingsThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.Originality/valueThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration

This paper proposes a novel framework to design efficient variable-latency speculative adders based on a method that mixes serial/parallel prefix structures. In comparison to the conventional speculative parallel prefix adders, the proposed method eliminates the dependency of error signals, and the corresponding late completion error correction. In comparison to conventional variable latency speculative parallel prefix adders, the proposed method reduces energy-consumption by avoiding overlap in the processing of the sub-adders, overcoming the application of double prefix cell and duplicated gates. Moreover, with the proposed method, instead of having an error detection and correction circuit for low-probability errors, serial concatenations of sub-adders are considered for the worst-case. Experimental results show significant improvements in the Area-Delay Product (ADP) and Power-Delay Product (PDP) in comparison to the state-of-the-art variable latency speculative designs.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

PurposeIn this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.Design/methodology/approachThe modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.FindingsBoth RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.Originality/valueThe DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application

A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application